JPH06164342A - Clock signal generation circuit - Google Patents

Abstract

PURPOSE:To suppress the increase of futile power consumption by stopping the unnecessary operations of respective circuit blocks. CONSTITUTION:Corresponding to the values of the respective bit memory elements of a clock control register 6, internal clock signals 5-14 synchronized with reference clock signals 4-1-2 are outputted or stopped (high potential fixation or low potential fixation) by a clock driver circuit 3 and the operations of the respective circuit blocks to which the internal clock signals 5-1-4 are supplied are independently controlled.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a clock signal generation circuit used in a semiconductor integrated circuit such as a microprocessor which operates in synchronization with a fixed reference signal.

[0002]

2. Description of the Related Art In recent years, as semiconductor integrated circuits such as microprocessors have become faster and larger in scale, the frequency of a clock signal which is a reference signal for the operation of each part in the integrated circuit has also become higher. The increase in power consumption due to the increase is a problem. In addition, since very large-scale circuits are integrated, it is becoming very difficult to test / debug circuit operation, and how to efficiently perform test / debug has become a major issue.

An example of a conventional clock signal generation circuit will be described below with reference to the drawings. FIG. 2 shows an example of a conventional clock signal generation circuit. For simplification, a case where a two-phase clock signal is supplied to two circuit blocks will be described.

The reference clock generation circuit 2 is composed of an RS flip-flop circuit and a delay circuit, and generates the reference clock signals 4-1 and 4-2 in synchronization with the external clock signal 1. Reference clock signal 4-1 and internal clock signal 4-2
Is a two-phase clock signal that has no high potential at the same time. The reference clock signals 4-1 and 4-2 are input to the clock driver circuit 3, respectively. The clock driver circuit 3 is composed of a delay buffer circuit for correcting a clock skew due to a wiring delay to each circuit block that supplies a clock signal, and an internal clock signal 5-synchronized with a reference clock signal 4-1. 1 to 2 and internal clock signals 5-3 to 4 synchronized with the reference clock signal 4-2, and supply the clock signal to each circuit block constituting the integrated circuit.

[0005]

However, according to such a configuration, the clock signal is always supplied to all the circuit blocks, and all the circuit blocks to which the clock signal is supplied are necessary / unnecessary. Regardless, it will always do something. Usually, in a large-scale integrated circuit, it is rare that all the circuit blocks always operate, and such unnecessary circuit operation (operation that does not contribute to the operation of the entire integrated circuit) consumes unnecessary power. There was a problem of doing.

Further, at the time of testing / debugging an integrated circuit,
In order to efficiently test / debug a circuit, it is necessary to prevent the operation of the circuit block of interest (the one to be tested) from being affected by the operations of other circuit blocks as much as possible. In other words, the operation of each circuit block must be controlled as independently as possible during test / debug. But,
As described above, when all the circuit blocks are always operating, there is a problem that it is difficult to suppress the influence of the operation of circuits other than the circuit block of interest. Therefore, in a large-scale integrated circuit, it is often the case that a test-dedicated circuit that allows independent control of the operation of each circuit block is added to each circuit block. However, there was a problem that the performance deteriorated.

These problems have occurred for the following reasons. That is, since the clock signal supplied to each circuit block cannot be independently controlled (cannot be stopped), the clock signal is always supplied to all the circuit blocks, so that all the circuit blocks to which the clock signal is supplied are supplied. This is because there is always some action regardless of whether it is necessary or not.

The present invention has been made in consideration of the above-mentioned problems, and it suppresses unnecessary power consumption by stopping unnecessary operation of each circuit block to which a clock signal is supplied, and also performs test / debug. At times, it is an object to provide a clock signal generation circuit that can independently control the operation of each circuit block.

[0009]

In order to solve the above-mentioned problems, a clock signal generating circuit according to the present invention comprises a reference clock generating circuit which receives an external clock signal as an input and generates a reference clock signal synchronized with the external clock signal. A clock control register including a plurality of bit storage elements, and the reference clock signal and the value of each bit storage element of the clock control register as an input to the reference clock signal according to the value of each bit storage element of the clock control register. A clock driver circuit for independently outputting or stopping a plurality of synchronized internal clock signals is provided, and the internal clock signals are independently output or stopped according to the value of the clock control register.

[0010]

According to the present invention, since the plurality of internal clock signals are independently output or stopped according to the value of the clock control register according to the above-described configuration, the clock control register is provided for each time according to the necessity / non-necessity of the operation of each circuit block. By changing the value of, the internal clock signal supplied to the circuit block that does not need to operate can be stopped only during the period that does not need to operate.

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 shows the configuration of a clock signal generation circuit according to an embodiment of the present invention. For simplification, a case where a two-phase clock signal is supplied to two circuit blocks will be described.

In FIG. 1, 1 is an external clock signal, 2 is an internal reference clock generation circuit, 3 is a clock driver circuit, 4-1 and 2 are reference clock signals, 5-1 to 4 are internal clock signals, and 6 Is a clock control register, 7-1 and 2
Is a clock control signal.

The reference clock generation circuit 2 is composed of an RS flip-flop circuit and a delay circuit as in the conventional example.
Reference clock signal 4-1 in synchronization with external clock signal 1
Generate and output ~ 2. The reference clock signal 4-1 and the internal clock signal 4-2 are two-phase clock signals in which there is no period in which the potential becomes high simultaneously.

The clock control register 6 is composed of a plurality of bit storage elements, and outputs the contents of each bit storage element as clock control signals 7-1 and 2-1. The reference clock signals 4-1 and 4-2 and the clock control signals 7-1 and 2-1 are input to the clock driver circuit 3. The clock driver circuit 3 is composed of a multiplexer circuit and a delay buffer circuit, and the internal clock signal 5- is generated by the multiplexer circuit according to the values of the clock control signals 7-1 and 2.
The following three signals (or states) are switched as 1 to 4 and output.

(1) Signals synchronized with reference clock signals 4-1 and 2 (2) High potential fixed (3) Low potential fixed Internal clock signals 5-1 to 4 are supplied to each circuit block constituting the integrated circuit. It By changing the value of the clock control register 6 such that (1) is selected during the operation of the circuit block and (2) or (3) is selected during the operation of the circuit block, each circuit is selected. The clock signal supplied to each circuit block can be independently stopped (fixed to a high potential or fixed to a low potential) for each circuit block depending on whether the operation of the block is necessary or unnecessary.

In FIG. 1, since it is assumed that the two-phase clock signals are supplied to the two circuit blocks, the internal clock signal 5-1 and the internal clock signal 5-3, and the internal clock signal 5-2 and the internal clock signal 5-2. The clock signals 5-4 are controlled simultaneously.

[0018]

As described above, according to the present invention, a reference clock generation circuit which receives an external clock signal and generates a reference clock signal synchronized with the external clock signal,
A clock control register including a plurality of bit storage elements, and the reference clock signal and the value of each bit storage element of the clock control register as an input to the reference clock signal according to the value of each bit storage element of the clock control register. By providing a clock driver circuit that outputs or stops multiple synchronized internal clock signals independently of each other, the clock signal supplied to each circuit block is supplied to each circuit block according to the necessity / unnecessity of the operation of each circuit block. By independently stopping (fixing the high potential or fixing the low potential) each, it is possible to stop the unnecessary operation of the circuit block and suppress unnecessary power consumption. In particular, the effect is great in a CMOS integrated circuit or the like that consumes most of the power when switching the transistors inside the circuit.

At the time of testing / debugging an integrated circuit, it is possible to control the operation / stop of each circuit block independently by changing the value of the clock control register as described above. The influence of the operation of the circuit blocks other than the circuit block can be suppressed. In this case, since it is not necessary to change each circuit block by adding a circuit, the circuit performance (such as operation speed) does not deteriorate.

[Brief description of drawings]

FIG. 1 is a configuration diagram of a clock signal generation circuit according to an embodiment of the present invention.

FIG. 2 is a block diagram of a conventional clock signal generation circuit.

[Explanation of symbols]

 1 External Clock Signal 2 Reference Clock Generation Circuit 3 Clock Driver Circuit 4-1 to 2 Reference Clock Signal 5-1 to 4 Internal Clock Signal 6 Clock Control Register 7-1 to 2 Clock Control Signal

Claims (1)

[Claims] 1. A reference clock generation circuit for inputting an external clock signal to generate a reference clock signal synchronized with the external clock signal, a clock control register including a plurality of bit storage elements, the reference clock signal and the clock control. A clock driver circuit that inputs the value of each bit storage element of the register and independently outputs or stops a plurality of internal clock signals synchronized with the reference clock signal according to the value of each bit storage element of the clock control register. A clock signal generation circuit provided.