CN108762828B - DSP multi-core array secondary starting method and device - Google Patents
DSP multi-core array secondary starting method and device Download PDFInfo
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/44—Arrangements for executing specific programs
- G06F9/4401—Bootstrapping
- G06F9/4405—Initialisation of multiprocessor systems
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/44—Arrangements for executing specific programs
- G06F9/4401—Bootstrapping
- G06F9/4406—Loading of operating system
- G06F9/4408—Boot device selection
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/44—Arrangements for executing specific programs
- G06F9/445—Program loading or initiating
- G06F9/44521—Dynamic linking or loading; Link editing at or after load time, e.g. Java class loading
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/44—Arrangements for executing specific programs
- G06F9/445—Program loading or initiating
- G06F9/44568—Immediately runnable code
- G06F9/44578—Preparing or optimising for loading
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Abstract
The invention provides a DSP multi-core array secondary starting method and a device, wherein the method comprises the following steps: solidifying the pre-loaded user main program into a FLASH memory of an external host; solidifying the pre-loaded secondary boot program into an EEPROM memory of the DSP multi-core array; when the DSP multi-core array is started, generating a power-on reset signal and determining whether a DSP secondary starting mode is started or not; calling a secondary bootstrap program from the EEPROM memory to a RAM random access memory of the DSP multi-core array according to a power-on reset signal and DSP secondary starting mode information, starting and operating the secondary bootstrap program, and loading a user main program in the FLASH memory to a processor of the DSP multi-core array through the secondary bootstrap program; and starting and running the user main program in a processor of the DSP multi-core array. The invention adopts a secondary program loading starting mode to realize that the DSP multi-core array directly loads the user main program without depending on an external network and an external control device.
Description
Technical Field
The invention mainly relates to the technical field of program loading, in particular to a DSP multi-core array secondary starting method and device.
Background
With the development of modern science and technology, the wide application of high technology and technology in military war, the degree of dependence on electronic equipment is increased sharply, and electronic war has become a key factor influencing the victory or defeat of war. In the modern electronic countermeasure environment, the signal environment is dense and complex, new radar systems are continuously emerging, and the signal processing system gradually realizes high real-time performance, high reliability and miniaturization. Thus, the signal processing system needs to process a larger amount of data and has higher complexity, and therefore, the real-time signal processing system must have strong computing power.
At present, the system program can be loaded through the DSP multi-core array, but some problems exist, for example, when the DSP is an application of a single main control unit, the DSP multi-core array cannot load a user main program under the condition of no external network communication support and can realize the loading only by depending on the support of an external control device.
Disclosure of Invention
The invention aims to solve the technical problem of the prior art and provides a two-stage starting method and a two-stage starting device for a DSP multi-core array.
The technical scheme for solving the technical problems is as follows: a DSP multi-core array secondary starting method comprises the following steps:
solidifying the pre-loaded user main program into a FLASH memory of an external host;
solidifying the pre-loaded secondary boot program into an EEPROM memory of the DSP multi-core array;
when the DSP multi-core array is started, generating a power-on reset signal, and confirming whether a DSP secondary starting mode is started or not from a BIOS (Basic Input Output System);
calling a secondary bootstrap program from the EEPROM memory to a RAM random access memory of the DSP multi-core array according to a power-on reset signal and DSP secondary starting mode information, starting and operating the secondary bootstrap program, and loading a user main program in the FLASH memory to a processor of the DSP multi-core array through the secondary bootstrap program;
and starting and running the user main program in a processor of the DSP multi-core array.
The invention has the beneficial effects that: the method is characterized in that a secondary program loading starting mode is adopted, a user main program is solidified into a FLASH memory to be convenient for calling the user main program, a secondary bootstrap program is solidified into an EEPROM memory to be convenient for calling the secondary bootstrap program, and the DSP multi-core array is guided by the secondary bootstrap program to carry out secondary loading starting on the user main program, so that the DSP multi-core array directly loads the user main program, and the loading can be realized without depending on an external network and an external control device; the DSP starting option set in the BIOS can start a secondary starting mode of the DSP multi-core array according to the requirement, two running modes are provided, namely a conventional system starting mode and a starting mode of the embedded system which is started according to the requirement, and the application is flexible.
On the basis of the technical scheme, the invention can be further improved as follows.
Further, the loading the user main program in the FLASH memory into the processor of the DSP multi-core array through the secondary boot program specifically includes:
and loading the user main program in the FLASH memory into a processor of the DSP multi-core array through an SRIO serial interface and a secondary bootstrap program.
The beneficial effect of adopting the further scheme is that: and loading a large-capacity user main program into the DSP multi-core array through an SRIO serial interface.
Further, the solidifying the pre-loaded user main program into the FLASH memory of the external host specifically includes:
compiling a main program main.main.pjt of a user into a main.out file, generating a code main.hex which can be executed by a processor of the DSP multi-core array from the main.out file, and curing the code main.hex into a FLASH memory of an external host through an FPGA programmable device.
The beneficial effect of adopting the further scheme is that: the DSP multi-core array can load the user main program quickly and normally, and the running stability is improved.
Further, the step of solidifying the pre-loaded secondary boot program into the EEPROM memory of the DSP multi-core array specifically includes:
and pre-loading a secondary boot program through an I2C interface, and solidifying the secondary boot program into the EEPROM memory of the DSP multi-core array.
And calling a secondary boot program from the EEPROM memory to a RAM random access memory of the DSP multi-core array through an I2C interface.
The beneficial effect of adopting the further scheme is that: fast loading and invoking of the secondary boot program is accomplished using the I2C bus.
Further, the solidifying the secondary boot program into the EEPROM memory of the DSP multi-core array specifically includes:
compiling the secondary boot program 2boot.pjt into a 2boot.out file, generating a code 2boot.hex executable by a processor of the DSP multi-core array from the generated 2boot.out file, and solidifying the code 2boot.hex into an EEPROM memory of the DSP multi-core array through an I2C interface.
The beneficial effect of adopting the further scheme is that: the DSP multi-core array can be quickly and normally guided by the secondary bootstrap program to carry out secondary loading to start the user main program, so that the running stability is improved.
Another technical solution of the present invention for solving the above technical problems is as follows: a DSP multi-core array secondary starting device comprises:
the main program loading and curing module is used for curing the pre-loaded user main program into a FLASH memory of an external host;
the boot program loading and curing module is used for curing the pre-loaded secondary boot program into the EEPROM memory of the DSP multi-core array;
the signal acquisition module is used for generating a power-on reset signal when the DSP is started and confirming whether a DSP secondary starting mode is started from the BIOS;
the secondary starting module is used for calling a secondary bootstrap program from the EEPROM memory to a RAM random access memory of the DSP multi-core array according to a power-on reset signal and DSP secondary starting mode information, starting and operating the secondary bootstrap program, and loading a user main program in the FLASH memory to a processor of the DSP multi-core array through the secondary bootstrap program;
and the operation module is used for starting and operating the user main program in the processor of the DSP multi-core array.
The invention has the beneficial effects that: the method is characterized in that a secondary program loading starting mode is adopted, a user main program is solidified into a FLASH memory to be convenient for calling the user main program, a secondary bootstrap program is solidified into an EEPROM memory to be convenient for calling the secondary bootstrap program, and the DSP multi-core array is guided by the secondary bootstrap program to carry out secondary loading starting on the user main program, so that the DSP multi-core array directly loads the user main program, and the loading can be realized without depending on an external network and an external control device; the DSP starting option is set in the BIOS, the secondary starting mode of the DSP multi-core array can be started as required, two running modes are provided, and the application is flexible.
On the basis of the technical scheme, the invention can be further improved as follows.
The secondary starting module is specifically used for loading the user main program in the FLASH memory into the processor of the DSP multi-core array through the SRIO serial interface and the secondary bootstrap.
The beneficial effect of adopting the further scheme is that: and loading a large-capacity user main program into the DSP multi-core array through an SRIO serial interface.
Furthermore, the main program loading and curing module is specifically used for compiling the user main program main.pjt into a main.out file, generating a code main.hex executable by a processor of the DSP multi-core array from the main.out file, and curing the code main.hex into a FLASH memory of an external host through the FPGA programmable device.
The beneficial effect of adopting the further scheme is that: the DSP multi-core array can load the user main program quickly and normally, and the running stability is improved.
Further, the boot program loading and solidifying module is specifically configured to pre-load a secondary boot program through an I2C interface, and solidify the secondary boot program into an EEPROM memory of the DSP multi-core array.
And calling a secondary boot program from the EEPROM memory to a RAM random access memory of the DSP multi-core array through an I2C interface.
The beneficial effect of adopting the further scheme is that: fast loading and invoking of the secondary boot program is accomplished using the I2C bus.
Further, the bootstrap loading and curing module is specifically configured to compile a secondary bootstrap 2boot.pjt into a 2boot.out file, generate a code 2boot.hex executable by a processor of the DSP multi-core array from the generated 2boot.out file, and cure the code 2boot.hex into an EEPROM memory of the DSP multi-core array through an I2C interface.
The beneficial effect of adopting the further scheme is that: the DSP multi-core array can be quickly and normally guided by the secondary bootstrap program to carry out secondary loading to start the user main program, so that the running stability is improved.
Drawings
FIG. 1 is a flowchart of a method for secondary booting of a DSP multi-core array according to an embodiment of the present invention;
fig. 2 is a block diagram of a secondary startup device of a DSP multi-core array according to an embodiment of the present invention.
Detailed Description
The principles and features of this invention are described below in conjunction with the following drawings, which are set forth by way of illustration only and are not intended to limit the scope of the invention.
The DSP multi-core Array comprises a DSP processor, an FPGA (Field-Programmable Gate Array), a FLASH memory, an EEPROM (electrically Erasable Programmable read only memory), a RapidIO Switch and the like, and the DSP multi-core Array is communicated through the RapidIO Switch. A DSP processor such as a TMS320C6474 chip, wherein the TMS320C6474 chip supports three Boot start modes, namely an EMAC (Ethernet port) Boot mode, an SRIO (SRIO high speed serial IO) Boot mode and an I2C Boot mode;
in addition to the above three types of loading modes, the embodiment of the present invention further provides a secondary boot function of the DSP, and how to perform the secondary boot is described in detail below.
FIG. 1 is a flowchart of a method for secondary booting of a DSP multi-core array according to an embodiment of the present invention;
as shown in fig. 1, a two-stage starting method for a DSP multi-core array includes the following steps:
step S1: solidifying the pre-loaded user main program into a FLASH memory of an external host;
step S2: solidifying the pre-loaded secondary boot program into an EEPROM memory of the DSP multi-core array;
step S3: when the DSP multi-core array is started, generating a power-on reset signal, and determining whether to start a DSP secondary starting mode from the BIOS;
step S4: calling a secondary boot program from the EEPROM memory to a RAM random access memory of the DSP multi-core array according to a power-on reset signal and DSP secondary starting mode information;
step S5: starting and operating the secondary bootstrap program, and loading the user main program in the FLASH memory into a processor of the DSP multi-core array through the secondary bootstrap program;
step S6: and starting and running the user main program in a processor of the DSP multi-core array.
Specifically, in step S3, BOOTMODE [ 3: 0] is set to 0001b, i.e. the DSP secondary boot mode is turned on.
After the DSP multi-core array is powered on, a first section of codes is executed, a secondary bootstrap program is used as the first section of codes, and after the initialization of an external host CPU and related hardware, the solidified embedded user main program is loaded to the DSP.
In the embodiment, a secondary program loading mode is adopted, the user main program is solidified into the FLASH memory to be convenient for calling the user main program, the secondary bootstrap program is solidified into the EEPROM memory to be convenient for calling the secondary bootstrap program, and the DSP multi-core array is guided by the secondary bootstrap program to carry out secondary loading starting on the user main program, so that the user main program is directly loaded by the DSP multi-core array, and the loading can be realized without depending on an external network and an external control device; the DSP starting option is set in the BIOS, the secondary starting mode of the DSP multi-core array can be started as required, two running modes are provided, and the application is flexible.
Optionally, as an embodiment of the present invention, the loading, by the secondary boot program, the user main program in the FLASH memory into the processor of the DSP multi-core array specifically includes:
and loading the user main program in the FLASH memory into a processor of the DSP multi-core array through an SRIO serial interface and a secondary bootstrap program.
In the above embodiment, a large-capacity user main program is loaded into the DSP multi-core array through the SRIO serial interface.
Optionally, as an embodiment of the present invention, the solidifying the pre-loaded user main program into a FLASH memory of an external host specifically includes:
compiling a main program main.main.pjt of a user into a main.out file, generating a code main.hex which can be executed by a processor of the DSP multi-core array from the main.out file, and curing the code main.hex into a FLASH memory of an external host through an FPGA programmable device. Specifically, Main is a user defined name, a user Main program main.pjt can be compiled through CCS (code Composer studio) software to obtain a Main project file, the Main project file main.out generates a code main.hex executable by a processor of the DSP multi-core array through Hex6x.exe software, and the code main.hex is solidified into a FLASH memory of an external host through an FPGA programmable device.
In the embodiment, the DSP multi-core array can load the user main program quickly and normally, and the running stability is improved.
Optionally, as an embodiment of the present invention, the solidifying the pre-loaded secondary boot program into an EEPROM memory of the DSP multi-core array specifically includes:
and pre-loading a secondary boot program through an I2C interface, and solidifying the secondary boot program into the EEPROM memory of the DSP multi-core array.
And calling a secondary boot program from the EEPROM memory to a RAM random access memory of the DSP multi-core array through an I2C interface.
In the above embodiment, the I2C bus is used to implement fast loading and invoking of the secondary boot program.
Optionally, as an embodiment of the present invention, the solidifying the secondary boot program into an EEPROM memory of the DSP multi-core array specifically includes:
compiling the secondary boot program 2boot.pjt into a 2boot.out file, generating a code 2boot.hex executable by a processor of the DSP multi-core array from the generated 2boot.out file, and solidifying the code 2boot.hex into an EEPROM memory of the DSP multi-core array through an I2C interface.
Specifically, the secondary boot program 2boot.pjt can be compiled through ccs (code Composer studio) software to obtain a 2boot.out file, the 2boot.out file generates a code 2boot.
In the embodiment, the DSP multi-core array can be quickly and normally guided by the secondary bootstrap program to carry out secondary loading to start the user main program, so that the running stability is improved.
As shown in fig. 2, optionally, as another embodiment of the present invention, a DSP multi-core array secondary starting apparatus includes:
the main program loading and curing module is used for curing the pre-loaded user main program into a FLASH memory of an external host;
the boot program loading and curing module is used for curing the pre-loaded secondary boot program into the EEPROM memory of the DSP multi-core array;
the signal acquisition module is used for generating a power-on reset signal when the DSP is started and confirming whether a DSP secondary starting mode is started from the BIOS;
the secondary starting module is used for calling a secondary bootstrap program from the EEPROM memory to a RAM random access memory of the DSP multi-core array according to a power-on reset signal and DSP secondary starting mode information, starting and operating the secondary bootstrap program, and loading a user main program in the FLASH memory to a processor of the DSP multi-core array through the secondary bootstrap program;
and the operation module is used for starting and operating the user main program in the processor of the DSP multi-core array.
Optionally, as an embodiment of the present invention, the boot program loading and solidifying module is specifically configured to pre-load a secondary boot program through an I2C interface, and solidify the secondary boot program into an EEPROM memory of the DSP multi-core array.
And calling a secondary boot program from the EEPROM memory to a RAM random access memory of the DSP multi-core array through an I2C interface.
In the above embodiment, the I2C bus is used to implement fast loading and invoking of the secondary boot program.
Optionally, as an embodiment of the present invention, the secondary boot module is specifically configured to load the user main program in the FLASH memory into the processor of the DSP multi-core array through an SRIO serial interface and a secondary bootstrap.
In the above embodiment, a large-capacity user main program is loaded into the DSP multi-core array through the SRIO serial interface.
Optionally, as an embodiment of the present invention, the main program loading and curing module is specifically configured to compile a user main program main.pjt into a main.out file, generate a code main.hex executable by a processor of the DSP multi-core array from the main.out file, and cure the code main.hex into a FLASH memory of an external host through an FPGA programmable device.
Specifically, Main is a user defined name, a user Main program main.pjt can be compiled through CCS (codeComposer studio) software to obtain a Main project file, the Main project file main.out generates a code main.hex executable by a processor of the DSP multi-core array through Hex6x.exe software, and the code main.hex is solidified into a FLASH memory of an external host through an FPGA programmable device.
In the embodiment, the DSP multi-core array can load the user main program quickly and normally, and the running stability is improved.
Optionally, as an embodiment of the present invention, the boot program loading and curing module is specifically configured to compile a secondary boot program 2boot.pjt into a 2boot.out file, generate a code 2boot.hex executable by a processor of the DSP multi-core array from the generated 2boot.out file, and cure the code 2boot.hex into an EEPROM memory of the DSP multi-core array through an I2C interface.
In the embodiment, the DSP multi-core array can be quickly and normally guided by the secondary bootstrap program to carry out secondary loading to start the user main program, so that the running stability is improved.
The method adopts a secondary program loading mode, the user main program is solidified into the FLASH memory to be convenient for calling the user main program, the secondary bootstrap program is solidified into the EEPROM memory to be convenient for calling the secondary bootstrap program, and the DSP multi-core array is guided by the secondary bootstrap program to carry out secondary starting on the user main program, so that the DSP multi-core array directly loads the user main program, and the loading can be realized without depending on an external network and an external control device; the DSP starting option set in the BIOS can start a secondary starting mode of the DSP multi-core array according to the requirement, two running modes are provided, namely a conventional system starting mode and a starting mode of the embedded system which is started according to the requirement, and the application is flexible.
Each functional unit in the embodiments of the present invention may be integrated into one processing unit, or each unit may exist alone physically, or two or more units are integrated into one unit. The integrated unit can be realized in a form of hardware, and can also be realized in a form of a software functional unit.
The integrated unit, if implemented in the form of a software functional unit and sold or used as a stand-alone product, may be stored in a computer readable storage medium. Based on such understanding, the technical solution of the present invention essentially or partially contributes to the prior art, or all or part of the technical solution can be embodied in the form of a software product stored in a storage medium and including instructions for causing a computer device (which may be a personal computer, a server, or a network device) to execute all or part of the steps of the method according to the embodiments of the present invention. And the aforementioned storage medium includes: a U-disk, a removable hard disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a magnetic disk or an optical disk, and other various media capable of storing program codes.
While the invention has been described with reference to specific embodiments, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined by the appended claims. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.
Claims (6)
1. A two-stage starting method of a DSP multi-core array is characterized by comprising the following steps:
solidifying the pre-loaded user main program into a FLASH memory of an external host;
solidifying the pre-loaded secondary boot program into an EEPROM memory of the DSP multi-core array; the method specifically comprises the following steps: pre-loading a secondary bootstrap program through an I2C interface, and then solidifying the secondary bootstrap program into an EEPROM memory of the DSP multi-core array;
when the DSP multi-core array is started, generating a power-on reset signal, and determining whether to start a DSP secondary starting mode;
calling a secondary bootstrap program from the EEPROM memory to a RAM random access memory of the DSP multi-core array according to a power-on reset signal and DSP secondary starting mode information, starting and operating the secondary bootstrap program, and loading a user main program in the FLASH memory to a processor of the DSP multi-core array through the secondary bootstrap program; the loading the user main program in the FLASH memory into the processor of the DSP multi-core array through the secondary bootstrap program specifically includes: loading the user main program in the FLASH memory into a processor of the DSP multi-core array through an SRIO serial interface and a secondary bootstrap program;
and starting and running the user main program in a processor of the DSP multi-core array.
2. The DSP multi-core array secondary startup method of claim 1, wherein the solidifying of the pre-loaded user main program into a FLASH memory of an external host specifically comprises:
compiling a main program main.main.pjt of a user into a main.out file, generating a code main.hex which can be executed by a processor of the DSP multi-core array from the main.out file, and curing the code main.hex into a FLASH memory of an external host through an FPGA programmable device.
3. The DSP multi-core array secondary boot method according to claim 1, wherein the solidifying of the secondary boot program into the EEPROM memory of the DSP multi-core array specifically comprises:
compiling the secondary boot program 2boot.pjt into a 2boot.out file, generating a code 2boot.hex executable by a processor of the DSP multi-core array from the generated 2boot.out file, and solidifying the code 2boot.hex into an EEPROM memory of the DSP multi-core array through an I2C interface.
4. A DSP multi-core array secondary starting device is characterized by comprising:
the main program loading and curing module is used for curing the pre-loaded user main program into a FLASH memory of an external host;
the boot program loading and curing module is used for curing the pre-loaded secondary boot program into the EEPROM memory of the DSP multi-core array; specifically, a secondary boot program is pre-loaded through an I2C interface and is solidified into an EEPROM memory of the DSP multi-core array;
the signal acquisition module is used for generating a power-on reset signal when the DSP multi-core array is started and confirming whether a DSP secondary starting mode is started or not;
the secondary starting module is used for calling a secondary bootstrap program from the EEPROM memory to a RAM random access memory of the DSP multi-core array according to a power-on reset signal and DSP secondary starting mode information, starting and operating the secondary bootstrap program, and loading a user main program in the FLASH memory to a processor of the DSP multi-core array through the secondary bootstrap program; the secondary starting module is specifically used for loading the user main program in the FLASH memory into a processor of the DSP multi-core array through an SRIO serial interface and a secondary bootstrap program;
and the operation module is used for starting and operating the user main program in the processor of the DSP multi-core array.
5. The DSP multi-core array secondary starting device of claim 4, wherein the main program loading and curing module is specifically configured to compile a user main program main.pjt into a main.out file, generate the main.out file into a code main.hex executable by a processor of the DSP multi-core array, and cure the code main.hex into a FLASH memory of an external host through an FPGA programmable device.
6. The DSP multi-core array secondary boot apparatus according to claim 4, wherein the boot program loading and curing module is specifically configured to compile a secondary boot program 2boot.pjt into a 2boot.out file, generate a code 2boot.hex executable by a processor of the DSP multi-core array from the generated 2boot.out file, and cure the code 2boot.hex into an EEPROM memory of the DSP multi-core array through an I2C interface.
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| CN110007974B (en) * | 2019-03-29 | 2021-02-19 | 联想(北京)有限公司 | Method and device applied to starting of operating system and electronic equipment |
| CN109979411B (en) * | 2019-04-29 | 2021-03-12 | 上海天马有机发光显示技术有限公司 | Display panel, burning method and electrifying method of display panel |
| CN115543467A (en) * | 2022-11-30 | 2022-12-30 | 天津聚芯光禾科技有限公司 | Method for accelerating starting speed of switch |
| CN117215664B (en) * | 2023-08-21 | 2024-06-11 | 白盒子(上海)微电子科技有限公司 | Quick starting method for multi-core DSP of system on chip |
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| CN103631674A (en) * | 2012-08-24 | 2014-03-12 | 京信通信系统（中国）有限公司 | FPGA embedded in CPU and starting method thereof |
| CN105630530A (en) * | 2014-11-15 | 2016-06-01 | 航天恒星科技有限公司 | Multilevel boot method and system of digital signal processor |
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| CN103389914B (en) * | 2013-07-03 | 2015-10-21 | 浙江大学 | Based on the spaceborne triple-modular redundancy system of Clock Synchronization Technology |
| CN106210061A (en) * | 2016-07-14 | 2016-12-07 | 桂林长海发展有限责任公司 | A kind of automatic recognition system of undercarriage folding and unfolding |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN102662715A (en) * | 2012-04-23 | 2012-09-12 | 深圳市掌讯通讯设备有限公司 | Startup method for embedded operation system |
| CN102662717A (en) * | 2012-04-27 | 2012-09-12 | 深圳市掌讯通讯设备有限公司 | Bootstrap starting method of embedded system |
| CN102662718A (en) * | 2012-05-03 | 2012-09-12 | 天津市英贝特航天科技有限公司 | Module for starting multiple user programs by single Flash |
| CN103631674A (en) * | 2012-08-24 | 2014-03-12 | 京信通信系统（中国）有限公司 | FPGA embedded in CPU and starting method thereof |
| CN105630530A (en) * | 2014-11-15 | 2016-06-01 | 航天恒星科技有限公司 | Multilevel boot method and system of digital signal processor |
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