CN107239433A - A kind of triple redundance computer synchronous method - Google Patents
A kind of triple redundance computer synchronous method Download PDFInfo
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- CN107239433A CN107239433A CN201710419360.9A CN201710419360A CN107239433A CN 107239433 A CN107239433 A CN 107239433A CN 201710419360 A CN201710419360 A CN 201710419360A CN 107239433 A CN107239433 A CN 107239433A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
- G06F15/163—Interprocessor communication
- G06F15/173—Interprocessor communication using an interconnection network, e.g. matrix, shuffle, pyramid, star, snowflake
- G06F15/17306—Intercommunication techniques
- G06F15/17325—Synchronisation; Hardware support therefor
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
Abstract
A kind of triple redundance computer synchronous method, triple redundance computer is included：Decide by vote module, and completely identical in structure first CPU module, the second CPU module and the 3rd CPU module, decide by vote module and include three identical and separate redundancy voting units of structure, each voting unit includes high accuracy real-time clock and voting FPGA, each CPU module includes CPU board FPGA and processor, triple redundance computer realizes that clock pulses is synchronous according to multiple clock sources dynamic fault diagnosis and switching method, then triple redundance computer realizes the synchronization of software time benchmark in computer according to same homologous clock signal.The present invention can solve the problem that redundant computer clock redundancy and software synchronization problem, and cost is low, and reliability is high, simple and easy to apply.
Description
Technical field
The present invention relates to launch vehicle ＆ spacecraft computer system, more particularly to a kind of triple redundance computer synchronization side
Method.
Background technology
Due to redundant computer highly reliable with inexpensive unique advantage, following various types of Upper Stages,
Liquid mouse, solid vehicle, the sky of quick response penetrate small delivery and will tools on the heavy launcher of manned lunar exploration
It is widely used.
Apply with Chinese Space, scientific exploration, the development of manned space flight, international business's transmitting works with international partners increasingly
Deepen, carrier rocket launch mission is more and more, high density rapid fire turns into the development trend of carrier rocket.In improving
The integral level and ability of state's carrier rocket, meet the demand of space flight development in following 20-30 years, keep China's delivery technology to exist
The status of world's space industry, China has carried out new generation rapid fire carrier rocket.
Rapid fire carrier rocket of new generation requires highly reliable and low cost, shortens the lead time, and reduces to high-grade
The dependence of device.Using " integration, autonomous control, integrated, low cost " redundancy, domestic various delivery fire are can be applied to
The computer system of arrow or spacecraft.
Current redundant computer has that clock redundancy is asynchronous and the nonsynchronous problem of software, is needed in real time in controlling cycle
Ask in higher system, it is impossible to rapid failure diagnosis and decision-making are realized, simultaneously as asynchronous problem, redundant system has shape
State difference, increases the complexity of fault diagnosis.
The content of the invention
The present invention provides a kind of triple redundance computer synchronous method, can solve the problem that redundant computer clock redundancy and software are same
Step problem, cost is low, and reliability is high, simple and easy to apply.
In order to achieve the above object, the present invention provides a kind of triple redundance computer synchronous method, and triple redundance computer is included：
Decide by vote module, and completely identical in structure first CPU module, the second CPU module and the 3rd CPU module, voting module is included
Three identical and separate redundancy voting units of structure, each voting unit includes high accuracy real-time clock and table
Certainly FPGA, each CPU module includes CPU board FPGA and processor, and described synchronous method is comprised the steps of：
Step S1, triple redundance computer realize that clock pulses is synchronous according to multiple clock sources dynamic fault diagnosis and switching method；
Step S2, triple redundance computer realize the synchronization of software time benchmark in computer according to same homologous clock signal.
In described step S1, described multiple clock sources dynamic fault diagnosis is comprised the steps of with switching method：
CPU board FPGA in three CPU modules obtains three lock-out pulses that three voting units are sent in voting module respectively
Signal, selects one of synchronization pulse as the homologous clock signal of three CPU modules, is selected according to clock two from three
Logic is diagnosed to the synchronization pulse broken down, and synchronizes pulse signal according to the selection strategy of lock-out pulse
Switching.
The selection strategy of described lock-out pulse is included：
Switch synchronization pulse according to the priority orders of synchronization pulse set in advance, acquiescence uses excellent when upper electric
First level order highest synchronization pulse.
Described synchronization pulse failure is included：
The mistake pulse produced, pulse Chang Weigao, pulse is disturbed often to be arrived for low, pulse advancing, pulse is postponed till, pulse
Broaden and narrow with pulse.
Described synchronization pulse method for diagnosing faults is included：
Three CPU modules monitor the synchronization pulse received, measure its pulse width by the High Precision Crystal Oscillator of itself
Whether deviation allows within allowed band if the CPU module of more than 2 monitors that the width of some synchronization pulse exceedes
Scope, then judge that the synchronization pulse breaks down, then the switching of pulse synchronized according to the selection strategy of lock-out pulse.
In described step S2, realize that the method for software time reference synchronization in computer is comprised the steps of：
After step S2.1, three CPU module electrification resets, the monitoring software in processor starts compilation script to be copied from EEPROM
Shellfish monitoring software and flight software are into SRAM, and the monitoring software that brings into operation；
Flight software in step S2.2, three CPU modules all enters inquiry wait state, and monitoring software passes through three votings
FPGA carries out three machine data interactions, inquires about the starting state of three machines；
After step S2.3, the starting state of three machines prepare normally, three CPU modules start jointly, and monitoring software configuration starts
Receive synchronization pulse；
The flight software that step S2.4, three CPU board FPGA are obtained in same homologous clock signal progress timing, three machines starts
Synchronous operation.
Described synchronous method is also included：The synchronous method of flight software in the process of running, is comprised the steps of：
CPU board FPGA in each CPU module provides for corresponding processor comes from the homologous of same synchronization pulse
Clock signal, processor carries out timing according to homologous clock signal, when often reaching the triggered time, software interrupt is triggered, after interruption
The flight software in three machines is run simultaneously again, realizes that running software is synchronous.
The invention has the advantages that：
1st, high reliability
Using triple redundance computer synchronous method, it is ensured that triple redundance clock under malfunction, is keeping providing high once or twice
The synchronizing clock signals of precision.
2nd, simplification
Triple redundance computer synchronous method, it is not necessary to complicated hardware logic design, and the software and hardware degree of coupling is relatively low, hardware is main
There is provided homologous clock, software only needs to ensure that initial synchronisation starting point is counted jointly, can various high-precise synchronizations redundancy meter
It is applicable in calculation machine, design of hardware and software method is simple and easy to apply.
3rd, it is inexpensive
Delivery flight control computer is used as flight control core, it is desirable to high reliability, and the method used in the past is mainly the first device of raising
The crucial grade of part, and substantial amounts of screening, checking test, using three machine full redundancy schemes, can effectively improve system reliable
Property, degradation development cost expands competitiveness of the rocket in Business Launch Market, and then occupies more market shares.
Brief description of the drawings
Fig. 1 is the structural representation of triple redundance computer.
Fig. 2 is a kind of flow chart for triple redundance computer synchronous method that the present invention is provided.
Fig. 3 is the schematic diagram of lock-out pulse selection strategy.
Fig. 4 is the flow chart of pulse fault and impulsive switched.
Fig. 5 is electric clock synchronization schematic diagram on three machines.
Fig. 6 is electric operation logic figure on software.
Fig. 7 is initial power-on main software flow chart.
Fig. 8 is the synchronous schematic diagram of flight software in the process of running.
Embodiment
Below according to Fig. 1~Fig. 8, presently preferred embodiments of the present invention is illustrated.
As shown in figure 1, triple redundance computer is included：Voting module 4, and completely identical in structure first CPU module 1,
Second CPU module 2 and the 3rd CPU module 3.
Described voting module 4 includes three identical and separate redundancy voting units of structure, i.e.,：First table
Certainly the voting of unit 5, second unit 6 and the 3rd decides by vote unit 7.The first described voting unit 5 sends the first synchronization pulse
To the first CPU module 1, the second CPU module 2 and the 3rd CPU module 3, the second described voting unit 6 sends the second lock-out pulse
Signal gives the first CPU module 1, the second CPU module 2 and the 3rd CPU module 3, and the 3rd voting unit 7 sends the 3rd lock-out pulse letter
Number give the first CPU module 1, the second CPU module 2 and the 3rd CPU module 3, the first CPU module 1, the second CPU module 2 and the 3rd
Data interaction is carried out between CPU module 3 two-by-two.
Each described voting unit includes high accuracy real-time clock and voting FPGA, and FPGA is to high precision clock for voting
Output sync pulse signal is to the first CPU module 1, the second CPU module 2 and the 3rd after the High Precision Crystal Oscillator that source is provided is handled
CPU module 3.In the present embodiment, described high accuracy real-time clock uses 20MHz high stability crystal oscillators, and concrete model is ZC550-
20MHZ-5V-5ppm（Particular technique index：Stability：5PPM；Operating temperature range：-55℃~85℃；Operating voltage：5V）,
By crystal oscillator step-by-step counting, when being counted as 20 times, output 1ms clock pulses to the first CPU module 1, the and of the second CPU module 2
3rd CPU module 3.First voting unit 5 includes the first high accuracy real-time clock 8 and the first voting FPGA11, the second voting unit 6
Comprising the second high accuracy real-time clock 9 and the second voting FPGA12, the 3rd voting unit 7 includes the 3rd high accuracy real-time clock 10 and the
Three voting FPGA13.
Each described CPU module includes CPU board FPGA and processor, and CPU board FPGA is received from three votings
Three synchronization pulses of unit, are carried out after two from three voting to synchronization pulse, and output of pulse signal is given all the way for selection
Processor, realizes the synchronization of triple redundance computer.First CPU module 1 includes the first CPU board FPGA14 and first processor 17,
Second CPU module 2 includes the second CPU board FPGA15 and second processor 18, and the 3rd CPU module 3 includes the 3rd CPU board FPGA16
With the 3rd processor 19.
As shown in Fig. 2 the present invention provides a kind of triple redundance computer synchronous method, comprise the steps of：
Step S1, triple redundance computer realize that clock pulses is synchronous according to multiple clock sources dynamic fault diagnosis and switching method；
Step S2, triple redundance computer realize the synchronization of software time benchmark in computer according to same homologous clock signal.
In described step S1, described multiple clock sources dynamic fault diagnosis is comprised the steps of with switching method：
CPU board FPGA in three CPU modules obtains three lock-out pulses that three voting units are sent in voting module respectively
Signal, selects one of synchronization pulse as the homologous clock signal of three CPU modules, is selected according to clock two from three
Logic is diagnosed to the synchronization pulse broken down, and synchronizes pulse signal according to the selection strategy of lock-out pulse
Switching, it is ensured that triple redundance clock was there is provided continuous high-precision synchronizing clock signals under malfunction once or twice.
The selection strategy of described lock-out pulse is included：According to the priority orders of synchronization pulse set in advance come
Switch synchronization pulse, the use priority order highest synchronization pulse is given tacit consent to when upper electric.As shown in figure 3, first is same
The priority of step pulse signal is 1, and the priority of the second synchronization pulse is 2, and the priority of the 3rd synchronization pulse is
3, the switch sequence of synchronization pulse is 1->2,2->3、3->1, that is, the synchronization pulse for machine of holding power breaks down, three
CPU board FPGA in computer is independently decided by vote using another synchronization pulse, and three machine synchronised clock hardware ensure that error is small
In 10us.
Described synchronization pulse failure is included：Disturb the mistake pulse produced（The mistake pulse is due to that the machine of redundancy three is brilliant
Shake caused by solder joint loose contact and crystal oscillator hardware fault etc.）, pulse Chang Weigao, pulse often arrived for low, pulse advancing, pulse
Postpone till, pulse broadens and narrowed with pulse.
Described synchronization pulse method for diagnosing faults is included：Three CPU modules pass through the High Precision Crystal Oscillator of itself, prison
The synchronization pulse received is surveyed, the deviation of its pulse width is measured whether within allowed band（Tolerance 10%）If,
The CPU module of more than 2 monitors that the width of some synchronization pulse exceedes allowed band, then judges the synchronization pulse
Break down.
As shown in figure 4, on triple redundance computer after electricity, the CPU board FPGA in three CPU modules obtains three respectively simultaneously
Whether synchronization pulse, diagnosis has synchronization pulse to break down, and pulse is diagnosed successively, and whether whether Chang Weigao, pulse are normal
Come for whether low, pulse advances to, whether pulse is postponed till, whether pulse broadens with whether pulse narrows, if
There is no pulse signal to break down, then acquiescence uses the first synchronization pulse, if the first synchronization pulse used
Break down, be then switched to the second synchronization pulse, if the second synchronization pulse used breaks down, switch
To the 3rd synchronization pulse, if the 3rd synchronization pulse used breaks down, the first lock-out pulse is switched to
Signal, by that analogy.
In described step S2, realize that the method for software time reference synchronization in computer is comprised the steps of：
After step S2.1, three CPU module electrification resets, the monitoring software in processor starts compilation script to be copied from EEPROM
Shellfish monitoring software and flight software are into SRAM, and the monitoring software that brings into operation；
Flight software in step S2.2, three CPU modules all enters inquiry wait state, and monitoring software passes through three votings
FPGA carries out three machine data interactions, inquires about the starting state of three machines；
After step S2.3, the starting state of three machines prepare normally, three CPU modules start jointly, and monitoring software configuration starts
Receive synchronization pulse；
The flight software that step S2.4, three CPU board FPGA are obtained in same homologous clock signal progress timing, three machines starts
Synchronous operation.
As shown in figure 5, when the first CPU board FPGA, the second CPU board FPGA and same homologous the 3rd CPU board FPGA selections
Clock signal output is into the first CPU module, the second CPU module and the 3rd CPU module, for the external interrupt signal of software, makees
For the minimum time unit of software synchronization flow, the first CPU module, the second CPU module and the 3rd CPU module pass through three machines " number
According to interaction " notice of starting state is realized, after obtaining mutual software starting state and preparing normal, while using " synchronous
Pulse " carries out timing, it is ensured that in the synchronism of software time benchmark, the present embodiment, and the precision of synchronization pulse is 1ms.
As shown in Figure 6 and Figure 7, after computer electrification reset, monitoring software starts compilation script and copied from EEPROM first
Shellfish monitoring software, flight software bring into operation into SRAM, and from monitoring software, condition of the monitoring software in all interruptions masking
Lower carry out System self-test, three machines are due to the difference of hardware-initiated execution existence time, and software is generally different in practical situations both
Step state.
Three machine synchronizing steps are as follows：
A, three machine flight softwares inquire about other machine interactive interfaces of two machine three by " circular wait " state, change " electrifying startup shape
State is identified " variable；
B, when three machines get it is normal start mark when, exit " circular wait " state；
C, three machines bring into operation jointly, and configuration, which starts, receives 1ms synchronization pulses, and time error is less than 10us；
D, by obtaining the homologous clock pulse counts of 1ms, it is ensured that long-time clock jitter is respectively less than 10us.
Exist between three machines and start time error, the value that three machines start time error t1, t2 is less than ± 100us.
Triple redundance computer is in software running process, and the running software workflow in three CPU modules is inconsistent, deposits
In the inconsistent situation of operation branch, it is necessary to synchronize.A kind of triple redundance computer synchronous method that the present invention is provided may be used also
To realize the synchronization of flight software in the process of running, as shown in figure 8, specifically comprising the steps of：
CPU board FPGA in each CPU module provides the 1ms's that comes from same synchronization pulse for corresponding processor
Homologous clock signal, processor carries out timing according to homologous clock signal, often reaches the triggered time（Such as 20ms）When, trigger soft
Part is interrupted, and runs simultaneously the flight software in three machines after interruption again, realizes that running software is synchronous.
The method that the present invention is used, its advantage is：
1st, high reliability
Using triple redundance computer synchronous method, it is ensured that triple redundance clock under malfunction, is keeping providing high once or twice
The synchronizing clock signals of precision.
2nd, simplification
Triple redundance computer synchronous method, it is not necessary to complicated hardware logic design, and the software and hardware degree of coupling is relatively low, hardware is main
There is provided homologous clock, software only needs to ensure that initial synchronisation starting point is counted jointly, can various high-precise synchronizations redundancy meter
It is applicable in calculation machine, design of hardware and software method is simple and easy to apply.
3rd, it is inexpensive
Delivery flight control computer is used as flight control core, it is desirable to high reliability, and the method used in the past is mainly the first device of raising
The crucial grade of part, and substantial amounts of screening, checking test, using three machine full redundancy schemes, can effectively improve system reliable
Property, degradation development cost expands competitiveness of the rocket in Business Launch Market, and then occupies more market shares.
Although present disclosure is discussed in detail by above preferred embodiment, but it should be appreciated that above-mentioned
Description is not considered as limitation of the present invention.After those skilled in the art have read the above, for the present invention's
A variety of modifications and substitutions all will be apparent.Therefore, protection scope of the present invention should be limited to the appended claims.
Claims (7)
1. a kind of triple redundance computer synchronous method, it is characterised in that triple redundance computer is included：Decide by vote module, and structure
Identical first CPU module, the second CPU module and the 3rd CPU module, voting module are identical and mutual comprising structure
Three independent redundancy voting units, each voting unit includes high accuracy real-time clock and voting FPGA, each CPU mould
Block all includes CPU board FPGA and processor, and described synchronous method is comprised the steps of：
Step S1, triple redundance computer realize that clock pulses is synchronous according to multiple clock sources dynamic fault diagnosis and switching method；
Step S2, triple redundance computer realize the synchronization of software time benchmark in computer according to same homologous clock signal.
2. triple redundance computer synchronous method as claimed in claim 1, it is characterised in that described in described step S1
Multiple clock sources dynamic fault diagnosis is comprised the steps of with switching method：
CPU board FPGA in three CPU modules obtains three lock-out pulses that three voting units are sent in voting module respectively
Signal, selects one of synchronization pulse as the homologous clock signal of three CPU modules, is selected according to clock two from three
Logic is diagnosed to the synchronization pulse broken down, and synchronizes pulse signal according to the selection strategy of lock-out pulse
Switching.
3. triple redundance computer synchronous method as claimed in claim 2, it is characterised in that the selection plan of described lock-out pulse
Slightly include：
Switch synchronization pulse according to the priority orders of synchronization pulse set in advance, acquiescence uses excellent when upper electric
First level order highest synchronization pulse.
4. triple redundance computer synchronous method as claimed in claim 2, it is characterised in that described synchronization pulse failure
Comprising：
The mistake pulse produced, pulse Chang Weigao, pulse is disturbed often to be arrived for low, pulse advancing, pulse is postponed till, pulse
Broaden and narrow with pulse.
5. triple redundance computer synchronous method as claimed in claim 2, it is characterised in that described synchronization pulse failure
Diagnostic method is included：
Three CPU modules monitor the synchronization pulse received, measure its pulse width by the High Precision Crystal Oscillator of itself
Whether deviation allows within allowed band if the CPU module of more than 2 monitors that the width of some synchronization pulse exceedes
Scope, then judge that the synchronization pulse breaks down, then the switching of pulse synchronized according to the selection strategy of lock-out pulse.
6. triple redundance computer synchronous method as claimed in claim 1, it is characterised in that in described step S2, realizes meter
The method of software time reference synchronization is comprised the steps of in calculation machine：
After step S2.1, three CPU module electrification resets, the monitoring software in processor starts compilation script to be copied from EEPROM
Shellfish monitoring software and flight software are into SRAM, and the monitoring software that brings into operation；
Flight software in step S2.2, three CPU modules all enters inquiry wait state, and monitoring software passes through three votings
FPGA carries out three machine data interactions, inquires about the starting state of three machines；
After step S2.3, the starting state of three machines prepare normally, three CPU modules start jointly, and monitoring software configuration starts
Receive synchronization pulse；
The flight software that step S2.4, three CPU board FPGA are obtained in same homologous clock signal progress timing, three machines starts
Synchronous operation.
7. the triple redundance computer synchronous method as described in any one in claim 1-6, it is characterised in that described synchronization
Method is also included：The synchronous method of flight software in the process of running, is comprised the steps of：
CPU board FPGA in each CPU module provides for corresponding processor comes from the homologous of same synchronization pulse
Clock signal, processor carries out timing according to homologous clock signal, when often reaching the triggered time, software interrupt is triggered, after interruption
The flight software in three machines is run simultaneously again, realizes that running software is synchronous.
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Cited By (5)
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| CN109634097A (en) * | 2018-12-12 | 2019-04-16 | 上海航天控制技术研究所 | A kind of triple redundance interface circuit and synchronous method |
| CN113190082A (en) * | 2021-05-27 | 2021-07-30 | 上海航天计算机技术研究所 | Triple redundant computer clock interrupt detection and synchronization method and computer system |
| CN114115005A (en) * | 2021-11-12 | 2022-03-01 | 华东计算技术研究所（中国电子科技集团公司第三十二研究所） | Flight control task synchronization system and method based on three-CPU redundant architecture |
| CN115017071A (en) * | 2022-06-30 | 2022-09-06 | 重庆秦嵩科技有限公司 | Multi-CPU voting system based on FPGA SRIO |
| CN114115005B (en) * | 2021-11-12 | 2024-05-03 | 华东计算技术研究所（中国电子科技集团公司第三十二研究所） | Flight control task synchronization system and method based on three-CPU redundancy architecture |
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| CN114115005B (en) * | 2021-11-12 | 2024-05-03 | 华东计算技术研究所（中国电子科技集团公司第三十二研究所） | Flight control task synchronization system and method based on three-CPU redundancy architecture |
| CN115017071A (en) * | 2022-06-30 | 2022-09-06 | 重庆秦嵩科技有限公司 | Multi-CPU voting system based on FPGA SRIO |
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