CN109634097A - A kind of triple redundance interface circuit and synchronous method - Google Patents
A kind of triple redundance interface circuit and synchronous method Download PDFInfo
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- CN109634097A CN109634097A CN201811517471.4A CN201811517471A CN109634097A CN 109634097 A CN109634097 A CN 109634097A CN 201811517471 A CN201811517471 A CN 201811517471A CN 109634097 A CN109634097 A CN 109634097A
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
- G05B9/00—Safety arrangements
- G05B9/02—Safety arrangements electric
- G05B9/03—Safety arrangements electric with multiple-channel loop, i.e. redundant control systems
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01C—MEASURING DISTANCES, LEVELS OR BEARINGS; SURVEYING; NAVIGATION; GYROSCOPIC INSTRUMENTS; PHOTOGRAMMETRY OR VIDEOGRAMMETRY
- G01C21/00—Navigation; Navigational instruments not provided for in groups G01C1/00 - G01C19/00
- G01C21/10—Navigation; Navigational instruments not provided for in groups G01C1/00 - G01C19/00 by using measurements of speed or acceleration
- G01C21/12—Navigation; Navigational instruments not provided for in groups G01C1/00 - G01C19/00 by using measurements of speed or acceleration executed aboard the object being navigated; Dead reckoning
- G01C21/16—Navigation; Navigational instruments not provided for in groups G01C1/00 - G01C19/00 by using measurements of speed or acceleration executed aboard the object being navigated; Dead reckoning by integrating acceleration or speed, i.e. inertial navigation
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- Radar, Positioning & Navigation (AREA)
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Abstract
Triple redundance interface circuit of the invention includes completely identical in structure first interface circuit, second interface circuit and third interface circuit.Each interface circuit includes sensor data acquisition module, bus protocol communication module and FPGA module.Each FPGA module periodically generates synchronization pulse, the FPGA module being sent in other two-way interface circuits.Three synchronization pulses can be received in each FPGA module in this way, FPGA module will carry out the interpretation of " two from three " to these three synchronization pulses, and what which sentenced is the sequencing that synchronization pulse arrives.FPGA module is whenever receiving two from the synchronization pulse of distinct interface circuit, control bus protocol communication module delivers a packet to navigational computer, when FPGA module receives three synchronization pulses from three interface circuits, then restart the interpretation of a new round.
Description
Technical field
The present invention relates to a kind of launch vehicle & spacecraft inertial measurement combination systems, more particularly to a kind of triple redundance interface
Circuit synchronization method.
Background technique
Inertial measurement combination system is the core component of carrier rocket and spacecraft, is directly related to the success or failure of task, because
This proposes high requirement for measuring the reliability of combined system.
In order to improve reliability, device level redundancy can be used to important component by measuring in combined system.This technology
Embodiment in circuit is exactly using triple redundance interface circuit.Triple redundance interface circuit acquires same inertial sensor data
And by after protocol packing, it is sent to navigational computer.And the data sent to three interface circuits are carried out 3 in navigational computer
2 interpretation is taken, when can guarantee that an interface circuit breaks down in this way, navigation system be can still work normally.
But triple redundance scheme, because to carry out interpretation, the data synchronism of interface circuit proposes very high want
It asks.I.e. navigational computer must be consistent in the data of collected three interface circuits of synchronization, if three data
It is inconsistent, it will to cause to judge by accident in two from three interpretation.
Even if the synchronous core acquisition time of data is consistent, data synchronism needs are guaranteed by time synchronization measure.
Currently used triple redundance Time Synchronizing, when usually coming to carry out triple redundance circuit by the synchronic command of external circuit
Between synchronous and calibration.This solution increases the complexity of external navigation circuit, higher costs；And external sync is instructed
It excessively relies on, once synchronic command mistake, triple redundance circuit is by simultaneous faults, and there are single-point, reliability is insufficient.
To sum up, at present in inertial measurement combination system common triple redundance synchronization scheme there are it is at high cost, there are single-point, can
By the problem of property deficiency, need further to solve.
Summary of the invention
The present invention provides the triple redundance interface circuit synchronous method in a kind of inertial measurement combination, is able to solve most critical
Time synchronization problem, it is at low cost, high reliablity, simple and easy.
Triple redundance interface circuit of the present invention includes: first interface circuit, second interface circuit and third interface circuit；
The first interface circuit includes: first sensor data acquisition module, the first bus protocol communication module and
One FPGA module；
The second interface circuit includes: second sensor data acquisition module, the second bus protocol communication module and
Two FPGA modules；
The third interface circuit includes: 3rd sensor data acquisition module, third bus protocol communication module and
Three FPGA modules；
First sensor data acquisition module, second sensor data acquisition module, 3rd sensor data acquisition module
Input terminal respectively connect with the input terminal of inertial sensor, output end is respectively connect with the FPGA module of respective interface circuit；
First FPGA module, the second FPGA module, third FPGA module respectively by respective bus protocol communication module come
It is connected to navigational computer, and an input of an output end of the first FPGA module and the second FPGA module, third FPGA module
End connection, one output end of the second FPGA module are connect with an input terminal of the first FPGA module, third FPGA module, the 3rd FPGA
One output end of module is connect with an input terminal of the first FPGA module, the second FPGA module, and the one of each FPGA module is defeated
Outlet is connect with an input terminal of respective FPGA module.
Synchronous method of the present invention the following steps are included:
Step 1, each FPGA module periodically generate synchronization pulse, are sent in other two-way interface circuits
FPGA module and respective FPGA module input terminal；
Step 2 restarts timer；
Step 3 judges whether the lock-out pulse that two different FPGA modules are received within 1.5 periods；If then carrying out
Step 4；If it is not, then carrying out the operating mode of single FPGA module；
Step 4, control sensor data acquisition module complete inertial sensor data acquisition, then control bus protocol communication
Module delivers a packet to navigational computer；
Step 5 restarts timer；
Step 6 judges whether the lock-out pulse that the FPGA module not received in step 3 is received within 1.5 periods；If
It is to carry out step 2；If it is not, then carrying out the operating mode of two FPGA modules.
Preferably, the operating mode of single FPGA module is Fisrt fault prediction scheme, and step includes:
S1.1, judge whether to receive the lock-out pulse of itself；If so, carrying out S1.2；If it is not, then carrying out again
S1.1；
S1.2, control sensor data acquisition module complete inertial sensor data acquisition, then control bus protocol communication
Module delivers a packet to navigational computer, and executes S1.1 again.
Preferably, the operating mode of two FPGA modules is the second fault countermeasure, and step includes:
S2.1, judge that the pulse of which FPGA module does not receive, then the FPGA module is rejected from interpretation, only interpretation
Remaining two FPGA module lock-out pulses；
S2.2, restart timer；
S2.3, judge whether the lock-out pulse that two different FPGA modules are received within 1.5 periods；If then being walked
Rapid 2.4；If it is not, then carrying out the operating mode of single FPGA module；
S2.4, control sensor data acquisition module complete inertial sensor data acquisition, then control bus protocol communication
Module delivers a packet to navigational computer, and executes S2.2 again.
Preferably, the period of the pulse signal of each FPGA module is equal to the data update cycle of inertial sensor.
Compared with the prior art, the advantages of the present invention are as follows extraneous input is not depended on, structure is simple, at low cost；And have
There are once fault redundance ability, high reliablity.
Detailed description of the invention
Fig. 1 is the structural schematic diagram of triple redundance interface circuit synchronization scheme；
Fig. 2 is lock-out pulse " two from three " interpretation strategy schematic diagram；
Fig. 3 is the countermeasure of synchronization scheme under different faults；
Fig. 4 is " two from three " interpretation program flow diagram in FPGA.
Specific embodiment
In order to be easy to understand the technical means, the creative features, the aims and the efficiencies achieved by the present invention, tie below
Closing the drawings and specific embodiments, the present invention will be further described in detail, the range of but do not limit the invention in any way.
As shown in Fig. 1, triple redundance interface circuit of the present invention includes: first interface circuit, second interface circuit and third
Interface circuit；The first interface circuit includes: first sensor data acquisition module, the first bus protocol communication module and
One FPGA module；The second interface circuit includes: second sensor data acquisition module, the second bus protocol communication module and
Second FPGA module；The third interface circuit includes: 3rd sensor data acquisition module, third bus protocol communication module
And third FPGA module；First sensor data acquisition module, second sensor data acquisition module, 3rd sensor data are adopted
The input terminal of collection module is respectively connect with the input terminal of inertial sensor, and output end respectively connects with the FPGA module of respective interface circuit
It connects；First FPGA module, the second FPGA module, third FPGA module are respectively connected to by respective bus protocol communication module
Navigational computer, and an output end of the first FPGA module is connect with an input terminal of the second FPGA module, third FPGA module,
Second FPGA module, one output end is connect with an input terminal of the first FPGA module, third FPGA module, third FPGA module one
Output end is connect with an input terminal of the first FPGA module, the second FPGA module, and an output end of each FPGA module with
The input terminal connection of respective FPGA module.Wherein the period of the pulse signal of each FPGA module is equal to the number of inertial sensor
According to the update cycle.
As shown in Fig. 4, synchronous method of the present invention the following steps are included:
Step 1, each FPGA module periodically generate synchronization pulse, are sent in other two-way interface circuits
FPGA module and respective FPGA module input terminal；
Step 2 restarts timer；
Step 3 judges whether the lock-out pulse that two different FPGA modules are received within 1.5 periods；If then carrying out
Step 4；If it is not, then carrying out the operating mode of single FPGA module；
Step 4, control sensor data acquisition module complete inertial sensor data acquisition, then control bus protocol communication
Module delivers a packet to navigational computer；
Step 5 restarts timer；
Step 6 judges whether the lock-out pulse that the FPGA module not received in step 3 is received within 1.5 periods；If
It is to carry out step 2；If it is not, then carrying out the operating mode of two FPGA modules.
The operating mode of single FPGA module is Fisrt fault prediction scheme, and step includes:
S1.1, judge whether to receive the lock-out pulse of itself；If so, carrying out S1.2；If it is not, then carrying out again
S1.1；
S1.2, control sensor data acquisition module complete inertial sensor data acquisition, then control bus protocol communication
Module delivers a packet to navigational computer, and executes S1.1 again.
The operating mode of two FPGA modules is the second fault countermeasure, and step includes:
S2.1, judge that the pulse of which FPGA module does not receive, then the FPGA module is rejected from interpretation, only interpretation
Remaining two FPGA module lock-out pulses；
S2.2, restart timer；
S2.3, judge whether the lock-out pulse that two different FPGA modules are received within 1.5 periods；If then being walked
Rapid 2.4；If it is not, then carrying out the operating mode of single FPGA module；
S2.4, control sensor data acquisition module complete inertial sensor data acquisition, then control bus protocol communication
Module delivers a packet to navigational computer, and executes S2.2 again.
As shown in Fig. 2, " two from three " interpretation sentence be synchronization pulse arrive sequencing.With the first FPGA module
For.Under normal circumstances, it when FPGA module is whenever receiving two from the synchronization pulse of distinct interface circuit, that is, controls
Sensor data acquisition module processed completes inertial sensor data acquisition, then control bus protocol communication module is sent the packet within
To navigational computer.Next when FPGA module receives three synchronization pulses from three interface circuits, then again
The interpretation for starting " two from three " of a new round, starts waiting the arrival of lock-out pulse.Three interface circuits be all receive it is identical
Three synchronization pulses are all to start acquisition and transmission, therefore the letter of triple redundance circuit in second pulse signal arrival
Number acquisition time is consistent, can accomplish that signal is synchronous.
Synchronization pulse of the invention is anomaly divided into two kinds of situations, is to miss pulse and no pulse respectively.Such as 3 institute of attached drawing
Show, irregular may not be sent according to the period when there is accidentally pulse situation, certain road lock-out pulse.But of the invention " three take
Two " interpretations are just starting acquisitions when receiving two synchronization pulses for coming from " distinct interface circuit ", right in same period
The synchronization pulse interpretation of same circuit and only interpretation are primary, will not repeat interpretation.Therefore interface circuit will not be because of certain road
It misses pulse and mistakenly acquires and send data, it still can be according to set periodic duty.When there is no pulse situation, if certain
A interface circuit stops output lock-out pulse, and " two from three " the interpretation program inside FPGA module can pass through " time-out diagnoses " at this time
It detects corresponding failure, and takes corresponding second fault countermeasure, automatic " dimensionality reduction " guarantees remaining two-way normal interface circuit
It still can be realized time synchronization.When occurring under the extreme case of no pulse, if two interface circuits all stop working, at this time
" two from three " interpretation program inside unique normal FPGA module can take automatically Fisrt fault prediction scheme, only judge itself
Lock-out pulse can at least guarantee that remaining one piece of normal interface circuit can be worked normally by the period.
Program of the invention relies primarily on " time-out diagnoses " for the judgement of failure.Because of three synchronizations under normal circumstances
Pulse was externally sent according to the same fixed cycle.Program once can not all receive certain within 1.5 periods and synchronize all the way
Pulse, then may determine that no pulse failure occur for the road interface circuit, take corresponding fault countermeasure further according to fault condition.
Program can be jumped from normal mode into Fisrt fault prediction scheme and the second fault countermeasure.Second fault countermeasure can enter first
Fault countermeasure, but Fisrt fault prediction scheme cannot jump to other schemes.
It is discussed in detail although the contents of the present invention have passed through above-mentioned preferred embodiment, but it should be appreciated that above-mentioned retouches
It states and is not considered as limitation of the invention.After those skilled in the art have read above content, for of the invention a variety of
Modifications and substitutions all will be apparent.Therefore, protection scope of the present invention should be limited to the appended claims.
Claims (5)
1. a kind of triple redundance interface circuit is, characterized by comprising: first interface circuit, second interface circuit and third interface
Circuit；
The first interface circuit includes: first sensor data acquisition module, the first bus protocol communication module and first
FPGA module；
The second interface circuit includes: second sensor data acquisition module, the second bus protocol communication module and second
FPGA module；
The third interface circuit includes: 3rd sensor data acquisition module, third bus protocol communication module and third
FPGA module；
First sensor data acquisition module, second sensor data acquisition module, 3rd sensor data acquisition module it is defeated
Enter end respectively to connect with the input terminal of inertial sensor, output end is respectively connect with the FPGA module of respective interface circuit；
First FPGA module, the second FPGA module, third FPGA module are respectively connected by respective bus protocol communication module
To navigational computer, and an output end of the first FPGA module and an input terminal of the second FPGA module, third FPGA module connect
It connects, one output end of the second FPGA module is connect with an input terminal of the first FPGA module, third FPGA module, third FPGA module
One output end is connect with an input terminal of the first FPGA module, the second FPGA module, and an output end of each FPGA module
It is connect with an input terminal of respective FPGA module.
2. a kind of triple redundance interface circuit synchronous method, which is characterized in that utilize a kind of triple redundance interface described in claim 1
Circuit, synchronous method step include:
Step 1, each FPGA module periodically generate synchronization pulse, are sent in other two-way interface circuits
FPGA module and respective FPGA module input terminal；
Step 2 restarts timer；
Step 3 judges whether the lock-out pulse that two different FPGA modules are received within 1.5 periods；If then carrying out step
4；If it is not, then carrying out the operating mode of single FPGA module；
Step 4, control sensor data acquisition module complete inertial sensor data acquisition, then control bus protocol communication module
Deliver a packet to navigational computer；
Step 5 restarts timer；
Step 6 judges whether the lock-out pulse that the FPGA module not received in step 3 is received within 1.5 periods；If then
Carry out step 2；If it is not, then carrying out the operating mode of two FPGA modules.
3. a kind of triple redundance interface circuit synchronous method as claimed in claim 2, which is characterized in that the work of single FPGA module
Operation mode is Fisrt fault prediction scheme, and step includes:
S1.1, judge whether to receive the lock-out pulse of itself；If so, carrying out S1.2；If it is not, then carrying out again
S1.1；
S1.2, control sensor data acquisition module complete inertial sensor data acquisition, then control bus protocol communication module
Navigational computer is delivered a packet to, and executes S1.1 again.
4. a kind of triple redundance interface circuit synchronous method as claimed in claim 3, which is characterized in that the work of two FPGA modules
Operation mode is the second fault countermeasure, and step includes:
S2.1, judge that the pulse of which FPGA module does not receive, then the FPGA module is rejected from interpretation, only interpretation is remaining
Two FPGA module lock-out pulses；
S2.2, restart timer；
S2.3, judge whether the lock-out pulse that two different FPGA modules are received within 1.5 periods；If then carrying out step
2.4；If it is not, then carrying out the operating mode of single FPGA module；
S2.4, control sensor data acquisition module complete inertial sensor data acquisition, then control bus protocol communication module
Navigational computer is delivered a packet to, and executes S2.2 again.
5. such as a kind of described in any item triple redundance interface circuit synchronous method of claim 2-4, which is characterized in that each FPGA
The period of the pulse signal of module is equal to the data update cycle of inertial sensor.
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114043997A (en) * | 2022-01-13 | 2022-02-15 | 禾美(浙江)汽车股份有限公司 | Automatic driving intelligent decision-making method based on high-sensitivity sensor |
| CN114166223A (en) * | 2021-03-01 | 2022-03-11 | 四川航浩科技有限公司 | Airborne pod inertial navigation time service core processing unit and processing method |
| CN114253164A (en) * | 2020-09-23 | 2022-03-29 | 海鹰航空通用装备有限责任公司 | Compact dual-redundancy data acquisition unit |
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Application publication date: 20190416 |