CN104572331A - Monitoring module with power monitoring and electrifying delay enable - Google Patents
Monitoring module with power monitoring and electrifying delay enable Download PDFInfo
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- CN104572331A CN104572331A CN201510009532.6A CN201510009532A CN104572331A CN 104572331 A CN104572331 A CN 104572331A CN 201510009532 A CN201510009532 A CN 201510009532A CN 104572331 A CN104572331 A CN 104572331A
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Abstract
The invention provides a monitoring module with power monitoring and electrifying delay enable. The monitoring module is able to adjust watchdog electrifying cycle according to the starting time of an operation system. The monitoring module is characterized in that a power monitoring circuit and an electrifying delay enable control circuit are arranged between the module input end and the module output end; the power monitoring circuit is mainly composed of a power monitoring chip; the electrifying delay enable control circuit is mainly composed of a programmable device; the module input end is used as a system power signal acquiring end; one end of the module output end is connected to the programmable device, and while the other end of the module output end is connected to a CPU, a network card or enable ends of other system application program modules. According to the design, the monitoring module has the advantages that a multifunctional watchdog is achieved through the power monitoring chip and the programmable device, and the program problem and the problem caused by the inherent defects of a watchdog chip can be effectively reduced; in addition, the monitoring module is simple to operate and multifunctional, and can be applied to an embedded type hardware system.
Description
Technical field
The present invention relates to embedded system hardware design.Particularly a kind of house dog hardware design with power monitoring and delayed.
Background technology
Usually, by in the microcomputer system that single-chip microcomputer is formed, work due to single-chip microcomputer usually can be subject to the interference from external electromagnetic field, the race of program is caused to fly, and be absorbed in endless loop, the normal operation of program is interrupted, cannot be worked on by monolithic processor controlled system, that can cause whole system is absorbed in dead state, there is unpredictable consequence, so for consideration single-chip microcomputer running status being carried out to Real-Time Monitoring, just a kind of chip being specifically designed to monitoring Single Chip Microcomputer (SCM) program running status is created, be commonly called as " house dog " (English title watchdog).
House dog divides hardware watchdog and software watchdog.Hardware watchdog utilizes a timer circuit, its timing output is connected to the reset terminal of circuit, program resets (being commonly called as " feeding dog ") timer within the scope of certain hour, therefore when program normally works, timer always can not overflow (overflowing for " barking " hereinafter referred to as timer), also just can not produce reset signal.If program malfunctions, the house dog that do not reset in timing cycle (namely to timer reset), just makes WatchDog Timer overflow to produce reset signal to lay equal stress on starting system.The same in software watchdog principle, just the timer internal of the timer purpose processor on hardware circuit is replaced, can hardware circuit design be simplified like this.
Along with the development of embedded hardware technology, the hardware of embedded system becomes increasingly complex.If falling appears in the working power voltage of system, the input and output of some digit chips or sequential can be made to occur abnormal, and then cause the expiration operation even generation of major accident.
In prior art, embedded OS often needs the longer time just can complete the startup of whole system.Bootloader (referring to the first paragraph code that embedded system performs after power) mainly because of system performs, Kernel (referring to operating system nucleus) decompress(ion) performs and the loading of File Sytem (referring to file system) all needs the longer time to go.
Although watchdog chip special at present has monitoring voltage function, but " feed dog " of often chip the time interval is short and can not adjust, with conventional MAX706, (MAX706 is CMOS supervisory circuit, can monitoring power voltage, the duty of battery failures and microprocessor) be example, it " feeds dog ", and the cycle is only 1.6s.Reset if directly control host CPU with this watchdog chip, when being greater than 1.6s the start-up time of embedded OS, system is reset when also never call task of " feeding dog ", and so system cannot start and enters mode of operation.
Summary of the invention
The technical problem to be solved in the present invention be to provide a kind ofly can to adjust " feeding dog " cycle according to the start-up time of operating system there is power monitoring and the enable monitoring module of delayed.
In order to solve the problems of the technologies described above, the technical solution used in the present invention is:
Of the present invention have power monitoring and the enable monitoring module of delayed, comprises module input and module output terminal, be provided with electric source monitoring circuit and the enable control circuit of delayed between module input and module output terminal, wherein,
Electric source monitoring circuit is made up of power monitoring chip, the first resistance, the second resistance and the first electric capacity, the end of the first resistance connects with system power supply signals collecting end, and its other end is connected to the voltage input end of power monitoring chip and is connected with earth terminal by the second resistance; First electric capacity connects with the second resistor coupled in parallel;
The enable control circuit of delayed is made up of programming device, the 3rd resistance, the 4th resistance and the second electric capacity, 3rd resistance one end connects with operating voltage end, the other end is connected to the reset output terminal of power monitoring chip and is connected to the signal input part of programming device by the 4th resistance, and the second electric capacity is connected across between the signal input part of programming device and earth terminal;
Described module input is system power supply signals collecting end; Described module output terminal one end is connected to the reset output terminal of programming device, and the other end is connected to the Enable Pin of CPU, network interface card or other system application module respectively.
Described programming device is CPLD, field programmable gate array or single-chip microcomputer.
Described programming device is made up of with door at least two timers and one, and the reset output terminal of described power monitoring chip is connected to the clearing reset terminal of first timer and an input pin with door; The time of first timer overflows the start end being terminated at second timer, and the time of second timer overflows and is terminated at another input pin with door, and the clearing reset terminal of second timer is connected to an I/O pin of CPU; With the module output terminal that the input end of door is described.
The chip of described power monitoring chip to be model be IMP809.
Compared with prior art, the present invention is by adopting the combination of power monitoring chip and programming device, realize power monitoring and electrification reset function, its input signal is the to be monitored signal extracted by system works power supply, the output signal of power monitoring chip is the input end that electrification reset or Voltage Drop reset signal are connected to programming device, this signal sets up multiple counter and judge Compare Logic in programming device, completes that delayed is enable, " barking " threshold is adjustable, the function such as house dog and reset pulse generation.
Design of the present invention utilizes power monitoring chip and programming device to realize having the house dog of several functions, very effectively can reduce the problem that procedural problem and the defect of watchdog chip own may be brought.And realize simple and complete function.Be convenient to apply in embedded hardware system.
Accompanying drawing explanation
Fig. 1 is hardware elementary diagram of the present invention.
Fig. 2 is hardware embodiment schematic diagram of the present invention
Reference numeral is as follows:
Power monitoring chip U1, programming device U2, first timer Timer1, second timer Timer2, the first resistance R1R1, the second resistance R2, the 3rd resistance R3, the 4th resistance R4, the first electric capacity C1, the second electric capacity C2.
Embodiment
Below in conjunction with accompanying drawing, the present invention is described in detail.
The present invention obtains power monitoring signal by resistors match and is used for input power supervision chip U1, and power monitoring chip U1 signal exports and is connected with programming device U2 with build-out resistor through pull-up.Programming device U2 completes delayed according to the reset signal that power monitoring chip U1 provides, produces the watchdog functions such as reset signal.And complete " feeding dog " operation to programming device U2 by CPU.
As shown in Figure 1, the present invention realizes power monitoring by power monitoring chip U1 (its model is the supervision chip of IMP809), and it provides reset signal to programming device U2 [this programming device can be CPLD (English abbreviation CPLD), field programmable gate array (English abbreviation FPGA) or single-chip microcomputer]; By to the function such as programming device U2 programming realization delayed, threshold of barking is adjustable, system reset pulses generation.
What described power monitoring chip U1 monitoring voltage input end (also known as module input) connected is power supply voltage signal to be monitored, is realized the threshold voltage of power monitoring by the resistance of regulating resistance first resistance R1 and the second resistance R2.The output terminal of described power monitoring chip U1, by after the 3rd resistance R3 pull-up, is connected to the input end of programming device U2 by the 4th resistance R4.When threshold voltage lower than setting of the voltage of system electrification or monitoring voltage input end, power monitoring chip U1 output low level signal is to programming device U2.
As shown in Figure 2, the present invention by setting up several timers or counter completes the functions such as delayed is enable, house dog threshold is adjustable in programming device U2.
The structure of preferred programming device U2 is: it is made up of with door two timers and one, and the reset output terminal of described power monitoring chip U1 is connected to first timer Timer1 and resets reset terminal and an input pin with door; The time of first timer Timer1 overflows the start end being terminated at second timer Timer2, and the time of second timer Timer2 overflows and is terminated at another input pin with door, and the clearing reset terminal of second timer Timer2 is connected to an I/O end of CPU; With the module output terminal that the input end of door is described.
The reset output signal RST1 of power monitoring chip U1 causes programming device U2, and the reset output signal RST of programming device U2 causes other devices such as CPU, network interface card.
Power monitoring chip U1 power on or Voltage Drop time produce RST1 signal logic reset carried out to programming device U2.Reset output signal RST carries out electrification reset to other devices such as CPU, network interface card.
First timer Timer1 in the RST1 signal enabling programming device U2 that power monitoring chip U1 produces.First timer Timer1 starts timing, produces the signal starting second timer Timer2 after first timer Timer1 overflows.Second timer Timer2 starts timing immediately, after second timer Timer2 overflows, export reset pulse RST2.The threshold adjustable function of house dog is completed by the timing adjusting first timer Timer1 and second timer Timer2.
Inner at programming device U2, reseting pulse signal RST1 and RST2 by one two input with door, the signal exported with the output terminal (also known as module output terminal) of door is the reset RST signal of system.
The reset signal of second timer Timer2 is by the I/O foot control system of host CPU.Under normal circumstances, within a certain period of time, CPU controls the change of this I/O pin low and high level once, realizes resetting second timer Timer2, namely " feeds dog " and operates, and prevents second timer Timer2 from overflowing startup and exports reset pulse RST2.
Claims (4)
1. there is power monitoring and the enable monitoring module of delayed, comprise module input and module output terminal, it is characterized in that: between module input and module output terminal, be provided with electric source monitoring circuit and the enable control circuit of delayed, wherein,
Electric source monitoring circuit is made up of power monitoring chip (U1), the first resistance (R1), the second resistance (R2) and the first electric capacity (C1), the end of the first resistance (R1) connects with system power supply signals collecting end, and its other end is connected to the voltage input end of power monitoring chip (U1) and is connected with earth terminal by the second resistance (R2); First electric capacity (C1) and the second resistance (R2) are connected in parallel;
The enable control circuit of delayed is made up of programming device (U2), the 3rd resistance (R3), the 4th resistance (R4) and the second electric capacity (C2), 3rd resistance (R3) one end connects with operating voltage end, the other end is connected to the reset output terminal of power monitoring chip (U1) and passes through the signal input part that the 4th resistance (R4) is connected to programming device (U2), between the signal input part that the second electric capacity (C2) is connected across programming device (U2) and earth terminal;
Described module input is system power supply signals collecting end; Described module output terminal one end is connected to the reset output terminal of programming device (U2), and the other end is connected to the Enable Pin of CPU, network interface card or other system application module respectively.
2. according to claim 1 have power monitoring and the enable monitoring module of delayed, it is characterized in that: described programming device (U2) is CPLD, field programmable gate array or single-chip microcomputer.
3. according to claim 2 have power monitoring and the enable monitoring module of delayed, it is characterized in that: described programming device (U2) is made up of with door at least two timers and one, and the reset output terminal of described power monitoring chip (U1) is connected to the clearing reset terminal of first timer (Timer1) and an input pin with door; The time of first timer (Timer1) overflows the start end being terminated at second timer (Timer2), the time of second timer (Timer2) overflows and is terminated at another input pin with door, and the clearing reset terminal of second timer (Timer2) is connected to an I/O pin of CPU; With the module output terminal that the input end of door is described.
4. according to claim 1 have power monitoring and the enable monitoring module of delayed, it is characterized in that: described power monitoring chip (U1) for model be the chip of IMP809.
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| CN201510009532.6A CN104572331B (en) | 2015-01-08 | 2015-01-08 | The monitoring module enabled with power monitoring and delayed |
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Cited By (5)
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| CN106776096A (en) * | 2016-12-27 | 2017-05-31 | 兴唐通信科技有限公司 | A kind of Trusted recovery method of embedded software error |
| CN106933319A (en) * | 2016-11-25 | 2017-07-07 | 科诺伟业风能设备（北京）有限公司 | A kind of current transformer DSP electrification reset control methods |
| CN107329847A (en) * | 2017-06-05 | 2017-11-07 | 深圳市有方科技股份有限公司 | The supervisory circuit of control system |
| CN112269347A (en) * | 2020-12-24 | 2021-01-26 | 深圳市鼎阳科技股份有限公司 | Power-on and power-off time sequence control device |
| CN118393985A (en) * | 2024-06-27 | 2024-07-26 | 库卡机器人(广东)有限公司 | Reset device, robot, and reset method |
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| CN112269347A (en) * | 2020-12-24 | 2021-01-26 | 深圳市鼎阳科技股份有限公司 | Power-on and power-off time sequence control device |
| CN112269347B (en) * | 2020-12-24 | 2021-03-16 | 深圳市鼎阳科技股份有限公司 | Power-on and power-off time sequence control device |
| CN118393985A (en) * | 2024-06-27 | 2024-07-26 | 库卡机器人(广东)有限公司 | Reset device, robot, and reset method |
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| CN104572331B (en) | 2017-09-19 |
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