CN203535627U - Watchdog circuit - Google Patents
Watchdog circuit Download PDFInfo
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- CN203535627U CN203535627U CN201320614911.4U CN201320614911U CN203535627U CN 203535627 U CN203535627 U CN 203535627U CN 201320614911 U CN201320614911 U CN 201320614911U CN 203535627 U CN203535627 U CN 203535627U
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- watchdog
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Abstract
The utility model discloses a watchdog circuit. The watchdog circuit is used for carrying out monitoring reset on a central processing unit, and comprises a watchdog chip, an oscillating circuit, a counter and a shielding circuit, wherein the oscillating circuit is used for generating and outputting square signals, and the counter is used for receiving the square signals of the oscillating circuit, counting pulses of the square signals, and outputting level signals. According to the watchdog circuit, when the central processing unit is started, the counter is started to count the pulses of the square signals generated by the oscillating circuit, the counter outputs the low level to the shielding circuit so that the shielding circuit can carry out shielding on signals output by the watchdog chip, and the watchdog circuit can be prevented from carrying out resetting on the central processing unit in the starting process; after starting of the central processing unit is accomplished, the counter overflows and outputs the high level to the shielding circuit so that the shielding circuit can remove shielding carried out on the signals output by the watchdog chip, and the watchdog circuit can normally monitor operation of the central processing unit, and can carry out resetting on the central processing unit in an abnormal state.
Description
Technical field
The utility model relates to technical field of electronic equipment, particularly a kind of watchdog circuit.
Background technology
In hardware design, in order to increase the reliability of system, conventionally watchdog circuit to be set, its effect is to guarantee when central processing unit (CPU) program of electronic equipment crashes also to recover normal by Self-resetting.The ultimate principle of watchdog circuit is that, after central processing unit program crashes, central processing unit can not carry out regular zero clearing (be commonly called as and feed dog) to watchdog circuit, over watchdog circuit after certain hour, will reset to electronic equipment.
But slower owing to there being the system of operating system (OS) to start, in start-up course, have little time to feed dog, house dog just starts to have resetted, and causes system to be in the state of restarting always.The common way of head it off has two kinds at present, and the one, by CPLD (CPLD), in the process starting, close watchdog circuit after a period of time, after OS has started, then open watchdog circuit.The 2nd, by the software control of CPU, after OS starts, then open watchdog circuit.For way one, there are a lot of systems there is no CPLD, it is higher that increase CPLD realizes cost.Way two cannot realize watchdog function in CPU start-up course, and after simultaneously CPU starts, due to before CPU runs and fly, state unpredictable, cannot guarantee that whether house dog is in work, and reliability is poor.
Utility model content
Fundamental purpose of the present utility model is to provide a kind of watchdog circuit, is intended to improve the reliability of watchdog circuit and reduce costs.
To achieve these goals, the utility model provides a kind of watchdog circuit, and this watchdog circuit is for carrying out monitoring and reset to central processing unit, and it comprises:
Watchdog chip;
Oscillatory circuit, for generation of and export square-wave signal;
Counter, receives the square-wave signal of described oscillatory circuit and the pulse of square-wave signal is counted, and outputs level signals;
Screened circuit, comprise first input end, the second input end and output terminal, described first input end is for receiving the level signal of described counter output, described the second input end is for receiving the WDT of described watchdog chip output, when described screened circuit receives counter output high level, the output terminal of described screened circuit and described the second input end conducting, when described screened circuit receives the low level of counter output, the output terminal of described screened circuit and the cut-off of the second input end are also exported high level at the output terminal of screened circuit;
The output terminal of described oscillatory circuit is connected with the input end of counter, the output terminal of described counter is connected with the first input end of described screened circuit, the second input end of described screened circuit is connected with the WDT output terminal of described watchdog chip, the output terminal of described screened circuit is connected with the hand-reset end of described watchdog chip, and the reset signal output terminal of described watchdog chip is connected with described central processing unit.
Preferably, described oscillatory circuit comprises the first phase inverter, the first electric capacity and the first resistance, the input end of described the first phase inverter is through described the first capacity earth, the output terminal of described the first phase inverter is connected with described counter, and described output terminal is connected with the input end of described the first phase inverter through the first resistance.
Preferably, described the first phase inverter is schmitt inverter.
Preferably, described screened circuit comprises the second phase inverter, the first triode, the second triode, the 3rd triode, the second resistance, the 3rd resistance and the 4th resistance, the input end of described the second phase inverter is as the first input end of screened circuit, the base stage of described the first triode is connected with the output terminal of described the second phase inverter through described the second resistance, collector is connected with the base stage of the 3rd triode with the collector of described the second triode, grounded emitter; The base stage of described the second triode is as the second input end of described screened circuit, and collector is connected with external dc power through the 3rd resistance, grounded emitter; The collector of described the 3rd triode is as the output terminal of screened circuit and through the 4th resistance, be connected grounded emitter with external dc power.
Preferably, described counter comprises counting assentment end, and the output terminal of described the second phase inverter is connected with the counting of described counter assentment end.
Preferably, watchdog circuit also comprises a button, and one end of described button is connected with the hand-reset end of described watchdog chip, other end ground connection.
Preferably, the reset terminal of described counter is connected with the reset signal output terminal of described watchdog chip.
The utility model is by when central processing unit starts, opening counter counts the square-wave pulse of oscillatory circuit generation, counter output low level is to screened circuit, screened circuit is shielded the signal of watchdog chip output, prevent that watchdog circuit from resetting the central processing unit in starting.After central processing unit has started, counter overflow is also exported high level to screened circuit, make screened circuit stop the shielding to watchdog chip output signal, thereby make watchdog circuit can normally monitor the running of central processing unit the central processing unit that can reset under abnormality.This watchdog circuit running cost more reliable and that realize is lower.
Accompanying drawing explanation
Fig. 1 is the module diagram of the utility model watchdog circuit;
Fig. 2 is the structural representation of the utility model watchdog circuit one embodiment.
The realization of the utility model object, functional characteristics and advantage, in connection with embodiment, are described further with reference to accompanying drawing.
Embodiment
Should be appreciated that specific embodiment described herein is only in order to explain the utility model, and be not used in restriction the utility model.
The utility model provides a kind of watchdog circuit.
With reference to Fig. 1 and 2, Fig. 1 is the module diagram of the utility model watchdog circuit; Fig. 2 is the structural representation of the utility model watchdog circuit one embodiment.The watchdog circuit that the present embodiment provides, for central processing unit is carried out to monitoring and reset, comprises watchdog chip U1, oscillatory circuit 1, counter U2 and screened circuit 2,
Watchdog chip U1, it should be noted that watchdog chip U1 can select according to actual conditions, as long as this chip can be realized the central processing unit that operation is monitored and can be resetted under abnormality to central processing unit.In the present embodiment, chip model is MAX706.This chip comprises hand-reset end/MR, reset signal output terminal/RST and WDT output terminal MDO.When watchdog chip U1 monitors central processing unit less than normal hello dog, WDT output terminal MDO is by output low level signal.When hand-reset end/MR is low level, reset signal output terminal/RST is by output low level, and low level output, to central processing unit, resets central processing unit.
Counter U2, receives the square-wave signal of oscillatory circuit 1 and the pulse of square-wave signal is counted, then in output terminal outputs level signals.This counter U2 it should be noted that counter U2 can select according to actual conditions, as long as can realize the pulse of square-wave signal is counted.In the present embodiment, counter U2 adopts 74LVC161.The TC end of the corresponding 74LVC161 counter of the output terminal U2 of its Counter U2, i.e. terminal count output.When counting full 16 to square-wave pulse, counter U2 overflows, at TC end output high level.When counter U2 to square-wave pulse counting less than 16 time, in TC end output low level.
Screened circuit 2, comprise first input end, the second input end and output terminal, first input end is for the level signal of count pick up device U2 output, the second input end is for receiving the WDT of watchdog chip U1 output, when screened circuit 2 receives counter U2 output high level, the output terminal of screened circuit 2 and the second input end conducting.When screened circuit 2 receives the low level of counter U2 output, the output terminal of screened circuit 2 and the cut-off of the second input end are also exported high level at the output terminal of screened circuit 2.
The output terminal of oscillatory circuit 1 is connected with the input end of counter U2, the output terminal of counter U2 is connected with the first input end of screened circuit 2, the second input end of screened circuit 2 is connected with the WDT output terminal MDO of watchdog circuit, the output terminal of screened circuit 2 is connected with hand-reset end/MR of watchdog chip U1, and reset signal output terminal/RST of watchdog chip U1 is connected with central processing unit.
When central processing unit is during in starting state, start counter U2, the pulse of the square-wave signal that counter U2 will produce oscillatory circuit 1 be counted, and output low level is to screened circuit 2.When screened circuit 2 receives low level signal, output terminal and the first input end of controlling screened circuit 2 disconnect and export high level to hand-reset end/MR of watchdog chip U1, thereby have shielded the reset signal that watchdog chip U1 sends to central processing unit.After central processing unit has started, counter U2 will overflow, and output low level signal is to screened circuit 2.Screened circuit 2 receives the low level signal of counter U2 output, the output terminal of controlling screened circuit 2 is communicated with its second input end, be hand-reset end/MR that the signal of watchdog chip U1 signal output part output transfers to watchdog chip U1, make watchdog chip U1 normally monitor the running status of central processing unit and central processing unit is resetted under abnormal state.
The utility model is by when central processing unit starts, the synchronous counter U2 that starts counts the square-wave pulse of oscillatory circuit 1 generation, counter U2 output low level is to screened circuit 2, the signal of 2 pairs of watchdog chip U1 outputs of screened circuit is shielded, prevent that watchdog circuit from resetting the central processing unit in starting.After central processing unit has started, counter U2 overflows and exports high level to screened circuit 2, make screened circuit 2 stop the shielding to watchdog chip U1 output signal, thereby make watchdog circuit can normally monitor the running of central processing unit the central processing unit that can reset under abnormality.This watchdog circuit running realizes more reliable with respect to software of the prior art, and realization is with low cost.
Further, oscillatory circuit 1 comprises the first phase inverter I1, the first capacitor C 1 and the first resistance R 1, the input end of the first phase inverter I1 is through the first capacitor C 1 ground connection, and its output terminal is connected with counter U2, and output terminal is connected with the input end of the first phase inverter I1 through the first resistance R 1.
In the present embodiment, oscillatory circuit 1 is for generation of square-wave signal, and this first phase inverter I1 is 74LVC1G14 schmitt inverter, and this chip comprises power end, earth terminal, input end and output terminal.Power end is connected with external dc power, usually, external dc power is+3.3V(under with), earth terminal ground connection.Under original state, the input end of schmitt inverter is low level, and low level is exported high level after schmitt inverter, and high level feeds back to input end and the first capacitor C 1 is charged through the first resistance R 1.After the first capacitor C 1 charging, make the input end of schmitt inverter become high level, high level again after this phase inverter, output terminal output low level.Due to the low level state of output terminal, the first capacitor C 1 will be by the first resistance R 1 electric discharge.After the first capacitor C 1 electric discharge, the input end of schmitt inverter returns to again low level state.Go round and begin again, make the square-wave pulse signal of the output terminal output low and high level of schmitt inverter.This square-wave pulse signal exports counter U2 to.
Further, screened circuit 2 comprises the second phase inverter I2, the first triode Q1, the second triode Q2, the 3rd triode Q3, the second resistance R 2, the 3rd resistance R 3 and the 4th resistance R 4.The input end of the second phase inverter I2 is as the first input end of screened circuit 2.The base stage of the first triode Q1 is connected with the output terminal of the second phase inverter I2 through the second resistance R 2, and collector is connected with the collector of the second triode Q2, the base stage of the 3rd triode Q3, grounded emitter.The base stage of the second triode Q2 is as the second input end of screened circuit 2, and collector is connected with external dc power through the 3rd resistance R 3, grounded emitter.The collector of the 3rd triode Q3 is as the output terminal of screened circuit 2 and through the 4th resistance R 4, be connected grounded emitter with external dc power.
In the present embodiment, when central processing unit is during in starting state, counter U2 does not overflow, counter U2 output low level to the second phase inverter I2.The output terminal of the second phase inverter I2 is by the base stage of output high level to the first triode Q1.The first triode Q1 emitter positively biased, makes collector and the emitter conducting of the first triode Q1, and collector draws as low level.The collector of the first triode Q1 is connected with the base stage of the 3rd triode Q3.The current collection of the first triode Q1 is low level very, thereby makes the emitter junction of the 3rd triode Q3 anti-inclined to one side, and the current collection of the 3rd triode Q3 is high level very.The high level of the collector of the 3rd triode Q3 will export hand-reset end/MR of watchdog chip U1 to, and hand-reset end/MR is high level, thereby shielded watchdog circuit, central processing unit is sent to reset signal.After central processing unit has started, counter U2 overflows and exports high level to the second phase inverter I2.The base stage of the second phase inverter I2 output low level to the first triode Q1.The first triode Q1 emitter junction is anti-inclined to one side, the collector of the first triode Q1 and emitter is disconnected, thereby removed the state that the 3rd triode Q3 base stage level is dragged down, and has removed the shielding of 2 pairs of watchdog chip U1 output signals of screened circuit.The signal output part of watchdog chip U1 is connected with the base stage of the second triode Q2, signal, by the hand-reset end/MR that transfers to watchdog chip U1 by the second triode Q2, the 3rd triode Q3, normally monitors watchdog circuit to central processing unit.
Further, watchdog circuit also comprises a button SW, and one end of button SW is connected with hand-reset end/MR of watchdog chip U1, other end ground connection.
In the present embodiment, when unusual condition appears in whole circuit, can also to central processing unit, reset by button SW.When button SW presses down, hand-reset end/MR of watchdog chip U1 is low level, and watchdog chip U1 sends reset signal to central processing unit.The setting of this button SW, makes the reliability of whole watchdog circuit stronger.
Further, counter U2 also comprises a counting assentment end CEP, and when counting assentment end CEP is low level, counter U2 stops counting.When counting assentment end CEP is high level, counter U2 starts counting.In the present embodiment, the second phase inverter I2 output terminal in screened circuit 2 is connected with the counting assentment end CEP of counter U2.After central processing unit has started, counter U2 overflows and exports high level to the second phase inverter I2.The output terminal output low level of the second phase inverter I2.Because the output terminal of the second phase inverter I2 holds CEP to be connected with counting assentment, when counting assentment end CEP is low level, stop counter U2 counting.
Further, the reset terminal MR of counter U2 and reset signal output terminal/RST of watchdog chip U1 are connected.When central processing unit resets, counter U2 synchronously resets, and is about to counter U2 zero clearing.When central processing unit starts, counter U2 synchronize with central processing unit and start counting.After central processing unit starts, counter U2 stops counting.Zero clearing again and again, count and stop counting.
The foregoing is only preferred embodiment of the present utility model; not thereby limit the scope of the claims of the present utility model; every equivalent structure transformation that utilizes the utility model instructions and accompanying drawing content to do; or be directly or indirectly used in other relevant technical fields, be all in like manner included in scope of patent protection of the present utility model.
Claims (7)
1. a watchdog circuit, for central processing unit is carried out to monitoring and reset, comprises watchdog chip, it is characterized in that, also comprises:
Oscillatory circuit, for generation of and export square-wave signal;
Counter, receives the square-wave signal of described oscillatory circuit and the pulse of square-wave signal is counted, and outputs level signals;
Screened circuit, comprise first input end, the second input end and output terminal, described first input end is for receiving the level signal of described counter output, described the second input end is for receiving the WDT of described watchdog chip output, when described screened circuit receives counter output high level, the output terminal of described screened circuit and described the second input end conducting, when described screened circuit receives the low level of counter output, the output terminal of described screened circuit and the cut-off of the second input end are also exported high level at the output terminal of screened circuit;
The output terminal of described oscillatory circuit is connected with the input end of counter, the output terminal of described counter is connected with the first input end of described screened circuit, the second input end of described screened circuit is connected with the WDT output terminal of described watchdog chip, the output terminal of described screened circuit is connected with the hand-reset end of described watchdog chip, and the reset signal output terminal of described watchdog chip is connected with described central processing unit.
2. watchdog circuit as claimed in claim 1, it is characterized in that, described oscillatory circuit comprises the first phase inverter, the first electric capacity and the first resistance, the input end of described the first phase inverter is through described the first capacity earth, the output terminal of described the first phase inverter is connected with described counter, and described output terminal is connected with the input end of described the first phase inverter through the first resistance.
3. watchdog circuit as claimed in claim 2, is characterized in that, described the first phase inverter is schmitt inverter.
4. watchdog circuit as claimed in claim 1, it is characterized in that, described screened circuit comprises the second phase inverter, the first triode, the second triode, the 3rd triode, the second resistance, the 3rd resistance and the 4th resistance, the input end of described the second phase inverter is as the first input end of screened circuit, the base stage of described the first triode is connected with the output terminal of described the second phase inverter through described the second resistance, collector is connected with the base stage of the 3rd triode with the collector of described the second triode, grounded emitter; The base stage of described the second triode is as the second input end of described screened circuit, and collector is connected with external dc power through the 3rd resistance, grounded emitter; The collector of described the 3rd triode is as the output terminal of screened circuit and through the 4th resistance, be connected grounded emitter with external dc power.
5. watchdog circuit as claimed in claim 4, is characterized in that, described counter comprises counting assentment end, and the output terminal of described the second phase inverter is connected with the counting of described counter assentment end.
6. watchdog circuit as claimed in claim 1, is characterized in that, also comprises a button, and one end of described button is connected with the hand-reset end of described watchdog chip, other end ground connection.
7. the watchdog circuit as described in claim 1 to 6 any one, is characterized in that, the reset terminal of described counter is connected with the reset signal output terminal of described watchdog chip.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201320614911.4U CN203535627U (en) | 2013-09-29 | 2013-09-29 | Watchdog circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201320614911.4U CN203535627U (en) | 2013-09-29 | 2013-09-29 | Watchdog circuit |
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| Publication Number | Publication Date |
|---|---|
| CN203535627U true CN203535627U (en) | 2014-04-09 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201320614911.4U Expired - Fee Related CN203535627U (en) | 2013-09-29 | 2013-09-29 | Watchdog circuit |
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| CN (1) | CN203535627U (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104750568A (en) * | 2015-04-14 | 2015-07-01 | 广州市智博光辉电气科技有限公司 | Abnormal forced resetting type watchdog circuit of microcontroller |
| CN111061590A (en) * | 2019-12-20 | 2020-04-24 | 威创集团股份有限公司 | Control method and system of watchdog circuit |
-
2013
- 2013-09-29 CN CN201320614911.4U patent/CN203535627U/en not_active Expired - Fee Related
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104750568A (en) * | 2015-04-14 | 2015-07-01 | 广州市智博光辉电气科技有限公司 | Abnormal forced resetting type watchdog circuit of microcontroller |
| CN104750568B (en) * | 2015-04-14 | 2019-03-26 | 广东正力通用电气有限公司 | A kind of watchdog circuit of microcontroller exception forced resetting |
| CN111061590A (en) * | 2019-12-20 | 2020-04-24 | 威创集团股份有限公司 | Control method and system of watchdog circuit |
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| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| C56 | Change in the name or address of the patentee | ||
| CP01 | Change in the name or title of a patent holder |
Address after: 518057, Shenzhen Province, Nanshan District hi tech Zone, Guangdong hi tech Zone, No. 9, building 8, East Patentee after: BANGYAN TECHNOLOGY CO., LTD. Address before: 518057, Shenzhen Province, Nanshan District hi tech Zone, Guangdong hi tech Zone, No. 9, building 8, East Patentee before: Shenzhen Bangyan Information Technology Co., Ltd. |
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| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20140409 Termination date: 20170929 |
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| CF01 | Termination of patent right due to non-payment of annual fee |