CN205121468U - System resets based on programmable logic chip - Google Patents

Abstract

The utility model discloses a system resets based on programmable logic chip, including programmable logic chip, CPU chip, crystal oscillator, the restore to the throne chip and the button that restores to the throne, the reset signal of the chip that restores to the throne output is connected to CPU chip and programmable logic chip, and hello the dog signal of CPU chip, the clock signal that crystal oscillator exported and the output signal who restores to the throne the button all are connected to programmable logic chip, output connection to the chip that restores to the throne of programmable logic chip " feeding the dog end ". The built -in logic gate of programmable logic chip and adjustable frequency divider, counter, crystal oscillator's clock signal become low frequency signals through the frequency divider, transmit for logic gate through the counter again, and logic gate will come from feeding the output signal of dog signal, counter and restore to the throne the output signal of button and carrying out the logic AND and calculate of CPU, signal output to the chip that restores to the throne after will calculating. The utility model relates to a nimble, accommodation is wide, and the interference killing feature is strong.

Description

A kind of resetting system based on programmable logic chip

Technical field

The utility model relates to a kind of resetting system based on programmable logic chip.

Background technology

Reset circuit is the basic circuit of electric intelligent device indispensability.Generally need to reset to device under three kinds of states: reset under electrification reset, deadlock state and artificial button reset.The repositioning method of existing electric intelligent device is generally monitored by the operation of reset chip to CPU, and CPU feeds dog by I/O mouth to reset chip, and the output signal of reset key is received on the hand-reset pin of reset chip.

This pattern has following defect:

1, " house dog " time of existing reset chip is generally 1.6 seconds (namely in 1.6 seconds not to reset chip " feed dog " then reset chip reset CPU), and in the electric intelligent device of some complexity, CPU program may arrive several seconds start-up time, tens seconds even tens seconds, and CPU program " can not feed dog " to reset chip before running.Obviously, existing design cannot meet the demands;

2, the hand-reset pin due to reset chip is more responsive, if reset key is interfered or touches by mistake, very easily cause reset chip " to reset " by mistake, thus cause CPU restart routine, if at this moment electric intelligent device is performing the mission critical such as outlet, locking, catastrophic effect will produced;

3, can only monitor the operation of CPU, and in electric intelligent device, the effect that programmable logic chip plays in systems in which more and more important (as analog acquisition, performing outlet action etc.), should increase the supervision to programmable logic chip running status.

Utility model content

The utility model is in order to solve the problem, propose a kind of resetting system based on programmable logic chip, native system utilizes programmable logic chip can the feature of flexible programming, programmable logic chip is introduced reset circuit design in, have adapt to wide, reliability is high, monitor comprehensive feature.

To achieve these goals, the utility model adopts following technical scheme:

A kind of resetting system based on programmable logic chip, comprise programmable logic chip, cpu chip, crystal oscillator, reset chip and reset key, wherein, programmable logic chip connects crystal oscillator, cpu chip and reset chip, the reset signal that reset chip exports passes to cpu chip and programmable logic chip, the output signal of the clock signal that the feeding-dog signal of cpu chip, crystal oscillator export and reset key all transfers to programmable logic chip, and the output terminal of programmable logic chip is connected to reset chip " feeding dog end ".

The built-in frequency divider of described programmable logic chip, counter and logic gates, the clock signal that crystal oscillator provides becomes through frequency divider can for the low frequency signal of reset chip identification, and described low frequency signal is transferred to logic gates by counter.

Described counter, before counting down to setting value, exports the signal from frequency divider, after counting down to setting value, exports high level signal always.

Described logic gates carries out logic and operation to the signal that the output signal of reset key, the feeding-dog signal sum counter of cpu chip export, and the signal that logical operation produces is outputted to reset chip.

The frequency-adjustable of described output signal of frequency divider, the setting value of counter is adjustable.

The beneficial effects of the utility model are:

(1) frequency divider, counter set point is adjustable, before counter counts counts to setting value, programmable logic chip can export feeding-dog signal to reset chip always, avoids reset chip to reset before cpu chip starts, and can adapt to CPU program and start longer occasion consuming time;

(2) feeding-dog signal is sent into programmable logic chip by cpu chip, after internal logic process, reset chip is sent a signal to again by programmable logic chip, then cpu chip and any one operation exception of programmable logic chip, reset chip all can reset, thus can be monitored the ruuning situation of two chips by reset chip;

(3) dog that feeds of the output signal of reset key and other signal logics and rear access reset chip is held, instead of by the hand-reset end of the signal of reset key access reset chip, reset key can being avoided to cause because being subject to ringing reset chip to reset, improve the reliability of system cloud gray model;

(4) solve that complication system program power-on time is long, button reset signal is easily disturbed, can only monitors the problems such as CPU, extend application scenario, improve dirigibility and reliability.

Accompanying drawing explanation

Fig. 1 is the general illustration of repositioning method described in the utility model;

Fig. 2 is the schematic diagram of the function that the utility model realizes based on programmable logic chip.

Embodiment:

Below in conjunction with accompanying drawing and embodiment, the utility model is described in further detail.

As shown in Figure 1, cpu chip, programmable logic chip, reset key, reset chip and crystal oscillator form complete resetting system.Programmable logic chip can adopt CPLD or FPGA, and crystal oscillator generally adopts the active crystal oscillator of 50MHz.The reset pin of reset chip connects cpu chip and programmable logic chip, the clock signal of the feeding-dog signal of cpu chip, the output signal of reset key and crystal oscillator all enters programmable logic chip, is given hello the dog pin of reset chip by output signal after programmable logic chip process.After device powers on, first reset chip resets (continuing about 200ms) to cpu chip and programmable logic chip.Afterwards, the program of cpu chip and programmable logic chip all starts to start, and program start-up time extremely short (being less than 1 millisecond) of programmable logic chip, therefore first the program of programmable logic chip brings into operation.

As shown in Figure 2, the clock signal of the 50MHz of crystal oscillator is input to the frequency divider of programmable logic chip inside, can obtain 10KHz signal (frequency values is adjustable), then export counter to through frequency divider frequency division.The signal A exported by counter, the feeding-dog signal B of cpu chip output, the output signal C of reset key are all connected to logic gates, produce signal D by after logic gates process, and D will output to hello the dog pin of reset chip as final feeding-dog signal.The logical formula of logic gates is as follows:

D＝A&B&C。

The counter of programmable logic chip inside generally sets a count value.After program is run, counter starts to count the 10KHz signal of input.When rolling counters forward does not arrive setting value, the 10KHz signal that frequency division obtains by counter directly outputs to logic gates, because now CPU program not yet starts, reset key is unattended, then signal B, C is high level, then by D=A & B & C, then signal D just equals signal A, is delivered to by 10KHz signal reset chip " feeding dog end ".After the counting of counter reaches setting value, fractional frequency signal no longer exports and directly output signal is set to high level by counter, and if at this moment CPU start to feed dog, then according to the formula of logic gates, D output be the feeding-dog signal B of CPU.If cpu chip or programmable logic chip operation exception, then D cannot export effective feeding-dog signal, then reset chip exceedes " house dog " time (being generally 1.6 seconds) and resets afterwards.If during the normal program operation of CPU program and programmable logic chip, press reset key and become low level by making the output signal of reset key, then according to logical formula, signal D is low level always, namely reset chip cannot detect effective feeding-dog signal, then reset chip starts timing, until reach " house dog " time of reset chip, reset chip just exports reset signal, and general glitch is difficult to continue so long, therefore, this design is difficult to " being resetted " by mistake, improves system rejection to disturbance ability.

In fig. 2, due to inner frequency divider, counter set point is adjustable, therefore the utility model can adapt to longer occasion CPU program start-up time, and feeding-dog signal is sent into programmable logic chip by CPU, output signal to reset chip after treatment by programmable logic chip again, then can be monitored the ruuning situation of two chips by reset chip.And the output signal of reset key only has the duration to exceed " house dog " time, reset chip just can be made to send reset signal, add reliability undoubtedly.

By reference to the accompanying drawings embodiment of the present utility model is described although above-mentioned; but the restriction not to the utility model protection domain; one of ordinary skill in the art should be understood that; on the basis of the technical solution of the utility model, those skilled in the art do not need to pay various amendment or distortion that creative work can make still within protection domain of the present utility model.

Claims (5)

1. the resetting system based on programmable logic chip, it is characterized in that: comprise programmable logic chip, cpu chip, crystal oscillator, reset chip and reset key, wherein, programmable logic chip connects crystal oscillator, cpu chip and reset chip, the reset signal that reset chip exports passes to cpu chip and programmable logic chip, the feeding-dog signal of cpu chip, the output signal of the clock signal that crystal oscillator exports and reset key all transfers to programmable logic chip, the output terminal of programmable logic chip is connected to reset chip " feeding dog end ".

2. a kind of resetting system based on programmable logic chip as claimed in claim 1, it is characterized in that: the built-in frequency divider of described programmable logic chip, counter and logic gates, the clock signal that crystal oscillator provides becomes through frequency divider can for the low frequency signal of reset chip identification, and described low frequency signal is transferred to logic gates by counter.

3. a kind of resetting system based on programmable logic chip as claimed in claim 2, is characterized in that: described counter, before counting down to setting value, exports the signal from frequency divider, after counting down to setting value, exports high level signal always.

4. a kind of resetting system based on programmable logic chip as claimed in claim 1, it is characterized in that: described logic gates carries out logic and operation to the signal that the output signal of reset key, the feeding-dog signal sum counter of cpu chip export, and the signal that logical operation produces is outputted to reset chip.

5. a kind of resetting system based on programmable logic chip as claimed in claim 2, it is characterized in that: the frequency-adjustable of described output signal of frequency divider, the setting value of counter is adjustable.