CN111061590A - Control method and system of watchdog circuit - Google Patents
Control method and system of watchdog circuit Download PDFInfo
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- CN111061590A CN111061590A CN201911328683.2A CN201911328683A CN111061590A CN 111061590 A CN111061590 A CN 111061590A CN 201911328683 A CN201911328683 A CN 201911328683A CN 111061590 A CN111061590 A CN 111061590A
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- control unit
- watchdog circuit
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
- G06F11/0751—Error or fault detection not based on redundancy
- G06F11/0754—Error or fault detection not based on redundancy by exceeding limits
- G06F11/0757—Error or fault detection not based on redundancy by exceeding limits by exceeding a time limit, i.e. time-out, e.g. watchdogs
Abstract
The invention relates to the technical field of micro control units, in particular to a control method and a system of a watchdog circuit; the control method comprises the following steps: acquiring a target running state of a micro control unit; determining a target level type output by the micro control unit according to a target running state of the micro control unit; and driving a preset control circuit according to the target level type to drive a corresponding target watchdog circuit, wherein the interval duration of the timing reset of the target watchdog circuit meets the abnormal reset requirement of the micro control unit in the target running state. The invention solves the problem that the interval duration requirements of the timing reset of the watchdog circuit are different when the micro control unit is in different operating states, and achieves the effect of meeting the abnormal reset requirements of the micro control unit in different operating states.
Description
Technical Field
The invention relates to the technical field of micro control units, in particular to a control method and a control system of a watchdog circuit
Background
At present, in order to implement an abnormal reset function of a Micro Control Unit (MCU), a watchdog circuit is usually built in the MCU to implement the above function, because the watchdog circuit can check whether the MCU is abnormal at regular time, and can reset the MCU in time when the MCU is checked to be abnormal, so as to ensure the normal operation of the MCU.
In practice, it is found that the interval duration requirements of the timing reset of the watchdog circuit of the micro-control unit are different in different operation states, but the interval duration of the timing reset of the conventional watchdog circuit is often fixed, so that the conventional watchdog circuit cannot meet the abnormal reset requirements of the micro-control unit in different operation states.
Disclosure of Invention
The invention aims to overcome the defect that the traditional watchdog circuit cannot meet the abnormal reset requirement of a micro control unit in different running states, and provides a control method and a system of the watchdog circuit, which are used for solving the problem that the interval duration requirement of the timing reset of the watchdog circuit is different in different running states of the micro control unit.
The technical scheme adopted by the invention is as follows: disclosed is a control method of a watchdog circuit, the method comprising:
acquiring a target running state of a micro control unit;
determining a target level type output by the micro control unit according to the target running state;
and driving a preset control circuit according to the target level type to drive a corresponding target watchdog circuit, wherein the interval duration of the timing reset of the target watchdog circuit meets the abnormal reset requirement of the micro control unit in the target running state.
A control system for a watchdog circuit, the system comprising:
the acquisition unit is used for acquiring a target operation state of the micro control unit;
the determining unit is used for determining the target level type output by the micro control unit according to the target running state;
and the first control unit is used for driving a preset control circuit according to the target level type so as to drive a corresponding target watchdog circuit, and the interval duration of the timing reset of the target watchdog circuit meets the abnormal reset requirement of the micro control unit in the target running state.
Compared with the prior art, the invention has the beneficial effects that:
according to the method and the system, the running state of the micro control unit can be obtained, and the corresponding target watchdog circuit is driven through the preset control circuit according to the running state of the micro control unit; the interval duration of the timing reset of the target watchdog circuit meets the abnormal reset requirement of the micro control unit in the target running state. That is to say, the implementation of the invention can drive the target watchdog circuit whose reset interval duration meets the condition to work through the preset control circuit when the micro control unit is in different running states; the problem that the interval duration of the timing reset of the watchdog circuit is different in requirements of the micro control unit in different running states is solved, and the effect of meeting the abnormal reset requirements of the micro control unit in different running states is achieved.
Drawings
Fig. 1 is a schematic flow chart of a control method of a watchdog circuit disclosed in the present invention.
Fig. 2 is a schematic diagram of a control circuit according to the present disclosure.
Fig. 3 is a schematic flow chart of another control method of the watchdog circuit disclosed by the invention.
Fig. 4 is a schematic structural diagram of a control system of a watchdog circuit disclosed by the invention.
Fig. 5 is a schematic structural diagram of a control system of another watchdog circuit disclosed by the invention.
Detailed Description
The drawings are only for purposes of illustration and are not to be construed as limiting the invention. For a better understanding of the following embodiments, certain features of the drawings may be omitted, enlarged or reduced, and do not represent the size of an actual product; it will be understood by those skilled in the art that certain well-known structures in the drawings and descriptions thereof may be omitted.
Example 1
As shown in fig. 1, fig. 1 is a schematic flow chart of a control method of a watchdog circuit disclosed in the present invention, and the control method of the watchdog circuit may include the following steps:
101. and acquiring the target running state of the micro control unit.
In this embodiment of the present invention, an execution main body for implementing the control method of the watchdog circuit disclosed in this embodiment of the present invention may be a control system of the watchdog circuit (where the control system may be the control circuit shown in fig. 2), and may also be other control equipment or control device, and this embodiment of the present invention is not limited; the embodiment of the present invention is described and illustrated by taking a control system of a watchdog circuit as an execution main body, and should not be limited to the embodiment of the present invention. It needs to be further explained that: the Micro Controller Unit (MCU) may include a single chip microcomputer and an ARM processor (Advanced RISCMachine, ARM), and the like, and the embodiment of the present invention is not limited.
In the embodiment of the invention, the control system can acquire the target running state of the micro control unit in real time, wherein the target running state can comprise a loading running state, a normal running state and the like; further, the loading operation state may further include a power-on loading operation state, a reset loading operation state, and the like. The power-on loading operation state can refer to a stage of data or signal loading of the micro control unit when the micro control unit is powered on and started; the reset loading operation state may refer to a stage in which data or signals of the micro control unit are reloaded after the micro control unit is reset.
102. And determining the target level type output by the micro control unit according to the target running state.
In the embodiment of the invention, the control system can determine the target level type required to be output by the universal output/input port of the micro control unit according to the target running state and the preset control logic of the control circuit; the target level type can drive a preset control circuit, and the corresponding watchdog circuit is called according to the control logic of the control circuit to realize the abnormal reset function of the micro control unit in the target running state.
In a specific implementation, the target level types may include: high and low. In addition, the step 102 determines that the target level type is for driving a preset control circuit in the step 103, and please refer to the description of the step 103 for specific control logic.
103. And driving a preset control circuit according to the target level type to drive a corresponding target watchdog circuit, wherein the interval duration of the timing reset of the target watchdog circuit meets the abnormal reset requirement of the micro control unit in the target running state.
In this embodiment of the present invention, the preset control circuit may be as shown in fig. 2, where fig. 2 is a schematic diagram of a control circuit disclosed in the embodiment of the present invention, and as shown in fig. 2, a manner that the control system drives the preset control circuit according to the target level type to drive the corresponding target watchdog circuit may be: when the target level type output by the general output/input port of the micro control unit is low level, one path is converted into high level through the NOT gate and then input into the OR gate 2, according to the logic function of the OR gate: when one input of the input OR gate is high level, the output of the OR gate is not affected by other inputs, that is, the signal of the input OR gate 2 of the second target watchdog circuit does not affect the output of the OR gate 2, that is, the second target watchdog circuit is disabled, because one input of the input OR gate 2 is high level. In contrast, the low level output from the general output/input port of the micro control unit is directly input to the or gate 1, and according to the logic function of the or gate: when one input of the input OR gate is at a low level, the output of the OR gate is the same as the level of the other input, so that the signal of the input OR gate 1 of the first target watchdog circuit can influence the output of the OR gate 1, namely the first target watchdog circuit works normally; then according to the logic function of the AND gate: when the input of all the input AND gates is high level, the output of the AND gate is high level, otherwise, the output of the AND gate is low level; as can be seen from the above description, when the type of the target level output by the general output/input port of the micro control unit is a low level, the output of the or gate 2 is kept at a high level in two inputs of the and gate (i.e. the output of the or gate 1 and the output of the or gate 2), and the output of the or gate 1 is affected by the first target watchdog circuit, and may be a high level or a low level, and what needs to be further explained in conjunction with the logic function of the and gate is that: when the output of the or gate 1 is at a high level, the output of the and gate is at a high level, when the output of the or gate 1 is at a low level, the output of the and gate is at a low level, that is, the output of the and gate is affected by the or gate 1, and the or gate 3 is used for disabling the target watchdog circuit (see the description of step 304), and does not act as a wire here. In summary, the output of the and gate is affected by the or gate 1, and the output of the or gate 1 is affected by the first target watchdog circuit, that is, when the target level type output by the general output/input port of the micro control unit is a low level, the second target watchdog circuit is disabled, and the first target watchdog circuit is driven by the preset control circuit, so as to implement the abnormal reset function of the micro control unit in the target operation state.
In a specific implementation process, as shown in fig. 2, a manner that the control system drives a preset control circuit according to the target level type to drive a corresponding target watchdog circuit may also be: when the target level type output by the general output/input port of the micro control unit is high level, one path is converted into low level through the NOT gate and then input into the OR gate 2, according to the logic function of the OR gate: when one input of the input OR gate is at low level, the output of the OR gate is at the same level as the other input, that is, the OR gate 2 has one input at low level, so the signal of the second target watchdog circuit input OR gate 2 will affect the output of the OR gate 2, that is, the second target watchdog circuit can work normally. In contrast, the high level output from the general output/input port of the micro control unit is directly input to the or gate 1, and according to the logic function of the or gate: when one input of the input OR gate is in a high level, the output of the OR gate is not influenced by other inputs, so that the signal of the input OR gate 1 of the first target watchdog circuit does not influence the output of the OR gate 1, namely the first target watchdog circuit is disabled; then according to the logic function of the AND gate: when the input of all the input AND gates is high level, the output of the AND gate is high level, otherwise, the output of the AND gate is low level; as can be seen from the above description, when the type of the target level output by the general output/input port of the micro control unit is a high level, the output of the or gate 1 is kept at a high level in two inputs of the and gate (i.e. the output of the or gate 1 and the output of the or gate 2), and the output of the or gate 2 is influenced by the second target watchdog circuit, and may be a high level or a low level; what needs to be further explained in conjunction with the logical function of the and gate is that: when the output of the or gate 2 is at a high level, the output of the and gate is at a high level, when the output of the or gate 2 is at a low level, the output of the and gate is at a low level, that is, the output of the and gate is affected by the or gate 2, and the or gate 3 is used for disabling the target watchdog circuit (see the description of step 304), and does not act as a wire here. In summary, the output of the and gate is affected by the or gate 2, and the output of the or gate 2 is affected by the second target watchdog circuit, that is, when the target level type output by the general output/input port of the micro control unit is a high level, the first target watchdog circuit is disabled, and the second target watchdog circuit is driven by the preset control circuit, so as to implement the abnormal reset function of the micro control unit in the target operation state.
In this embodiment of the present invention, there may be a plurality of corresponding target watchdog circuits, and the control circuit shown in fig. 2 is also an optional implementation, and in other possible implementations, there may also be 3 or 4 corresponding target watchdog circuits, and the embodiment of the present invention is not limited; the embodiment of the present invention is described by taking 2 target watchdog circuits and the control circuit shown in fig. 2 as examples, and should not be construed as limiting the embodiment of the present invention.
In the embodiment of the invention, the interval duration of the timing reset of the first target watchdog circuit and the second target watchdog circuit can be different, the interval duration can meet the abnormal reset requirements of the micro control unit in different target operation states, and when the micro control unit is in a certain target operation state, the control system can drive the corresponding target watchdog circuit through the control circuit to perform abnormal reset on the micro control unit. In a specific implementation, the specific time length value of the time interval between the timing resets of the first target watchdog circuit and the second target watchdog circuit may be set by a developer according to a large amount of development data, and the embodiment of the present invention is not limited. As an alternative embodiment, the target watchdog circuit may set the interval duration of the timing reset of the target watchdog circuit by configuring the resistance value of the pull-down resistor to ground at the input/output port of the circuit.
In the embodiment of the invention, the target watchdog circuit can also input high level through a key to control the target watchdog circuit to output a reset signal to the micro control unit; in addition, the level signal input to the target watchdog circuit may be a jump square wave signal, and the reset signal output by the target watchdog circuit may be a fixed high level signal or a fixed low level signal, where when the reset signal output by the target watchdog circuit is a high level, the micro control unit keeps normal operation, and when the reset signal output by the target watchdog circuit is a low level, the micro control unit may be reset.
As an optional implementation manner, the manner in which the control system determines the type of the target level output by the micro control unit according to the target operation state may be: when the control system determines that the target running state is the loading running state, determining that the target level type output by the micro control unit is a low level according to the target running state; and the way that the control system drives the preset control circuit according to the target level type to drive the corresponding target watchdog circuit may be: the control system drives a preset control circuit according to the low level to drive a corresponding first target watchdog circuit, and the interval duration of the timing reset of the first target watchdog circuit meets the abnormal reset requirement of the micro control unit in the loading running state.
In a specific implementation process, when the micro control unit is in a loading operation state, because the time required for loading the micro control unit is long, the interval duration of the timing reset of the first target watchdog circuit can be configured to exceed a preset first time duration threshold so as to meet the requirement of abnormal reset of the micro control unit in the loading operation state. It needs to be further explained that: hardware of the control system can be set to be a fixed pull-down circuit, so that the control level of the micro control unit in the loading operation stage is low level, and the unstable IO level state of the MCU in the power-on or reset stage is avoided.
By implementing the method, the control system can drive the first target watchdog circuit, the interval duration of the timing reset meets the abnormal reset requirement of the micro control unit in the loading operation state, when the micro control unit is determined to be in the loading operation state, so as to realize the abnormal reset function of the micro control unit in the loading operation state.
As another alternative implementation, the manner in which the control system determines the type of the target level output by the micro control unit according to the target operation state may be: when the control system determines that the target running state is the normal running state, determining that the type of the target level output by the micro control unit is a high level according to the target running state; and the way that the control system drives the preset control circuit according to the target level type to drive the corresponding target watchdog circuit may be: the control system drives a preset control circuit according to the high level to drive a corresponding second target watchdog circuit, and the interval duration of the timing reset of the second target watchdog circuit meets the abnormal reset requirement of the micro control unit in the normal running state.
In a specific implementation process, when the micro control unit is in a normal operation state, the required interval duration of the timing reset is short, so that the interval duration of the timing reset of the second target watchdog circuit can be configured to be lower than a preset second duration threshold (the second duration threshold is less than or equal to the first duration threshold) so as to meet the abnormal reset requirement of the micro control unit in the normal operation state.
By implementing the method, the control system can drive the second target watchdog circuit, the interval duration of the timing reset meets the abnormal reset requirement of the micro control unit in the normal operation state, when the micro control unit is determined to be in the normal operation state, so as to realize the abnormal reset function of the micro control unit in the normal operation state.
It can be seen that, by implementing the control method described in fig. 1, the operating state of the micro control unit can be obtained, and the corresponding target watchdog circuit is driven by the preset control circuit according to the operating state of the micro control unit; the interval duration of the timing reset of the target watchdog circuit meets the abnormal reset requirement of the micro control unit in the target running state. That is to say, by implementing the embodiment of the present invention, the control system can drive the target watchdog circuit whose reset interval duration satisfies the condition to operate through the preset control circuit when the micro control unit is in different operating states; the problem that the interval duration of the timing reset of the watchdog circuit is different in requirements of the micro control unit in different running states is solved, and the effect of meeting the abnormal reset requirements of the micro control unit in different running states is achieved.
Example 2
As shown in fig. 3, fig. 3 is a schematic flow chart of another control method of a watchdog circuit disclosed in the present invention, and the control method of the watchdog circuit may include the following steps:
301. and acquiring the target running state of the micro control unit.
302. And determining the target level type output by the micro control unit according to the target running state.
303. And driving a preset control circuit according to the target level type to drive a corresponding target watchdog circuit, wherein the interval duration of the timing reset of the target watchdog circuit meets the abnormal reset requirement of the micro control unit in the target running state.
304. And if the target watchdog circuit needs to be disabled during debugging, controlling a preset control circuit to be connected to a power supply end through a jumper socket so as to disable the preset control circuit to drive the target watchdog circuit.
In the embodiment of the present invention, it needs to be described with reference to fig. 2 that: when an instruction indicating that the target watchdog circuit is disabled is received, one input port of an or gate 3 (please refer to fig. 2) in a preset control circuit can be controlled to be connected to a power supply end through a jumper socket (in a normal condition, the or gate 3 defaults to connect a pull-down resistor), and since the power supply end outputs a high level stably, when the jumper socket is plugged into a jumper cap, one input of the or gate 3 is connected with the power supply end, one input of the or gate 3 is kept at the high level; it should be further noted that, according to the logic function of the or gate, when the input of the or gate, which is one input, is high, the output of the or gate is kept high regardless of whether the other input is high or low, that is, the output of the or gate 3 is not affected by the other input, so that the control circuit before the or gate 3 is disabled (or disabled), and obviously, the first target watchdog circuit and the second target watchdog circuit are also correspondingly disabled.
As an optional implementation manner, when detecting that the input pin of the target watchdog circuit receives the start signal, the control circuit may start the target watchdog circuit, so that the target watchdog circuit sends a reset signal to the micro control unit, and forcibly resets the micro control unit according to the reset signal.
In a specific implementation process, when the input pin receives a start signal or is activated, the target watchdog circuit can forcibly send a reset signal to the micro control unit so as to forcibly reset the micro control unit.
By way of example, the control circuit shown in FIG. 2: the time interval of the timing reset of the first target watchdog circuit meets the abnormal reset requirement of the micro control unit in the loading running state; the interval duration of the timing reset of the second target watchdog circuit meets the abnormal reset requirement of the micro control unit in the normal running state; therefore, the input pins of the first target watchdog circuit and the second target watchdog circuit can be activated simultaneously, so that the first target watchdog circuit and the second target watchdog circuit both send reset signals to the micro control unit, and the micro control unit can be forcibly reset no matter in a loading operation state or a normal operation state.
By implementing the method, the method for forcibly resetting the micro control unit is expanded, and the micro control unit can be forcibly reset no matter in the running states such as the loading running state, the normal running state and the like, so that the abnormal resetting problem of the micro control unit is solved, and the normal running of the micro control unit is ensured.
In addition to the control method described in fig. 1, the control method described in fig. 2 may also be implemented by connecting a preset control circuit to a power supply terminal through a jumper socket, and disabling the target watchdog circuit through disabling the control circuit; that is to say, the control method described in fig. 2 expands a method for disabling the target watchdog circuit, which is used for debugging an application scenario in which the watchdog function needs to be disabled, and provides an effective implementation means for debugging a machine.
Example 3
As shown in fig. 4, fig. 4 is a schematic structural diagram of a control system of a watchdog circuit according to an embodiment of the present invention, where the control system may include:
an obtaining unit 401, configured to obtain a target operation state in which the micro control unit is located;
a determining unit 402, configured to determine a target level type output by the micro control unit according to the target operating state;
the first control unit 403 is configured to drive a preset control circuit according to a target level type to drive a corresponding target watchdog circuit, where an interval duration of the timing reset of the target watchdog circuit meets an abnormal reset requirement of the micro control unit in a target operation state.
The control system described in fig. 4 can acquire the operating state of the micro control unit, and drive the corresponding target watchdog circuit through the preset control circuit according to the operating state of the micro control unit; the interval duration of the timing reset of the target watchdog circuit meets the abnormal reset requirement of the micro control unit in the target running state. That is to say, by implementing the embodiment of the present invention, the control system can drive the target watchdog circuit whose reset interval duration satisfies the condition to operate through the preset control circuit when the micro control unit is in different operating states; the problem that the interval duration of the timing reset of the watchdog circuit is different in requirements of the micro control unit in different running states is solved, and the effect of meeting the abnormal reset requirements of the micro control unit in different running states is achieved.
Example 4
As shown in fig. 5, fig. 5 is a schematic structural diagram of another control system of a watchdog circuit disclosed in the present invention, the control system shown in fig. 5 may be optimized by the control system shown in fig. 4, and compared with the control system shown in fig. 4, the control system shown in fig. 5 may further include:
and the second control unit 404 is configured to control the preset control circuit to be connected to a power supply end through a jumper socket when the target watchdog circuit needs to be disabled for debugging, so as to disable the preset control circuit from driving the target watchdog circuit.
As an alternative embodiment, the control system shown in fig. 5 may further include:
the starting unit 405 is configured to start the target watchdog circuit when detecting that the input pin of the target watchdog circuit receives the starting signal, so that the target watchdog circuit sends a reset signal to the micro control unit, and the micro control unit is forcibly reset according to the reset signal.
By implementing the method, the method for forcibly resetting the micro control unit is expanded, and the micro control unit can be forcibly reset no matter in the running states such as the loading running state, the normal running state and the like, so that the abnormal resetting problem of the micro control unit is solved, and the normal running of the micro control unit is ensured.
As an optional implementation manner, the manner that the determining unit 402 is configured to determine the type of the target level output by the micro control unit according to the target operation state may specifically be:
a determining unit 402, configured to determine, according to a target operation state, that a target level type output by the micro control unit is a low level when the target operation state is determined to be the loading operation state;
the manner for the first control unit 403 to drive the preset control circuit according to the target level type to drive the corresponding target watchdog circuit may specifically be:
the first control unit 403 is configured to drive a preset control circuit according to a low level to drive a corresponding first target watchdog circuit, where an interval duration of the timing reset of the first target watchdog circuit meets an abnormal reset requirement of the micro control unit in the loading operation state.
By implementing the method, the control system can drive the first target watchdog circuit, the interval duration of the timing reset meets the abnormal reset requirement of the micro control unit in the loading operation state, when the micro control unit is determined to be in the loading operation state, so as to realize the abnormal reset function of the micro control unit in the loading operation state.
As an optional implementation manner, the manner that the determining unit 402 is configured to determine the type of the target level output by the micro control unit according to the target operation state may specifically be:
a determining unit 402, configured to determine, according to the target operation state, that the type of the target level output by the micro control unit is a high level when the target operation state is determined to be the normal operation state;
the manner for the first control unit 403 to drive the preset control circuit according to the target level type to drive the corresponding target watchdog circuit may specifically be:
the first control unit 403 is configured to drive a preset control circuit according to the high level to drive a corresponding second target watchdog circuit, where an interval duration of the timing reset of the second target watchdog circuit meets an abnormal reset requirement of the micro control unit in a normal operation state.
By implementing the method, the control system can drive the second target watchdog circuit, the interval duration of the timing reset meets the abnormal reset requirement of the micro control unit in the normal operation state, when the micro control unit is determined to be in the normal operation state, so as to realize the abnormal reset function of the micro control unit in the normal operation state.
Compared with the control system described in the embodiment of fig. 4, the control system described in fig. 5 can also be implemented by connecting a preset control circuit to a power supply end through a jumper socket, and disabling the target watchdog circuit through disabling the control circuit; that is to say, the control method described in fig. 2 expands a method for disabling the target watchdog circuit, which is used for debugging an application scenario in which the watchdog function needs to be disabled, and provides an effective implementation means for debugging a machine.
It should be understood that the above-mentioned embodiments of the present invention are only examples for clearly illustrating the technical solutions of the present invention, and are not intended to limit the specific embodiments of the present invention. Any modification, equivalent replacement, and improvement made within the spirit and principle of the present invention claims should be included in the protection scope of the present invention claims.
Claims (10)
1. A method of controlling a watchdog circuit, the method comprising:
acquiring a target running state of a micro control unit;
determining a target level type output by the micro control unit according to the target running state;
and driving a preset control circuit according to the target level type to drive a corresponding target watchdog circuit, wherein the interval duration of the timing reset of the target watchdog circuit meets the abnormal reset requirement of the micro control unit in the target running state.
2. The method for controlling a watchdog circuit according to claim 1, wherein the determining a target level type of the output of the micro control unit according to the target operating state comprises:
when the target running state is determined to be the loading running state, determining that the target level type output by the micro control unit is a low level according to the target running state;
and driving a preset control circuit according to the target level type to drive a corresponding target watchdog circuit, including:
and driving a preset control circuit according to the low level to drive a corresponding first target watchdog circuit, wherein the interval duration of the timing reset of the first target watchdog circuit meets the abnormal reset requirement of the micro control unit in the loading running state.
3. The method for controlling a watchdog circuit according to claim 1, wherein the determining a target level type of the output of the micro control unit according to the target operating state comprises:
when the target running state is determined to be the normal running state, determining that the type of the target level output by the micro control unit is a high level according to the target running state;
and driving a preset control circuit according to the target level type to drive a corresponding target watchdog circuit, including:
and driving a preset control circuit according to the high level to drive a corresponding second target watchdog circuit, wherein the interval duration of the timing reset of the second target watchdog circuit meets the abnormal reset requirement of the micro control unit in the normal running state.
4. The method of controlling a watchdog circuit according to claim 1, the method further comprising:
and if the target watchdog circuit needs to be disabled during debugging, controlling the preset control circuit to be connected to a power supply end through a jumper socket so as to prohibit the preset control circuit from driving the target watchdog circuit.
5. The method of controlling a watchdog circuit according to claim 1, the method further comprising:
and when detecting that the input pin of the target watchdog circuit receives a starting signal, starting the target watchdog circuit, so that the target watchdog circuit sends a reset signal to the micro control unit, and forcibly resetting the micro control unit according to the reset signal.
6. A control system for a watchdog circuit, the system comprising:
the acquisition unit is used for acquiring a target operation state of the micro control unit;
the determining unit is used for determining the target level type output by the micro control unit according to the target running state;
and the first control unit is used for driving a preset control circuit according to the target level type so as to drive a corresponding target watchdog circuit, and the interval duration of the timing reset of the target watchdog circuit meets the abnormal reset requirement of the micro control unit in the target running state.
7. The control system of a watchdog circuit according to claim 6, wherein the determining unit is configured to determine the type of the target level output by the micro control unit according to the target operating state in a specific manner:
the determining unit is used for determining that the target level type output by the micro control unit is a low level according to the target running state when the target running state is determined to be the loading running state;
and the first control unit is used for driving a preset control circuit according to the target level type so as to drive a corresponding target watchdog circuit, and the mode specifically comprises the following steps:
and the first control unit is used for driving a preset control circuit according to the low level so as to drive a corresponding first target watchdog circuit, and the interval duration of the timing reset of the first target watchdog circuit meets the abnormal reset requirement of the micro control unit in the loading running state.
8. The control system of a watchdog circuit according to claim 6, wherein the determining unit is configured to determine the type of the target level output by the micro control unit according to the target operating state in a specific manner:
the determining unit is used for determining that the type of the target level output by the micro control unit is a high level according to the target running state when the target running state is determined to be a normal running state;
and the first control unit is used for driving a preset control circuit according to the target level type so as to drive a corresponding target watchdog circuit, and the mode specifically comprises the following steps:
and the first control unit is used for driving a preset control circuit according to the high level so as to drive a corresponding second target watchdog circuit, and the interval duration of the timing reset of the second target watchdog circuit meets the abnormal reset requirement of the micro control unit in the normal running state.
9. The control system of a watchdog circuit according to claim 6, the system further comprising:
and the second control unit is used for controlling the preset control circuit to be connected to a power supply end through a jumper socket when the target watchdog circuit is required to be disabled in debugging and testing so as to prohibit the preset control circuit from driving the target watchdog circuit.
10. The control system of a watchdog circuit according to claim 6, the system further comprising:
and the starting unit is used for starting the target watchdog circuit when detecting that the input pin of the target watchdog circuit receives a starting signal, so that the target watchdog circuit sends a reset signal to the micro control unit, and the micro control unit is forcibly reset according to the reset signal.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201911328683.2A CN111061590A (en) | 2019-12-20 | 2019-12-20 | Control method and system of watchdog circuit |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201911328683.2A CN111061590A (en) | 2019-12-20 | 2019-12-20 | Control method and system of watchdog circuit |
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| CN2681231Y (en) * | 2003-06-24 | 2005-02-23 | 华为技术有限公司 | A watchdog circuit |
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| CN203535627U (en) * | 2013-09-29 | 2014-04-09 | 深圳市邦彦信息技术有限公司 | Watchdog circuit |
| US20160357623A1 (en) * | 2015-06-04 | 2016-12-08 | Fujitsu Limited | Abnormality detection method and information processing apparatus |
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| CN2681231Y (en) * | 2003-06-24 | 2005-02-23 | 华为技术有限公司 | A watchdog circuit |
| CN102214124A (en) * | 2011-06-08 | 2011-10-12 | 深圳市理邦精密仪器股份有限公司 | Watchdog reset control system |
| CN203535627U (en) * | 2013-09-29 | 2014-04-09 | 深圳市邦彦信息技术有限公司 | Watchdog circuit |
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Application publication date: 20200424 |