CN115480884A - Chip, test monitoring method of chip and computer readable storage medium - Google Patents
Chip, test monitoring method of chip and computer readable storage medium Download PDFInfo
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- CN115480884A CN115480884A CN202110602781.1A CN202110602781A CN115480884A CN 115480884 A CN115480884 A CN 115480884A CN 202110602781 A CN202110602781 A CN 202110602781A CN 115480884 A CN115480884 A CN 115480884A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/46—Multiprogramming arrangements
- G06F9/48—Program initiating; Program switching, e.g. by interrupt
- G06F9/4806—Task transfer initiation or dispatching
- G06F9/4812—Task transfer initiation or dispatching by interrupt, e.g. masked
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
- G06F11/0751—Error or fault detection not based on redundancy
- G06F11/0754—Error or fault detection not based on redundancy by exceeding limits
- G06F11/0757—Error or fault detection not based on redundancy by exceeding limits by exceeding a time limit, i.e. time-out, e.g. watchdogs
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/14—Error detection or correction of the data by redundancy in operation
- G06F11/1402—Saving, restoring, recovering or retrying
- G06F11/1415—Saving, restoring, recovering or retrying at system level
- G06F11/1441—Resetting or repowering
Abstract
The present disclosure relates to a chip, a test monitoring method of the chip, and a computer-readable storage medium. The chip comprises a memory, an internal bus and an interrupt processing monitoring device, wherein the memory is coupled with the interrupt processing monitoring device through the internal bus, a plurality of interrupt entry addresses which are in one-to-one correspondence with a plurality of interrupt service programs are stored in the memory, and the interrupt processing monitoring device comprises: the monitoring processing module is used for responding to a first event that an interrupt entry address of a target interrupt service program is called and starting timing; the target interrupt service program is any one of a plurality of interrupt service programs; the signal output module is used for outputting an error indication signal corresponding to the target interrupt service program under the condition that the timing result of the timing is greater than the preset execution duration threshold of the target interrupt service program; and the result processing module is used for executing the stop operation corresponding to the error indication signal to the target interrupt service program so as to stop the execution of the target interrupt service program.
Description
Technical Field
The disclosed embodiments relate to the field of chip design technologies, and more particularly, to a chip, a chip test monitoring method, and a computer-readable storage medium.
Background
In the process of running the main program, a Micro Control Unit (MCU) responds to an interrupt signal, and skips to a corresponding interrupt service program and runs the interrupt service program when receiving the interrupt signal. In the process, if an abnormality occurs in the running process of the interrupt service routine, for example, a running fault occurs or the interrupt processing time limit of the MCU is not met, a corresponding function error of the MCU may be caused. In order to recover the corresponding functions of the MCU, the MCU is reset by setting a watchdog and performing a watchdog feeding operation on the main program.
In practical situations, the watchdog has a long watchdog feeding period, and cannot respond to an exception occurring in the running process of the interrupt service routine in time, so that the processing time for the exception is long.
Disclosure of Invention
An object of the disclosed embodiments is to provide a new technical solution for a chip.
According to a first aspect of the present disclosure, there is provided a chip, including a memory, an internal bus, and an interrupt processing monitoring device, the memory being coupled to the interrupt processing monitoring device through the internal bus, a plurality of interrupt entry addresses corresponding to a plurality of interrupt service programs one to one being stored in the memory, the interrupt processing monitoring device including: the monitoring processing module is used for responding to a first event that an interrupt entry address of a target interrupt service program is called and starting timing; the target interrupt service program is any one of a plurality of interrupt service programs; the signal output module is used for outputting an error indication signal corresponding to the target interrupt service program under the condition that the timing result of the timing is greater than the preset execution duration threshold of the target interrupt service program; and the result processing module is used for executing the stop operation corresponding to the error indication signal to the target interrupt service program so as to stop the execution of the target interrupt service program.
Optionally, the error indication signal includes a first error indication signal, and the result processing module is specifically configured to: and stopping the target interrupt service program according to the first error indication signal, and returning to an interrupt point to continue executing the main program.
Optionally, the chip further comprises a watchdog timer and a reset terminal coupled with the watchdog timer, and the interrupt processing monitoring device is coupled with the watchdog timer through an internal bus; the error indication signal includes a second error indication signal, and the result processing module is specifically configured to: and placing the watchdog timer in an overflow state according to the second error indication signal, so that the watchdog timer sends a reset signal to a reset terminal.
Optionally, the interrupt processing monitoring apparatus further includes: the data recording module is used for recording the running data of the target interrupt service program after the timing is started; and responding to a second event of which the timing result is greater than the preset execution time length threshold of the target interrupt service program, and recording the timing result.
Optionally, the operational data comprises: the interrupt entry address, the interrupt exit address, and the number of interrupt execution instructions of the target interrupt service routine.
Optionally, the interrupt processing monitoring apparatus further includes: and the sending module is used for sending the error indication signal to the main program which jumps to the front of the target interrupt service program after the result processing module executes the stopping operation corresponding to the error indication signal on the target interrupt service program so as to stop the execution of the target interrupt service program, so that the main program can obtain the recording result of the data recording module according to the error indication signal and output the error analysis result after the error analysis is carried out on the running process of the target interrupt service program according to the recording result.
According to a second aspect of the present disclosure, there is also provided a test monitoring method for a chip, where the chip includes a memory, an internal bus, and an interrupt processing monitoring device, the memory is coupled to the interrupt processing monitoring device through the internal bus, and multiple interrupt entry addresses corresponding to multiple interrupt service programs one to one are stored in the memory, and the method is applied to the interrupt processing monitoring device, and the method includes: responding to a first event that an interrupt entry address of a target interrupt service program is called, and starting timing; the target interrupt service program is any one of a plurality of interrupt service programs; under the condition that the timing result is greater than the preset execution time length threshold of the target interrupt service program, outputting an error indication signal corresponding to the target interrupt service program; and executing the stop operation corresponding to the error indication signal on the target interrupt service program so as to stop the execution of the target interrupt service program.
Optionally, the error indication signal includes a first error indication signal, and the performing, on the target interrupt service program, a stop operation corresponding to the error indication signal so as to stop the execution of the target interrupt service program includes: and stopping the target interrupt service program according to the first error indication signal, and returning to an interrupt point to continue executing the main program.
Optionally, the chip further comprises a watchdog timer and a reset terminal coupled with the watchdog timer, and the interrupt processing monitoring device is coupled with the watchdog timer through an internal bus; the error indication signal comprises a second error indication signal, and the stop operation corresponding to the error indication signal is executed on the target interrupt service program so as to stop the execution of the target interrupt service program, and the method comprises the following steps: and placing the watchdog timer in an overflow state according to the second error indication signal, so that the watchdog timer sends a reset signal to a reset terminal.
Optionally, the method further comprises: after timing is started, recording running data of a target interrupt service program; and responding to a second event of which the timing result is greater than the preset execution time threshold of the target interrupt service program, and recording the timing result.
Optionally, the operation data includes: the interrupt entry address, the interrupt exit address, and the number of interrupt execution instructions of the target interrupt service routine.
Optionally, after the stop operation corresponding to the error indication signal is executed on the target interrupt service program so as to stop the execution of the target interrupt service program, the method further includes: and sending the error indication signal to a main program before the target interrupt service program is jumped to, so that the main program can obtain a recording result of the data recording module according to the error indication signal and output an error analysis result after error analysis is carried out on the running process of the target interrupt service program according to the recording result.
According to a third aspect of the present disclosure, there is also provided a computer readable storage medium having stored thereon a computer program which, when executed by a processor, implements a method according to the second aspect of the present disclosure.
One beneficial effect of the embodiments of the present disclosure is that, a first event that an interrupt entry address of a target interrupt service program is called can be responded, and timing is started; and under the condition that the timing result is greater than the preset execution time length threshold value of the target interrupt service program, outputting an error indication signal corresponding to the target interrupt service program, and then executing a stopping operation corresponding to the error indication signal on the target interrupt service program so as to stop the execution of the target interrupt service program. The embodiment of the disclosure can set different error indication signals for different interrupt service programs, so that the abnormal processing mode in the running process of the interrupt service program is no longer a single mode of resetting the MCU by setting a watchdog and carrying out watchdog feeding operation on a main program, the problem that the abnormal processing time for the abnormal condition is long due to the fact that the watchdog feeding period is long and the abnormal processing in the running process of the interrupt service program cannot be responded in time under some conditions is effectively avoided, and the purpose of timely responding to the abnormal processing in the running process of the interrupt service program is achieved.
Other features of embodiments of the present disclosure and advantages thereof will become apparent from the following detailed description of exemplary embodiments thereof, which is to be read in connection with the accompanying drawings.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of the specification, illustrate embodiments of the disclosure and together with the description, serve to explain the principles of the embodiments of the disclosure.
Fig. 1 is a schematic structural diagram of a chip according to an embodiment of the disclosure;
fig. 2 is a schematic structural diagram of another chip provided in the embodiment of the present disclosure;
fig. 3 is a schematic structural diagram of another chip according to an embodiment of the disclosure;
fig. 4 is a schematic structural diagram of another chip according to an embodiment of the disclosure;
fig. 5 is a flowchart of a method for monitoring a test of a chip according to an embodiment of the present disclosure;
fig. 6 is a schematic diagram of a hardware structure of a chip according to the disclosed embodiment.
Detailed Description
Various exemplary embodiments of the present disclosure will now be described in detail with reference to the accompanying drawings. It should be noted that: the relative arrangement of the components and steps, the numerical expressions, and numerical values set forth in these embodiments do not limit the scope of the present disclosure unless specifically stated otherwise.
The following description of at least one exemplary embodiment is merely illustrative in nature and is in no way intended to limit the disclosure, its application, or uses.
Techniques, methods, and apparatus known to those of ordinary skill in the relevant art may not be discussed in detail but are intended to be part of the specification where appropriate.
In all examples shown and discussed herein, any particular value should be construed as merely illustrative, and not limiting. Thus, other examples of the exemplary embodiments may have different values.
It should be noted that: like reference numbers and letters refer to like items in the following figures, and thus, once an item is defined in one figure, further discussion thereof is not required in subsequent figures.
Various embodiments and examples according to the present disclosure are described below with reference to the drawings.
< apparatus embodiment >
Fig. 1 is a schematic structural diagram of a chip according to an embodiment of the disclosure. The chip 10 may include: a memory 12, an internal bus 14 and an interrupt handling monitoring means 15, the interrupt handling monitoring means 15 being coupled to the memory 12 via the internal bus 14.
Fig. 2 is a schematic structural diagram of a chip according to an embodiment of the disclosure. As shown in fig. 2, the chip 10 may further include: a watchdog timer 11 and a reset terminal 13 coupled to the watchdog timer 11. The interrupt handling monitoring means 15 may be coupled to the watchdog timer 11 via an internal bus 14.
The chip 10 may have multiple interrupt interfaces (not shown in fig. 1). The memory 12 stores a plurality of interrupt entry addresses corresponding to a plurality of interrupt service programs one by one, and the plurality of interrupt entry addresses and the plurality of interrupt interfaces also correspond one by one.
Illustratively, as shown In FIG. 2, chip 10 has a plurality of interrupt interfaces 16, such as interrupt interfaces I1-In FIG. 2. The plurality of interrupt interfaces 16 may be, for example, hardware interfaces, such as pins on the chip 10.
The plurality of interrupt interfaces 16 may include at least one internal interrupt interface and at least one external interrupt interface. At least one internal interrupt interface, such as interrupt interfaces I1-Im In fig. 2, and at least one external interrupt interface, such as interrupt interfaces I (m + 1) -In fig. 2; wherein n > m >0,n and m are natural numbers.
When one interrupt interface in a plurality of interrupt interfaces receives an interrupt signal, the interrupt entry address of the target interrupt service program is called for the target interrupt service program corresponding to the interrupt interface, and the target interrupt service program starts to run. In this case, the interruption processing monitoring means 15 starts operating.
As shown in fig. 1, the interruption processing monitoring apparatus 15 includes: a monitor processing module 151, a signal output module 152, and a result processing module 153.
The monitoring processing module 151 is configured to start timing in response to a first event that an interrupt entry address of the target interrupt service routine is called; the target interrupt service routine is any one of a plurality of interrupt service routines.
The signal output module 152 is configured to output an error indication signal corresponding to the target interrupt service routine when the timing result of the timing is greater than a preset execution duration threshold of the target interrupt service routine.
And the result processing module 153 is used for executing the stopping operation corresponding to the error indication signal on the target interrupt service program so as to stop the execution of the target interrupt service program.
In the embodiment of the present disclosure, a preset execution duration threshold corresponding to each interrupt service program may be set in advance for the interrupt service program. The preset execution time length threshold corresponding to the interrupt service program is the maximum time length required to be consumed under the condition that the interrupt service program normally runs.
In some embodiments, the preset execution duration threshold corresponding to the interrupt service routine is less than or equal to 1ms.
In some embodiments, an error indication signal corresponding to each interrupt service routine is set in advance for the interrupt service routine. For example, according to whether the chip 10 needs to be initialized when the interrupt service routine is abnormal, the interrupt service routines are divided into at least one first target interrupt service routine and at least one second target interrupt service routine, the chip 10 does not need to be initialized when the first target interrupt service routine is abnormal, and the chip 10 needs to be initialized when the second target interrupt service routine is abnormal. In this case, the error indication signal of the first target interrupt service routine is set as the first error indication signal, and the error indication signal of the second target interrupt service routine is set as the second error indication signal.
When the target interrupt service program is the first target interrupt service program, the error indication signal output by the signal output module 152 is the first error indication signal, and the result processing module 153 stops the execution of the target interrupt service program according to the first error indication signal, and returns to the interrupt point to continue executing the main program, thereby achieving the purpose of timely responding to the abnormality in the running process of the target interrupt service program.
In the case that the target interrupt service program is the second target interrupt service program, the error indication signal output by the signal output module 152 is the second error indication signal, and in this case, the result processing module 153 sets the watchdog timer in an overflow state according to the second error indication signal, so that the watchdog timer sends a reset signal to the reset terminal, and the chip 10 resumes initialization, so as to stop the execution of the target interrupt service program, and achieve the purpose of timely responding to an abnormality in the running process of the target interrupt service program.
It should be understood that the above-mentioned embodiments only adopt different processing manners for the exception occurring in the running process of the interrupt service program according to whether the chip 10 needs to be initialized when the exception occurs in the interrupt service program. In an actual situation, the interrupt service program can be divided from other dimensions, and a processing mode to be adopted after the running process of different interrupt service programs is abnormal is set according to the division result, so that the purpose of timely responding to the abnormality in the running process of the interrupt service program is achieved.
Therefore, the embodiment of the disclosure can set different error indication signals for different interrupt service programs, so that the processing mode of the abnormal operation process of the interrupt service program is no longer a single mode of resetting the MCU by setting a watchdog and performing watchdog feeding operation on the main program, thereby effectively avoiding the problem that the abnormal operation process of the interrupt service program cannot be responded in time due to a longer watchdog feeding period under some conditions, and further the processing time of the abnormal operation process is longer, and realizing the purpose of responding in time to the abnormal operation process of the interrupt service program.
When the timing result is less than or equal to the target timing threshold corresponding to the target interrupt entry address, it indicates that the target interrupt service routine is operating normally, and in this case, the result processing module 152 does not output an error indication signal.
In some embodiments, the number of the target interrupt service programs may be multiple, in which case, the interrupt processing monitoring device 15 may include multiple threads, each thread corresponding to one target interrupt service program, so that the running processes of multiple target interrupt service programs can be monitored simultaneously. In addition, the monitoring processes of the target interrupt service programs are independent from each other, and for any target interrupt service program in the target interrupt service programs, the monitoring process for the target interrupt service program is not influenced by the monitoring processes of other target interrupt service programs.
In order to record the relevant data and status during the running process of the interrupt service program, in some embodiments, as shown in fig. 2, the interrupt processing monitoring apparatus 15 may further include: a data logging module 154.
A data recording module 154, configured to record the running data of the target interrupt service program after the monitoring processing module 151 starts timing; and responding to a second event of which the timing result is greater than the preset execution time threshold of the target interrupt service program, and recording the timing result.
In some embodiments, the operational data includes: the interrupt entry address, the interrupt exit address, and the number of interrupt execution instructions of the target interrupt service routine.
The interrupt exit address is, for example, an address to be called to end the operation of the target interrupt service routine.
The interrupt execution instruction is an instruction for specifying a jump to a target interrupt service routine. In some cases, the target interrupt service routine executes in a loop, thus requiring multiple interrupt execution instructions to be issued to specify a jump to the target interrupt service routine to execute the target interrupt service routine. In this case, the number of interrupt execution instructions may represent the number of times the target interrupt service routine is executed in a loop.
In some embodiments, as shown in fig. 3, the interrupt processing monitoring apparatus 15 further includes: a sending module 155, configured to send an error indication signal to the main program that jumps to the front of the target interrupt service routine after the result processing module performs a stopping operation corresponding to the error indication signal on the target interrupt service routine so as to stop execution of the target interrupt service routine, so that the main program obtains a recording result of the data recording module according to the error indication signal, and outputs an error analysis result after performing error analysis on the running process of the target interrupt service routine according to the recording result.
In order to turn on or off the function of the interrupt processing monitoring apparatus 15, in some embodiments, as shown in fig. 4, the interrupt processing monitoring apparatus 15 further includes: a function configuration module 156.
Specifically, the function configuration module 156 is configured to control the state of the interrupt processing monitoring apparatus to be an enabled state when a preset enabling event is detected. And controlling the state of the interrupt processing monitoring device to be a non-enabled state under the condition that the occurrence of the preset non-enabled event is monitored. For example, in the case where it is monitored that a preset enable event occurs, the interrupt processing monitoring device 15 is controlled to be decoupled from the internal bus 14; for example, in the case where a preset disable event is detected to occur, the interrupt processing monitoring means 15 is controlled to be coupled to the internal bus 14.
The preset enabling event and the preset disabling event may be set by those skilled in the art according to practical situations, and are not limited in the implementation of the present disclosure.
The embodiments of the present disclosure are described in detail below by way of some examples.
As shown in fig. 2, the interrupt interface I1 corresponds to an interrupt function of a first counter (not shown in fig. 2), the interrupt interface I2 corresponds to an interrupt function of a second counter (not shown in fig. 2), and the interrupt interface I3 corresponds to an interrupt function of a serial communication module (not shown in fig. 2).
The interrupt entry address corresponding to the interrupt interface I1 is a first interrupt entry address, and the first interrupt entry address corresponds to a first interrupt service routine. The interrupt entry address corresponding to the interrupt interface I2 is a second interrupt entry address, and the second interrupt entry address corresponds to a second interrupt service routine. The interrupt entry address corresponding to the interrupt interface I3 is a third interrupt entry address, and the third interrupt entry address corresponds to a third interrupt service routine. The first interrupt service routine and the third interrupt service routine are, for example, a first target interrupt service routine, and the preset execution time length thresholds of the first interrupt service routine and the third interrupt service routine are both 1ms. The second interrupt service routine is, for example, the first target interrupt service routine, and the preset execution time threshold values are all 0.5ms.
Taking the interrupt interface I1 as an example, when the first interrupt entry address is called, the monitoring processing module 151 starts timing, the signal output module 152 monitors a timing result in real time, when the timing result of the timing is greater than the preset execution time threshold of the first interrupt service program, the signal output module 152 acquires the timing result in the monitoring processing module 151 in real time, and when the timing result is less than or equal to 1ms, the error indication signal is not output; when the timing result is greater than 1ms, a first error indication signal is output. The result processing module 153 forcibly stops the execution of the first interrupt service routine according to the first error indication signal, and returns to the interrupt point to continue executing the main routine.
Taking the interrupt interface I3 as an example, when the second interrupt entry address is called, the monitoring processing module 151 starts timing, the signal output module 152 monitors a timing result in real time, when the timing result of the timing is greater than the preset execution time threshold of the second interrupt service program, the signal output module 152 acquires the timing result in the monitoring processing module 151 in real time, and when the timing result is less than or equal to 0.5ms, the error indication signal is not output; if the timing result is greater than 0.5ms, a second error indication signal is output. The result processing module 153 outputs an overflow signal to the watchdog timer 11 according to the second error indication signal, so that the watchdog timer 11 converts its current state into an overflow state according to the overflow signal, and the watchdog timer 11 sends a reset signal to the reset terminal 13.
Therefore, in the embodiment of the disclosure, different processing modes can be set for the abnormal operation of the interrupt service program corresponding to the interrupt interface according to different interrupt interfaces, so as to achieve the purpose of timely responding to the abnormality in the operation process of the interrupt service program.
The chip 10 in the embodiment of the present disclosure may be, for example, an MCU (micro controller unit), a central processing unit (CPU for short), or the like.
< method examples >
Fig. 5 is a flowchart of a method for monitoring and testing a chip according to an embodiment of the present disclosure. The chip comprises a memory, an internal bus and an interrupt processing monitoring device, wherein the memory is coupled with the interrupt processing monitoring device through the internal bus, a plurality of interrupt entry addresses which are in one-to-one correspondence with a plurality of interrupt service programs are stored in the memory, the method is applied to the interrupt processing monitoring device, and as shown in fig. 5, the method comprises the following steps of S510-S530:
step S510: responding to a first event that an interrupt entry address of a target interrupt service program is called, and starting timing; the target interrupt service routine is any one of a plurality of interrupt service routines.
Step S520: and outputting an error indication signal corresponding to the target interrupt service program under the condition that the timing result of the timing is greater than the preset execution time length threshold of the target interrupt service program.
Step S530: and executing the stop operation corresponding to the error indication signal on the target interrupt service program so as to stop the execution of the target interrupt service program.
Optionally, the error indication signal includes a first error indication signal, and the performing, on the target interrupt service routine, a stop operation corresponding to the error indication signal so as to stop the execution of the target interrupt service routine includes: and stopping the target interrupt service program according to the first error indication signal, and returning to an interrupt point to continue executing the main program.
Optionally, the chip further comprises a watchdog timer and a reset terminal coupled with the watchdog timer, and the interrupt processing monitoring device is coupled with the watchdog timer through an internal bus; the error indication signal comprises a second error indication signal, and the stopping operation corresponding to the error indication signal is executed on the target interrupt service program so as to stop the execution of the target interrupt service program, and the method comprises the following steps: and placing the watchdog timer in an overflow state according to the second error indication signal, so that the watchdog timer sends a reset signal to a reset terminal.
Optionally, the method further comprises: after timing is started, recording running data of a target interrupt service program; and responding to a second event of which the timing result is greater than the preset execution time threshold of the target interrupt service program, and recording the timing result.
Optionally, the operation data includes: the interrupt entry address, the interrupt exit address, and the number of interrupt execution instructions of the target interrupt service routine.
Optionally, after the stop operation corresponding to the error indication signal is executed on the target interrupt service routine so as to stop the execution of the target interrupt service routine, the method further includes: and sending the error indication signal to a main program before the target interrupt service program is jumped to, so that the main program can obtain a recording result of the data recording module according to the error indication signal and output an error analysis result after error analysis is carried out on the running process of the target interrupt service program according to the recording result.
For a specific implementation manner of the above method steps, reference may be made to the corresponding description in the embodiment of the chip 10 described above, and details are not described here again.
The method and the device have the advantages that timing can be started in response to a first event that a target interrupt entry address in a plurality of interrupt entry addresses is called, and a target timing threshold corresponding to the target interrupt entry address is obtained from timing thresholds corresponding to a plurality of preset interrupt interface addresses; and the result processing module is used for outputting an error indication signal to the watchdog timer under the condition that the timing result is greater than a target timing threshold corresponding to the target interrupt entry address so as to place the watchdog timer in an overflow state and enable the watchdog timer to send a reset signal to the reset end. The problem that due to the fact that the watchdog is long in dog feeding period and the execution period of the main program, the abnormity appearing in the running process of the interrupt service program cannot be responded in time, and the processing time for the abnormal condition is long is solved, and the purpose of responding in time to the abnormity appearing in the running process of the interrupt service program is achieved.
Fig. 6 is a schematic diagram of a hardware structure of a chip according to an embodiment of the present disclosure.
As shown in fig. 6, the interrupt handling monitoring apparatus 600 comprises a processor 610 and a memory 620, the memory 620 is used for storing an executable computer program, and the processor 610 is used for executing the method according to any of the above method embodiments according to the control of the computer program.
The modules of the interrupt processing monitoring apparatus 15 may be implemented by the processor 610 in the present embodiment executing the computer program stored in the memory 620, or may be implemented by other circuit configurations, which is not limited herein.
The method and the device have the advantages that timing can be started in response to a first event that a target interrupt entry address in a plurality of interrupt entry addresses is called, and a target timing threshold corresponding to the target interrupt entry address is obtained from timing thresholds corresponding to a plurality of preset interrupt interface addresses; and the result processing module is used for outputting an error indication signal to the watchdog timer under the condition that the timing result is greater than a target timing threshold corresponding to the target interrupt entry address so as to place the watchdog timer in an overflow state and enable the watchdog timer to send a reset signal to the reset end. The problem that due to the fact that the watchdog is long in dog feeding period and the execution period of the main program, the abnormity appearing in the running process of the interrupt service program cannot be responded in time, and the processing time for the abnormal condition is long is solved, and the purpose of responding in time to the abnormity appearing in the running process of the interrupt service program is achieved.
The present disclosure may be systems, methods, and/or computer program products. The computer program product may include a computer-readable storage medium having computer-readable program instructions embodied thereon for causing a processor to implement various aspects of the present disclosure.
The computer readable storage medium may be a tangible device that can hold and store the instructions for use by the instruction execution device. The computer readable storage medium may be, for example, but not limited to, an electronic memory device, a magnetic memory device, an optical memory device, an electromagnetic memory device, a semiconductor memory device, or any suitable combination of the foregoing. More specific examples (a non-exhaustive list) of the computer readable storage medium would include the following: a portable computer diskette, a hard disk, a Random Access Memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), a Static Random Access Memory (SRAM), a portable compact disc read-only memory (CD-ROM), a Digital Versatile Disc (DVD), a memory stick, a floppy disk, a mechanical coding device, such as punch cards or in-groove projection structures having instructions stored thereon, and any suitable combination of the foregoing. Computer-readable storage media as used herein is not to be construed as transitory signals per se, such as radio waves or other freely propagating electromagnetic waves, electromagnetic waves propagating through a waveguide or other transmission medium (e.g., optical pulses through a fiber optic cable), or electrical signals transmitted through electrical wires.
The computer-readable program instructions described herein may be downloaded from a computer-readable storage medium to a respective computing/processing device, or to an external computer or external storage device over a network, such as the internet, a local area network, a wide area network, and/or a wireless network. The network may include copper transmission cables, fiber optic transmission, wireless transmission, routers, firewalls, switches, gateway computers and/or edge servers. The network adapter card or network interface in each computing/processing device receives computer-readable program instructions from the network and forwards the computer-readable program instructions for storage in a computer-readable storage medium in the respective computing/processing device.
The computer program instructions for carrying out operations of the present disclosure may be assembler instructions, instruction Set Architecture (ISA) instructions, machine-related instructions, microcode, firmware instructions, state setting data, or source or object code written in any combination of one or more programming languages, including an object oriented programming language such as Smalltalk, C + + or the like and conventional procedural programming languages, such as the "C" programming language or similar programming languages. The computer-readable program instructions may execute entirely on the user's computer, partly on the user's computer, as a stand-alone software package, partly on the user's computer and partly on a remote computer or entirely on the remote computer or server. In the case of a remote computer, the remote computer may be connected to the user's computer through any type of network, including a Local Area Network (LAN) or a Wide Area Network (WAN), or the connection may be made to an external computer (for example, through the Internet using an Internet service provider). In some embodiments, the electronic circuitry that can execute the computer-readable program instructions implements aspects of the present disclosure by utilizing the state information of the computer-readable program instructions to personalize the electronic circuitry, such as a programmable logic circuit, a Field Programmable Gate Array (FPGA), or a Programmable Logic Array (PLA).
Various aspects of the present disclosure are described herein with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems) and computer program products according to embodiments of the disclosure. It will be understood that each block of the flowchart illustrations and/or block diagrams, and combinations of blocks in the flowchart illustrations and/or block diagrams, can be implemented by computer-readable program instructions.
These computer-readable program instructions may be provided to a processor of a general purpose computer, special purpose computer, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions/acts specified in the flowchart and/or block diagram block or blocks. These computer-readable program instructions may also be stored in a computer-readable storage medium that can direct a computer, programmable data processing apparatus, and/or other devices to function in a particular manner, such that the computer-readable medium storing the instructions comprises an article of manufacture including instructions which implement the function/act specified in the flowchart and/or block diagram block or blocks.
The computer readable program instructions may also be loaded onto a computer, other programmable data processing apparatus, or other devices to cause a series of operational steps to be performed on the computer, other programmable apparatus or other devices to produce a computer implemented process such that the instructions which execute on the computer, other programmable apparatus or other devices implement the functions/acts specified in the flowchart and/or block diagram block or blocks.
The flowchart and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods and computer program products according to various embodiments of the present disclosure. In this regard, each block in the flowchart or block diagrams may represent a module, segment, or portion of instructions, which comprises one or more executable instructions for implementing the specified logical function(s). In some alternative implementations, the functions noted in the block may occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved. It will also be noted that each block of the block diagrams and/or flowchart illustration, and combinations of blocks in the block diagrams and/or flowchart illustration, can be implemented by special purpose hardware-based systems which perform the specified functions or acts, or combinations of special purpose hardware and computer instructions. It is well known to those skilled in the art that implementation by hardware, by software, and by a combination of software and hardware are equivalent.
The foregoing description of the embodiments of the present disclosure has been presented for purposes of illustration and description, but is not intended to be exhaustive or limited to the embodiments disclosed. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The terminology used herein is chosen in order to best explain the principles of the embodiments, the practical application, or improvements made to the technology in the marketplace, or to enable others of ordinary skill in the art to understand the embodiments disclosed herein. The scope of the present disclosure is defined by the appended claims.
Claims (10)
1. A chip, comprising a memory, an internal bus, and an interrupt processing monitoring device, wherein the memory is coupled to the interrupt processing monitoring device via the internal bus, and a plurality of interrupt entry addresses corresponding to a plurality of interrupt service programs are stored in the memory, and the interrupt processing monitoring device comprises:
the monitoring processing module is used for responding to a first event that an interrupt entry address of a target interrupt service program is called and starting timing; wherein the target interrupt service routine is any one of the plurality of interrupt service routines;
the signal output module is used for outputting an error indication signal corresponding to the target interrupt service program under the condition that the timing result of the timing is greater than a preset execution duration threshold of the target interrupt service program;
and the result processing module is used for executing the stop operation corresponding to the error indication signal on the target interrupt service program so as to stop the execution of the target interrupt service program.
2. The chip of claim 1, wherein the error indication signal comprises a first error indication signal, and wherein the result processing module is specifically configured to:
and stopping the target interrupt service program according to the first error indication signal, and returning to an interrupt point to continue executing the main program.
3. The chip according to claim 1, wherein the chip further comprises a watchdog timer and a reset terminal coupled to the watchdog timer, the interrupt processing monitoring device is coupled to the watchdog timer through the internal bus;
the error indication signal comprises a second error indication signal, and the result processing module is specifically configured to:
and placing the watchdog timer in an overflow state according to the second error indication signal, so that the watchdog timer sends a reset signal to a reset terminal.
4. The chip according to any of claims 1 to 3, wherein the interrupt handling monitoring means further comprises:
a data recording module, configured to record running data of the target interrupt service routine after the start of timing; and responding to a second event of which the timing result is greater than the preset execution time threshold of the target interrupt service program, and recording the timing result.
5. The chip of claim 4, wherein the operational data comprises: an interrupt entry address, an interrupt exit address, and a number of interrupt execution instructions of the target interrupt service routine.
6. The chip of claim 1, wherein the interrupt handling monitoring means further comprises:
and the sending module is used for sending the error indication signal to a main program which jumps to the front of the target interrupt service program after the result processing module executes the stopping operation corresponding to the error indication signal on the target interrupt service program so as to stop the execution of the target interrupt service program, so that the main program obtains a recording result of a data recording module according to the error indication signal and outputs an error analysis result after error analysis is carried out on the running process of the target interrupt service program according to the recording result.
7. A method for monitoring chip test, wherein the chip includes a memory, an internal bus and an interrupt handling monitoring device, the memory is coupled to the interrupt handling monitoring device through the internal bus, a plurality of interrupt entry addresses corresponding to a plurality of interrupt service programs are stored in the memory, the method is applied to the interrupt handling monitoring device, and the method includes:
responding to a first event that an interrupt entry address of a target interrupt service program is called, and starting timing; wherein the target interrupt service routine is any one of the plurality of interrupt service routines;
outputting an error indication signal corresponding to the target interrupt service program under the condition that the timing result of the timing is greater than a preset execution duration threshold of the target interrupt service program;
and executing a stopping operation corresponding to the error indication signal on the target interrupt service program so as to stop the execution of the target interrupt service program.
8. The method of claim 7, wherein the error indication signal comprises a first error indication signal;
the executing the stop operation corresponding to the error indication signal to the target interrupt service program so as to stop the execution of the target interrupt service program includes:
and stopping the target interrupt service program according to the first error indication signal, and returning to an interrupt point to continue executing the main program.
9. The method of claim 7, wherein the chip further comprises a watchdog timer and a reset terminal coupled to the watchdog timer, the interrupt handling monitoring device being coupled to the watchdog timer via the internal bus;
the error indication signal comprises a second error indication signal, and the executing of the stop operation corresponding to the error indication signal on the target interrupt service routine so as to stop the execution of the target interrupt service routine comprises:
and placing the watchdog timer in an overflow state according to the second error indication signal, so that the watchdog timer sends a reset signal to a reset terminal.
10. A computer-readable storage medium, characterized in that a computer program is stored on the computer-readable storage medium, which computer program, when being executed by a processor, carries out the method according to any one of claims 7-9.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117056062A (en) * | 2023-10-13 | 2023-11-14 | 武汉天喻信息产业股份有限公司 | Method and device for forcedly exiting interrupt service routine |
| CN117076169A (en) * | 2023-08-04 | 2023-11-17 | 阿波罗智联(北京)科技有限公司 | Method and device for detecting interruption abnormality of operating system and electronic equipment |
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2021
- 2021-05-31 CN CN202110602781.1A patent/CN115480884A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117076169A (en) * | 2023-08-04 | 2023-11-17 | 阿波罗智联(北京)科技有限公司 | Method and device for detecting interruption abnormality of operating system and electronic equipment |
| CN117056062A (en) * | 2023-10-13 | 2023-11-14 | 武汉天喻信息产业股份有限公司 | Method and device for forcedly exiting interrupt service routine |
| CN117056062B (en) * | 2023-10-13 | 2024-04-02 | 武汉天喻信息产业股份有限公司 | Method and device for forcedly exiting interrupt service routine |
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