CN104156289A - Synchronous control method and system based on detection circuit - Google Patents
Synchronous control method and system based on detection circuit Download PDFInfo
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Abstract
The invention provides a synchronous control method and a system based on a detection circuit, the system comprises a computer system, the detection circuit and a reset switch, the input end of the detection circuit is connected with the computer system through a GPIO interface and an LPC bus interface, the output end of the detection circuit is connected with the reset switch, the detection circuit comprises: the system comprises a timer, a received signal judging module, an overtime period setting module and a resetting system, wherein the received signal judging module is connected with a computer system, the timer, the overtime period setting module and the resetting system are respectively connected with the received signal judging module, and the resetting system is connected with a resetting switch. The invention has the advantages of improving the stability and fault tolerance of the computer system of the domestic processor.
Description
Technical field
The present invention relates to computer realm, particularly, relate to a kind of synchronisation control means based on testing circuit and system of the stability that promotes domestic processor computer system.
Background technology
At present, computer system based on domestic processor is mostly in the starting stage, autonomous crucial software and hardware has had large quantities of producers to obtain achievement in research, at present these producers positive by application of result to the improvement of verifying in various equipment or project.But, because batch, the use of domestic processor are historical far away from external chip, may there is some flaw; Degree of ripeness, the use history of domestic operating system also can not show a candle to external product, in use may expose some inconsiderate situations, and domestic debugging method are relatively deficient.Therefore, although domestic core electron components and parts can be applicable to design and the development of equipment substantially through the development of ten several years, but chip application and popularization immature, fail to form a whole set of mechanism based on domestic processor benign development, and the chip using at present also exists some problems.In order to solve or to evade these problems, expand the range of application of domestic processor, promote domestic processor technology constantly to promote, need in application process, adopt various technology and means, ensure autonomous controlled computing platform stability and reliability based on domestic processor design, for the stability aspect of home brewed computer system, the relevant producer of domestic each research field furthers investigate always.
In home brewed computer system stability design, often run into two kinds of situations: the one, there is the abnormal situation of sequential owing to being subject to external disturbance in computer system electrifying startup process, system can not normally be started once in a while; The 2nd, when system runs application, there is unpredictable gross error, cause system in case of system halt.As shown in Figure 1, traditional typical computer system needs human intervention while there are these situations, confirm system state restarting systems, the synchronisation control means based on testing circuit that the present invention proposes fast and effectively resolution system starts failure or the problem crashing that runs application.
Summary of the invention
For defect of the prior art, the object of this invention is to provide a kind of synchronisation control means and system based on testing circuit.
According to an aspect provided by the invention, a kind of synchronisation control means based on testing circuit is provided, comprise the following steps:
The operation that powers on of step (1) system, testing circuit is started working, firmware is working properly by the GPIO level change notification detection circuitry of set handling device, if testing circuit is not notified in Preset Time, produce system reset information and be sent to reset switch, start reset mechanism, restarting systems;
Step (2), when firmware initialization completes, the time unloading phase of being set to be slightly larger than system, comes into force testing circuit setting by the time-out time T0 of total line traffic control testing circuit testing circuit;
After finishing the unloading phase of step (3) system, if receiving system in time T 0, testing circuit starts normal notice, testing circuit reset function is temporarily forbidden, enter the application program operation phase, otherwise, testing circuit produces system reset information and is sent to reset switch, starts reset mechanism, restarting systems;
Step (4), according to the requirement of concrete applied environment, arranges the time-out time of testing circuit by bus, enable detection circuit recovers to start service routine after reset function;
Step (5) service routine is working properly as cycle notice detection circuitry taking the time-out time T that is slightly less than testing circuit, if testing circuit receives the notice of program normal operation in time T, continues operation service program; Otherwise testing circuit produces system reset information and is sent to reset switch, start reset mechanism, restarting systems.
Preferably, the output signal that the reset mechanism employing output signal of testing circuit and the output signal of reset key produce after logical AND gate is as the reset signal of system.
Preferably, step (1) comprises the following steps:
The operation that powers on of step (11) system, testing circuit is started working;
Step (12) is if user by entering the debugging mode of firmware before load operation system by function key, and testing circuit will be closed reset function automatically; Otherwise, execution step (13);
Step (13) starts load operation system file, jump into system entry address, successfully enter operating system, in the meantime, if occur unsuccessfully, system sends and starts failure notification to testing circuit, and testing circuit sends repositioning information to reset switch, start reset mechanism, restarting systems.
Preferably, scope is set is 0.01s to 655.35s to the time-out time of testing circuit.
Preferably, the overtime Preset Time of testing circuit in step (1) is 2s; The time-out time T0 of the testing circuit in step (2) is 25s; Between load operation system runs application to system, the time-out time of testing circuit is T, and the time-out time T of the testing circuit in step (5) is 15s.
Preferably, bus is lpc bus.
According to another aspect of the present invention, a kind of synchronous control system based on testing circuit is provided, comprise: computer system, testing circuit and reset switch, testing circuit input end is connected with computer system with lpc bus interface by GPIO interface, testing circuit output terminal is connected with reset switch, comprise: timer, receive signal judge module, time out period arranges module and resetting system, receiving signal judge module is connected with computer system, timer, time out period arranges module and is connected with reception signal judge module respectively with resetting system, resetting system connects reset switch, time out period arranges module and is connected with computer system.
Preferably, the output signal that the output signal of testing circuit and the output signal of reset key produce after logical AND gate is as the reset signal of system.
Preferably, reset switch is reset button or electrify restoration circuit.
The present invention guarantees that by testing circuit system is in the whole course of work, the unloading phase of comprising and the application program operation phase, can in the time that system runs into abnormal deadlock, effectively process, and makes the system can be again in running order.Compared with prior art, the present invention has following beneficial effect: the present invention by design testing circuit the system unloading phase and the system operation phase carry out sectionalization test, difference control, the system causing for all kinds of faults of domestic processor computer system is hung and is recovered extremely in time, reenter normal operating conditions, there is the stability and the fault-tolerance that improve domestic processor computer system.
Brief description of the drawings
By reading the detailed description of non-limiting example being done with reference to the following drawings, it is more obvious that other features, objects and advantages of the present invention will become:
Fig. 1 is the structure principle chart of existing home brewed computer system;
Fig. 2 is the theory diagram of testing circuit in the present invention;
Fig. 3 is the structure principle chart that the present invention is based on the synchronous control system of testing circuit;
Fig. 4 is the synchronous control system structural representation based on testing circuit of the embodiment of the present invention;
Fig. 5 is the process principle figure that the present invention is based on the synchronisation control means of testing circuit;
Fig. 6 is the process principle figure of synchronisation control means in system starting process that the present invention is based on testing circuit.
Embodiment
Below in conjunction with specific embodiment, the present invention is described in detail.Following examples will contribute to those skilled in the art further to understand the present invention, but not limit in any form the present invention.It should be pointed out that to those skilled in the art, without departing from the inventive concept of the premise, can also make some distortion and improvement.These all belong to protection scope of the present invention.
Refer to Fig. 3, a kind of synchronous control system based on testing circuit, comprise: computer system, testing circuit and reset switch, testing circuit input end is connected with computer system with lpc bus interface by GPIO interface, and testing circuit output terminal is connected with reset switch.
Refer to Fig. 2, testing circuit comprises: timer, reception signal judge module, time out period arrange module and resetting system, receiving signal judge module is connected with computer system, timer, time out period arrange module and are connected with reception signal judge module respectively with resetting system, resetting system connects reset switch, and time out period arranges module and is connected with computer system.
Testing circuit is mainly used in the running status of monitoring, management system, and the CPU in abnormality is carried out to reset operation, can rework.Testing circuit passes through software code realization based on the existing CPLD chip of system.
CLK0 is as external clock input signal, and the inner integrated timer of testing circuit, as the work clock of testing circuit.Between domestic processor and testing circuit, be connected by GPIO interface and lpc bus interface.Reset switch is mainly used in forbidden energy reset function and output reset signal.Testing circuit receives the enable signal of CPU by GPIO1 pin, start detection circuit is started working.Periodically receive working state signal by GPIO2 pin, with monitoring CPU duty.In the different operation phase of system, the time out period of testing circuit arranges module and receives by lpc bus the different cycle signalization that CPU sends, and according to it, rational time out period is set.Resetting system is mainly used in forbidden energy reset function and output reset signal.Whether the monitoring in real time of the reception signal judge module of testing circuit receives the system state normal signal that CPU sends in the time-out time of regulation, start resetting system if do not receive and send reset signal to CPU, in the time being interfered, still can maintain normal duty with guarantee system.
Particularly, the output signal that the output signal of testing circuit and the output signal of reset key produce after logical AND gate is as the reset signal of system.Reset switch is reset button or electrify restoration circuit.
Testing circuit provides GPIO and two kinds of modes of lpc bus to make the system running status of reporting system easily.After resetting, supervisory circuit acquiescence is used GPIO advice method, and time-out time is 2s.After lpc bus initialization finishes, software can pass through advice method and the time-out time of lpc bus configuration detection circuit.
As shown in Figure 3, the synchronous control system structural representation based on testing circuit of embodiment, this system is a computer system based on domestic processor, and this system is accidental after the stuck situation of firmware several times in os starting process, restarts rear normal by reset key.Through test repeatedly, this phenomenon is difficult to reproduction.For this situation, testing circuit mechanism of the present invention is set, to the stuck phenomenon that may exist in the firmware start-up course processing that automatically resets.Testing circuit passes through software code realization in the existing CPLD chip of system.Between domestic processor and testing circuit, send and enable and signalization function by GPIO interface and lpc bus Interface realization, once testing circuit is not received the system state normal information that processor sends in official hour, thereby decision processor breaks down, start immediately reset mechanism, send reset signal to processor, allow system enter normal running status.
The present invention is in domestic processor computer system starting process or application program operational process, and while occurring that unpredictable mistake causes system in case of system halt, testing circuit can be realized auto-reset function.System is started and carries out segment monitoring, and before lpc bus no initializtion, acquiescence adopts GPIO notice, adopts LPC reporting system state after LPC initialization.In system starting process, monitored respectively lpc bus connection procedure, LPC connect be accomplished to load operation system before, load operation system is to system this three phases that runs application.
Time-out time of the present invention is configurable, and configurable time-out time scope is 0.01s to 655.35s, and time-out time precision is 0.01s.In system operational process according to the different time-out time cycles is set the actual start-up time of different phase.
The present invention also provides and the invention provides a kind of automatic checkout system running status and automatically reset method in the time occurring crashing: after system powers on, first enter firmware and start, complete the initialization of the basic input/output BIOS (Basic Input/output System) of computing machine, start rear load operation system file mirror image, jump into subsequently operating system entry address, login of operating system, runs application afterwards.After powering on, when firmware starts, testing circuit is also started working, the running status of the whole process of supervisory system.The unloading phase that whole process comprising system and the application program operation phase, the running status of system and testing circuit as shown in Figure 5.
The unloading phase of system: system powers on and brings into operation, and testing circuit starts working.Firmware is working properly by the GPIO level change notification detection circuitry of set handling device, if testing circuit is not notified in 2s, produces system reset information; When firmware initialization completes lpc bus (or other buses), the time unloading phase of being set to be slightly larger than system by the time-out time T0 of lpc bus control testing circuit testing circuit, testing circuit setting is come into force; The unloading phase of system, finish rear testing circuit reset function and temporarily forbid, then enter the application program operation phase.
The application program operation phase: according to the requirement of concrete applied environment, the time-out time of testing circuit is set by lpc bus, enable detection circuit recovers to start a service routine after reset function, and service routine notifies detection circuitry working properly taking T as the cycle.T is the time-out time that is slightly less than testing circuit.
Refer to Fig. 5, a kind of synchronisation control means based on testing circuit, comprises the following steps:
S1: the system operation that powers on, testing circuit is started working, firmware is working properly by the GPIO level change notification detection circuitry of set handling device, if testing circuit is not notified in Preset Time, produce system reset information and be sent to reset switch, start reset mechanism, restarting systems.
The state variation of testing circuit in system starting process as shown in Figure 6, after system powers on, firmware starts to carry out simultaneously start detection circuit immediately, and the overall process that firmware is carried out is enabled testing circuit, guarantees when before entering operating system, system exception crashes to automatically reset.User by entering the debugging mode of firmware before load operation system by function key, testing circuit will be closed reset function automatically.Otherwise, start load operation system file, jump into system entry address, successfully enter operating system.In the meantime, if occur unsuccessfully, testing circuit sends reset signal to system, specifically comprises the following steps:
S11: the system operation that powers on, testing circuit is started working;
S12: if user by entering the debugging mode of firmware before load operation system by function key, testing circuit will be closed reset function automatically; Otherwise, execution step (13);
S13: start load operation system file, jump into system entry address, successfully enter operating system, in the meantime, if occur unsuccessfully, system sends and starts failure notification to testing circuit, testing circuit sends repositioning information to reset switch, starts reset mechanism, restarting systems.
S2: when firmware initialization completes, the time unloading phase of being set to be slightly larger than system by the time-out time T0 of total line traffic control testing circuit testing circuit, testing circuit setting is come into force;
S3: after finishing the unloading phase of system, if receiving system in time T 0, testing circuit starts normal notice, testing circuit reset function is temporarily forbidden, enter the application program operation phase, otherwise, testing circuit produces system reset information and is sent to reset switch, starts reset mechanism, restarting systems;
S4: according to the requirement of concrete applied environment, the time-out time of testing circuit is set by bus, enable detection circuit recovers to start service routine after reset function;
S5: service routine is working properly as cycle notice detection circuitry taking the time-out time T that is slightly less than testing circuit, if testing circuit receives the notice of program normal operation in time T, continues operation service program; Otherwise testing circuit produces system reset information and is sent to reset switch, start reset mechanism, restarting systems.
It is 0.01s to 655.35s that the time-out time of testing circuit arranges scope.In native system, in setting steps under default situations (1) lpc bus connection procedure, the time-out time of testing circuit is 2s (unit is second); LPC connects that to be accomplished to the time-out time T0 of testing circuit before load operation system be 25s in step (2); Between the middle load operation system of step (5) runs application to system, the time-out time of testing circuit is T, and it is 15s that system default arranges T.Can, by the value of the T that sets, specify and jump into operating system testing circuit time-out time during this period of time from load operation system to program.This time is depended on load operation system mode (network or local hard drive), the size of the operating system being loaded.
Further, bus is lpc bus; The output signal that the reset mechanism employing output signal of testing circuit and the output signal of reset key produce after logical AND gate is as the reset signal of system.
The present invention is integrated automatic detection circuit in system, for occurring automatically reseting while deadlock at system operational process.The computer system of integrated detection circuit can guarantee that system is in the whole course of work, the unloading phase of comprising and the application program operation phase, can in the time that running into abnormal deadlock, system effectively process, make the system can be again in running order, promote stability and the fault-tolerance of domestic processor system work.
Above specific embodiments of the invention are described.It will be appreciated that, the present invention is not limited to above-mentioned specific implementations, and those skilled in the art can make various distortion or amendment within the scope of the claims, and this does not affect flesh and blood of the present invention.
Claims (9)
1. the synchronisation control means based on testing circuit, is characterized in that, comprises the following steps:
The operation that powers on of step (1) system, testing circuit is started working, firmware is working properly by the GPIO level change notification detection circuitry of set handling device, if testing circuit is not notified in Preset Time, produce system reset information and be sent to reset switch, start reset mechanism, restarting systems;
Step (2), when firmware initialization completes, the time unloading phase of being set to be slightly larger than system, comes into force testing circuit setting by the time-out time T0 of total line traffic control testing circuit testing circuit;
After finishing the unloading phase of step (3) system, if receiving system in time T 0, testing circuit starts normal notice, testing circuit reset function is temporarily forbidden, enter the application program operation phase, otherwise, testing circuit produces system reset information and is sent to reset switch, starts reset mechanism, restarting systems;
Step (4), according to the requirement of concrete applied environment, arranges the time-out time of testing circuit by bus, enable detection circuit recovers to start service routine after reset function;
Step (5) service routine is working properly as cycle notice detection circuitry taking the time-out time T that is slightly less than testing circuit, if testing circuit receives the notice of program normal operation in time T, continues operation service program; Otherwise testing circuit produces system reset information and is sent to reset switch, start reset mechanism, restarting systems.
2. the synchronisation control means based on testing circuit according to claim 1, it is characterized in that, the output signal that the described reset mechanism employing output signal of testing circuit and the output signal of reset key produce after logical AND gate is as the reset signal of system.
3. the synchronisation control means based on testing circuit according to claim 1, is characterized in that, step (1) comprises the following steps:
The operation that powers on of step (11) system, testing circuit is started working;
Step (12) is if user by entering the debugging mode of firmware before load operation system by function key, and testing circuit will be closed reset function automatically; Otherwise, execution step (13);
Step (13) starts load operation system file, jump into system entry address, successfully enter operating system, in the meantime, if occur unsuccessfully, system sends and starts failure notification to testing circuit, and testing circuit sends repositioning information to reset switch, start reset mechanism, restarting systems.
4. the synchronisation control means based on testing circuit according to claim 1, is characterized in that, it is 0.01s to 655.35s that the time-out time of testing circuit arranges scope.
5. the synchronisation control means based on testing circuit according to claim 4, is characterized in that, the overtime Preset Time of testing circuit described in step (1) is 2s; The time-out time T0 of the testing circuit described in step (2) is 25s; Between load operation system runs application to system, the time-out time of testing circuit is T, and the time-out time T of the testing circuit described in step (5) is 15s.
6. the synchronisation control means based on testing circuit according to claim 1, is characterized in that, described bus is lpc bus.
7. the synchronous control system based on testing circuit, it is characterized in that, comprise: computer system, testing circuit and reset switch, described testing circuit input end is connected with described computer system with lpc bus interface by GPIO interface, described testing circuit output terminal is connected with described reset switch, described testing circuit comprises: timer, receive signal judge module, time out period arranges module and resetting system, described reception signal judge module is connected with computer system, described timer, time out period arranges module and is connected with reception signal judge module respectively with resetting system, resetting system connects reset switch, described time out period arranges module and is connected with described computer system.
8. the synchronous control system based on testing circuit according to claim 7, is characterized in that, the output signal that the output signal of described testing circuit and the output signal of reset key produce after logical AND gate is as the reset signal of system.
9. the synchronous control system based on testing circuit according to claim 7, is characterized in that, described reset switch is reset button or electrify restoration circuit.
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