CN102270028A

CN102270028A - Automatic Loongson mainboard resetting device based on field programmable gate array (FPGA)

Info

Publication number: CN102270028A
Application number: CN2011102050872A
Authority: CN
Inventors: 王晖; 郑臣明; 邵宗有; 刘新春; 杨晓君; 王英; 柳胜杰; 姚文浩; 郝志彬; 梁发清
Original assignee: Dawning Information Industry Co Ltd
Current assignee: Dawning Information Systems (Liaoning) Co., Ltd.
Priority date: 2011-07-21
Filing date: 2011-07-21
Publication date: 2011-12-07
Anticipated expiration: 2031-07-21
Also published as: CN102270028B

Abstract

The invention provides an automatic Loongson mainboard resetting device based on a field programmable gate array (FPGA). An FPGA chip and a resetting circuit are arranged on a Loongson mainboard, wherein the FPGA chip receives a signal of a general-purpose input/output (GPIO) pin of a Loongson central processor unit (CPU) and sends the signal to the resetting circuit; and the resetting circuit sends a resetting signal to the Loongson CPU, a north bridge chip and a south bridge chip.

Description

A kind of automatically reset device of Godson mainboard based on FPGA

Technical field

The present invention relates to the Godson mainboard and automatically reset, specifically, relate to a kind of automatically reset device of Godson mainboard based on FPGA.

Background technology

Because the cause of the design of loongson3A CPU, the HT bus that can cause CPU does not link under individual cases with the HT bus of RS780E and the situation that occurs crashing, but when this situation occurring, the mainboard that resets just can make it chain again.

Therefore in order to repair the BUG of this hardware, the mainboard that designs with loongson3A CPU and AMD RS780E north bridge in the market can adopt a kind of method of using house dog to realize the timing automatic mainboard that resets.Detailed method such as Fig. 1:

The key of the realization of this method is to select a watchdog circuit, watchdog circuit, be watchdog timer again, it is a timer circuit, an input is generally arranged, cry and feed dog (kicking the dog or service the dog), a RST end that outputs to MCU in the time of the MCU operate as normal, is held to feeding dog every signal of end time output, give the WDT zero clearing, do not feed dog if surpass official hour, (generally when program fleet), WDT regularly surpasses, will provide a reset signal to MCU, MCU is resetted. its function is to prevent that MCU from crashing.

Principle of work for Fig. 1 is such: when mainboard one start, watchdog circuit has just been started working, because there is individual timer the watchdog circuit the inside, one power on so, timer has just picked up counting, and Godson 3A CPU need be by the GPIO pin of oneself, regularly send pulse waveform to watchdog circuit, allow the timer of watchdog circuit carry out clear operation, if and CPU is not with on north bridge is connected, mainboard crashes so, and PMON can not continue to carry out yet, and therefore comes the timer of watchdog circuit is carried out clear operation with regard to not sending pulse, and like this, when house dog timing the time to the regular hour, will send the order that resets with reset circuit, make the reset circuit monoblock mainboard that resets.Like this just can solve the hardware BUG of the above-mentioned Godson 3A CPU that carries.

But there is the problem of adjustability difference in such method.At first will select a suitable watchdog circuit is exactly a problem, because there is the problem of maximum timing in watchdog chip, so the speed of on type selecting, carrying out with regard to the program that needs concern PMON.Like this, if the program of PMON has been changed, just cause previously used house dog just to be done for possibly, because surpassed the maximum timing number of house dog.

The time of the timer of watchdog circuit is provided with in addition needs to use RC to be provided with, like this, and neither be very convenient in debugging.Simultaneously since need allow CPU regularly send reset signal to watchdog circuit, like this, can take the occupancy of number of C PU.

Summary of the invention

Realize the problem of the automatically reset adjustability difference of Godson 3A mainboard in order to solve watchdog circuit.The present invention adopts the mode of FPGA to realize automatically reseting of Godson mainboard.

A kind of automatically reset device of Godson mainboard based on FPGA, fpga chip and reset circuit on the Godson mainboard, have been added, described fpga chip receives the signal of the GPIO pin of Godson CPU, described fpga chip sends a signal to described reset circuit, and described reset circuit sends reset signal to Godson CPU, north bridge chips and South Bridge chip.

Preferably, when the Godson mainboard starts, check out after whether the HT bus connect, load the assignment program GPIO pin is carried out assignment at PMON.

Preferably, described assignment program is not operated the GPIO pin when the HT bus does not connect; After on the HT bus connects, to GPIO pin assignment.

Preferably, described FPGA begins to detect GPIO pin value after the time of setting.

Preferably, if described GPIO pin value 0, then FPGA sends signal and gives reset circuit; Described GPIO pin value is if be not 0, and then FPGA does not send signal.

Preferably, described reset circuit sends reset signal and gives Godson CPU after receiving the signal of FPGA, and north bridge chips and South Bridge chip restart.

Preferably, the initial value of described GPIO pin is 0.

Preferably, the time of described setting is to set in FPGA by program.

Beneficial effect of the present invention is as follows:

1, it is unrestricted that FPGA regulates the time, and than the method for house dog, convenience is to have improved greatly.

2, owing to be to realize automatically reseting with FPGA, employing be the method that detects GPIO pin level, and, after being provided with a value,, can remain this value if it is not operated again for the GPIO pin of Godson 3A CPU always.The utilization factor that like this just can be good at saving CPU, and unlike the method for using house dog, CPU also wants sending watchdog zero clearing signal and need take the utilization factor of CPU regularly.

Description of drawings

Fig. 1 is the resetting means of present Godson mainboard

Fig. 2 is the resetting means of Godson mainboard of the present invention

Embodiment

The present invention has changed watchdog circuit commonly used at present into FPGA and has realized that detailed principle of work is as follows:

The present invention utilizes the GPIO pin of Godson 3A CPU to make an issue of, because we know the GPIO pin of Godson 3A, it is output as " 0 " under the state that it is not carried out any operation, therefore the GPIO pin of Godson 3A is connected on the FPGA, by after detecting the program whether HT chain on the PMON, add the program of GPIO pin assignment, because FPGA is being provided with temporal superiority, therefore when FPGA begins to detect this GPIO pin by the time (execution speed that needs coupling PMON is set of time) is set, if find that at this moment the value of GPIO pin does not change, then show system extremely at link this part of HT, at this moment system is restarted by FPGA.Like this just having avoided the people is the situation of restarting.And if variation has taken place in discovery GPIO pin at this moment, prove that then PMON has carried out the code of this delegation, that is to say the link success of HT, then FPGA does not send reset signal to reset circuit.

Claims

1. automatically reset device of Godson mainboard based on FPGA, it is characterized in that: on the Godson mainboard, added fpga chip and reset circuit, described fpga chip receives the signal of the G PIO pin of Godson CPU, described fpga chip sends a signal to described reset circuit, and described reset circuit sends reset signal to Godson CPU, north bridge chips and South Bridge chip.

2. device as claimed in claim 1 is characterized in that: when the Godson mainboard starts, check out after whether the HT bus connect at PMON, load the assignment program GPIO pin is carried out assignment.

3. device as claimed in claim 2 is characterized in that: described assignment program is not operated the GPIO pin when the HT bus does not connect; After on the HT bus connects, to GPIO pin assignment.

4. device as claimed in claim 1 is characterized in that: described FPGA begins to detect GPIO pin value after the time of setting.

5. device as claimed in claim 4 is characterized in that: if described GPIO pin value 0, then FPGA sends signal and gives reset circuit; Described GPIO pin value is if be not 0, and then FPGA does not send signal.

6. device as claimed in claim 5 is characterized in that: described reset circuit sends reset signal and gives Godson CPU after receiving the signal of FPGA, and north bridge chips and South Bridge chip restart.

7. device as claimed in claim 1 is characterized in that: the initial value of described GPIO pin is 0.

8. device as claimed in claim 4 is characterized in that: the time of described setting is to set in FPGA by program.