CN102063081A - Design method for realizing power on and off and time sequence resetting of Loongson mainboard by utilizing state machine - Google Patents

Design method for realizing power on and off and time sequence resetting of Loongson mainboard by utilizing state machine Download PDF

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Publication number
CN102063081A
CN102063081A CN2010105364985A CN201010536498A CN102063081A CN 102063081 A CN102063081 A CN 102063081A CN 2010105364985 A CN2010105364985 A CN 2010105364985A CN 201010536498 A CN201010536498 A CN 201010536498A CN 102063081 A CN102063081 A CN 102063081A
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state
power
state machine
mainboard
slp
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CN102063081B (en
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王晖
郑臣明
柳胜杰
王英
郝志彬
梁发清
邵宗有
刘新春
方信我
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Zhongke Hongtai Electronics Co ltd
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TIANJIN SUGON COMPUTER INDUSTRY Co Ltd
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Abstract

The invention provides a design method for power on and off of a Loongson mainboard, in particular relates to a design method for realizing power on and off and time sequence resetting of a Loongson mainboard by utilizing a state machine. The design method comprises the following steps of: A, initiating the mainboard into an Idle state; B, after the machine is started, sending a high level signal of Slp-s5=1 by a south bridge; C, after a programmable logic device receives the signal of Slp-s5=1, starting to run the state machine to enter an S0 state; D, sending a power supply control logic, a resetting logic of south and north bridges and a resetting logic of a Loongson CPU by the state machine; E, after the machine is started for 4s through long pressing, sending a low level signal of Slp-s5=0 by the south bridge; F, after the programmable logic device receives the signal of Slp-s5=0, enabling the state machine to enter an S5 state; and G, executing the power off state by the state machine, and returning to the Idle state after a 12V power supply is switched off. The method for controlling the power on and off and the time sequence resetting through the state machine by utilizing the programmable logic device, which is provided by the invention, has excellent availability and can stably play the roles of starting up and shutting down.

Description

A kind of method for designing that adopts state machine to realize Godson mainboard power-on and power-off and reset timing
Technical field
The invention provides a kind of method for designing of mainboard power-on and power-off, be specifically related to a kind of method for designing that adopts state machine to realize Godson mainboard power-on and power-off and reset timing.
Background technology
Designing in the process of X86 mainboard at present, control main board power-on and power-off and the method that resets mainly be to realize by the method that discharges and recharges delay of regulating resistance and electric capacity, but such method have a very big drawback: be exactly dumb; Especially when just beginning to debug motherboard circuit, owing to need choose the parameter of resistance and electric capacity, can be very time-consuming, and might be under situation about not choosing, can bring serious consequence to circuit, and for the Godson mainboard, because its processor architecture is based on MIPS's, and power-on and power-off and the method that resets and the mainboard of traditional X86 framework have a little different: mainly show in the accurate control to the time, if therefore the mode of having selected for use electric capacity and resistance to discharge and recharge is debugged, can be very time-consuming, if a parameter is not chosen, destroyed the sequential that powers on and reset and to have caused very big influence to the Godson mainboard.
Summary of the invention
In order to can be good at solving the power-on and power-off and the reset timing problem of Godson mainboard, but the present invention has adopted the method for use programming in logic device (FPGA) to realize that state machine is used for controlling the power-on and power-off and the reset timing problem of Godson mainboard.
A kind of method for designing that adopts state machine to realize Godson mainboard power-on and power-off and reset timing uses programmable logic device (PLD) FPGA to realize, may further comprise the steps:
A, initial mainboard are the Idle state;
After B, the start, south bridge sends the high signal of Slp_s5=1;
After C, programmable logic device (PLD) received the Slp_s5=1 signal, the running of initial state machine entered the S0 state;
D, state machine send the reseting logic of power control logic, north and south bridge and the reseting logic of Godson CPU;
E, long by behind the start 4s, south bridge sends the low level signal of Slp_s5=0;
After F, programmable logic device (PLD) received the Slp_s5=0 signal, state machine entered the S5 state;
G, state machine are carried out power-down state, return the Idle state after closing the 12V power supply.
A kind of optimal technical scheme of the present invention is: the described Idle state representation mainboard plug that just plugged in, this is only to treat electromechanics, described S0 state representation be the mainboard power-up state, described S5 state representation be the mainboard power-down state.
But usefulness programming in logic device proposed by the invention realizes that the method that state machine goes to control power-on and power-off and reset timing has good availability, and the effect of playing startup and shutdown that can be highly stable.
Description of drawings
Fig. 1 is a state transition diagram of the present invention
Fig. 2 is mainboard signal controlling figure of the present invention
Embodiment
What represent among Fig. 1 is designed state transitions synoptic diagram among the present invention.The power-on and power-off sequential of Godson mainboard all is to carry out according to the running of this state machine.
Idle: the expression mainboard plug that just plugged in, this is to have only Standby.
S0: expression be power-up state.
S5: the state of electricity under being of expression.
As can see from Figure 1, when not pressing mainboard start button, be in the Idle state, at this moment Slp_s5 is a low level 0.And in case after pressing the start button, it is high level 1 that the south bridge of mainboard can send Slp_s5, and at this moment when state machine detect Slp_s5 become 1 after, will jump to the S0 state, begin to carry out the logic of electrifying timing sequence, and in case long by after the start button 4s, it is low signal that south bridge can send Slp_s5, and at this moment state machine will jump to the S5 state, begins to carry out down electric sequential, and electric instantly sequential is carried out when closing the 12V power supply, just can get back to the Idle state again.And if, just can make the state machine entry into service again by the start button.This state machine is exactly the key that realizes whole mainboard power-on and power-off and reset timing.In this design, the most important point is the condition that chooses triggering, that is to say, need through after studying the databook of chip carefully, can choose this condition, be exactly the Slp_s5 signal that sends from south bridge and here we select, because, its change can bring the difference of above-mentioned state.

Claims (2)

1. a method for designing that adopts state machine to realize Godson mainboard power-on and power-off and reset timing is characterized in that, uses programmable logic device (PLD) FPGA to realize, may further comprise the steps:
A, initial mainboard are the Idle state;
After B, the start, south bridge sends the high signal of Slp_s5=1;
After C, programmable logic device (PLD) received the Slp_s5=1 signal, the running of initial state machine entered the S0 state;
D, state machine send the reseting logic of power control logic, north and south bridge and the reseting logic of Godson CPU;
E, long by behind the start 4s, south bridge sends the low level signal of Slp_s5=0;
After F, programmable logic device (PLD) received the Slp_s5=0 signal, state machine entered the S5 state;
G, state machine are carried out power-down state, return the Idle state after closing the 12V power supply.
2. a kind of method for designing that adopts state machine to realize Godson mainboard power-on and power-off and reset timing as claimed in claim 1, it is characterized in that: the described Idle state representation mainboard plug that just plugged in, this is only to treat electromechanics, described S0 state representation be the mainboard power-up state, described S5 state representation be the mainboard power-down state.
CN 201010536498 2010-11-04 2010-11-04 Design method for realizing power on and off and time sequence resetting of Loongson mainboard by utilizing state machine Active CN102063081B (en)

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Cited By (12)

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Publication number Priority date Publication date Assignee Title
CN102236570A (en) * 2011-07-21 2011-11-09 曙光信息产业(北京)有限公司 Method for soft shutdown of loongson blade
CN102236398A (en) * 2011-07-21 2011-11-09 曙光信息产业(北京)有限公司 Godson blade main board cold start method
CN102253704A (en) * 2011-07-21 2011-11-23 曙光信息产业股份有限公司 Device for meeting electrifying time sequence requirement of LoongSon CPU (central processing unit)
CN102270028A (en) * 2011-07-21 2011-12-07 曙光信息产业股份有限公司 Automatic Loongson mainboard resetting device based on field programmable gate array (FPGA)
CN105759663A (en) * 2014-12-16 2016-07-13 研祥智能科技股份有限公司 Industrial equipment monitoring processing method and system thereof
CN105827927A (en) * 2015-01-05 2016-08-03 速位互动系统有限公司 Method for controlling state machine of camera and camera
CN105955085A (en) * 2016-06-13 2016-09-21 中国科学院等离子体物理研究所 Method for realizing real-time control of power supply system by using EPICS-based finite-state machine
CN107992179A (en) * 2017-11-01 2018-05-04 湖北三江航天万峰科技发展有限公司 A kind of power-on and power-off of multi processor platform and repositioning control device
CN109657474A (en) * 2018-11-30 2019-04-19 江苏航天龙梦信息技术有限公司 The mainboard control sequential and power-on time sequence control method of compatible individual secure card
CN112463443A (en) * 2020-11-18 2021-03-09 北京东土科技股份有限公司 Server with AC LOSS function and method for automatically powering on and starting up after abnormal power failure
CN114995262A (en) * 2022-08-05 2022-09-02 成都万创科技股份有限公司 Power supply time sequence control method and system of X86 platform
CN117893638A (en) * 2024-03-18 2024-04-16 上海朋熙半导体有限公司 Timing diagram generation method, device and equipment of fusion state machine and storage medium

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Cited By (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102236398A (en) * 2011-07-21 2011-11-09 曙光信息产业(北京)有限公司 Godson blade main board cold start method
CN102253704A (en) * 2011-07-21 2011-11-23 曙光信息产业股份有限公司 Device for meeting electrifying time sequence requirement of LoongSon CPU (central processing unit)
CN102270028A (en) * 2011-07-21 2011-12-07 曙光信息产业股份有限公司 Automatic Loongson mainboard resetting device based on field programmable gate array (FPGA)
CN102236570B (en) * 2011-07-21 2014-07-02 曙光信息产业(北京)有限公司 Method for soft shutdown of loongson blade
CN102236570A (en) * 2011-07-21 2011-11-09 曙光信息产业(北京)有限公司 Method for soft shutdown of loongson blade
CN105759663B (en) * 2014-12-16 2019-08-20 研祥智能科技股份有限公司 Industrial device controls treating method and apparatus
CN105759663A (en) * 2014-12-16 2016-07-13 研祥智能科技股份有限公司 Industrial equipment monitoring processing method and system thereof
CN105827927A (en) * 2015-01-05 2016-08-03 速位互动系统有限公司 Method for controlling state machine of camera and camera
CN105955085A (en) * 2016-06-13 2016-09-21 中国科学院等离子体物理研究所 Method for realizing real-time control of power supply system by using EPICS-based finite-state machine
CN107992179A (en) * 2017-11-01 2018-05-04 湖北三江航天万峰科技发展有限公司 A kind of power-on and power-off of multi processor platform and repositioning control device
CN107992179B (en) * 2017-11-01 2020-08-11 湖北三江航天万峰科技发展有限公司 Power-on and power-off and reset control device of multiprocessor platform
CN109657474A (en) * 2018-11-30 2019-04-19 江苏航天龙梦信息技术有限公司 The mainboard control sequential and power-on time sequence control method of compatible individual secure card
CN109657474B (en) * 2018-11-30 2023-07-11 江苏航天龙梦信息技术有限公司 Motherboard control time sequence compatible with independent safety card and power-on time sequence control method
CN112463443A (en) * 2020-11-18 2021-03-09 北京东土科技股份有限公司 Server with AC LOSS function and method for automatically powering on and starting up after abnormal power failure
CN114995262A (en) * 2022-08-05 2022-09-02 成都万创科技股份有限公司 Power supply time sequence control method and system of X86 platform
CN117893638A (en) * 2024-03-18 2024-04-16 上海朋熙半导体有限公司 Timing diagram generation method, device and equipment of fusion state machine and storage medium
CN117893638B (en) * 2024-03-18 2024-06-11 上海朋熙半导体有限公司 Timing diagram generation method, device and equipment of fusion state machine and storage medium

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