CN102063081A

CN102063081A - Design method for realizing power on and off and time sequence resetting of Loongson mainboard by utilizing state machine

Info

Publication number: CN102063081A
Application number: CN2010105364985A
Authority: CN
Inventors: 王晖; 郑臣明; 柳胜杰; 王英; 郝志彬; 梁发清; 邵宗有; 刘新春; 方信我
Original assignee: TIANJIN SUGON COMPUTER INDUSTRY Co Ltd
Current assignee: Zhongke Hongtai Electronics Co ltd
Priority date: 2010-11-04
Filing date: 2010-11-04
Publication date: 2011-05-18
Anticipated expiration: 2030-11-04
Also published as: CN102063081B

Abstract

The invention provides a design method for power on and off of a Loongson mainboard, in particular relates to a design method for realizing power on and off and time sequence resetting of a Loongson mainboard by utilizing a state machine. The design method comprises the following steps of: A, initiating the mainboard into an Idle state; B, after the machine is started, sending a high level signal of Slp-s5=1 by a south bridge; C, after a programmable logic device receives the signal of Slp-s5=1, starting to run the state machine to enter an S0 state; D, sending a power supply control logic, a resetting logic of south and north bridges and a resetting logic of a Loongson CPU by the state machine; E, after the machine is started for 4s through long pressing, sending a low level signal of Slp-s5=0 by the south bridge; F, after the programmable logic device receives the signal of Slp-s5=0, enabling the state machine to enter an S5 state; and G, executing the power off state by the state machine, and returning to the Idle state after a 12V power supply is switched off. The method for controlling the power on and off and the time sequence resetting through the state machine by utilizing the programmable logic device, which is provided by the invention, has excellent availability and can stably play the roles of starting up and shutting down.

Description

A kind of method for designing that adopts state machine to realize Godson mainboard power-on and power-off and reset timing

Technical field

The invention provides a kind of method for designing of mainboard power-on and power-off, be specifically related to a kind of method for designing that adopts state machine to realize Godson mainboard power-on and power-off and reset timing.

Background technology

Designing in the process of X86 mainboard at present, control main board power-on and power-off and the method that resets mainly be to realize by the method that discharges and recharges delay of regulating resistance and electric capacity, but such method have a very big drawback: be exactly dumb; Especially when just beginning to debug motherboard circuit, owing to need choose the parameter of resistance and electric capacity, can be very time-consuming, and might be under situation about not choosing, can bring serious consequence to circuit, and for the Godson mainboard, because its processor architecture is based on MIPS's, and power-on and power-off and the method that resets and the mainboard of traditional X86 framework have a little different: mainly show in the accurate control to the time, if therefore the mode of having selected for use electric capacity and resistance to discharge and recharge is debugged, can be very time-consuming, if a parameter is not chosen, destroyed the sequential that powers on and reset and to have caused very big influence to the Godson mainboard.

Summary of the invention

In order to can be good at solving the power-on and power-off and the reset timing problem of Godson mainboard, but the present invention has adopted the method for use programming in logic device (FPGA) to realize that state machine is used for controlling the power-on and power-off and the reset timing problem of Godson mainboard.

A kind of method for designing that adopts state machine to realize Godson mainboard power-on and power-off and reset timing uses programmable logic device (PLD) FPGA to realize, may further comprise the steps:

A, initial mainboard are the Idle state;

After B, the start, south bridge sends the high signal of Slp_s5=1;

After C, programmable logic device (PLD) received the Slp_s5=1 signal, the running of initial state machine entered the S0 state;

D, state machine send the reseting logic of power control logic, north and south bridge and the reseting logic of Godson CPU;

E, long by behind the start 4s, south bridge sends the low level signal of Slp_s5=0;

After F, programmable logic device (PLD) received the Slp_s5=0 signal, state machine entered the S5 state;

G, state machine are carried out power-down state, return the Idle state after closing the 12V power supply.

A kind of optimal technical scheme of the present invention is: the described Idle state representation mainboard plug that just plugged in, this is only to treat electromechanics, described S0 state representation be the mainboard power-up state, described S5 state representation be the mainboard power-down state.

But usefulness programming in logic device proposed by the invention realizes that the method that state machine goes to control power-on and power-off and reset timing has good availability, and the effect of playing startup and shutdown that can be highly stable.

Description of drawings

Fig. 1 is a state transition diagram of the present invention

Fig. 2 is mainboard signal controlling figure of the present invention

Embodiment

What represent among Fig. 1 is designed state transitions synoptic diagram among the present invention.The power-on and power-off sequential of Godson mainboard all is to carry out according to the running of this state machine.

Idle: the expression mainboard plug that just plugged in, this is to have only Standby.

S0: expression be power-up state.

S5: the state of electricity under being of expression.

As can see from Figure 1, when not pressing mainboard start button, be in the Idle state, at this moment Slp_s5 is a low level 0.And in case after pressing the start button, it is high level 1 that the south bridge of mainboard can send Slp_s5, and at this moment when state machine detect Slp_s5 become 1 after, will jump to the S0 state, begin to carry out the logic of electrifying timing sequence, and in case long by after the start button 4s, it is low signal that south bridge can send Slp_s5, and at this moment state machine will jump to the S5 state, begins to carry out down electric sequential, and electric instantly sequential is carried out when closing the 12V power supply, just can get back to the Idle state again.And if, just can make the state machine entry into service again by the start button.This state machine is exactly the key that realizes whole mainboard power-on and power-off and reset timing.In this design, the most important point is the condition that chooses triggering, that is to say, need through after studying the databook of chip carefully, can choose this condition, be exactly the Slp_s5 signal that sends from south bridge and here we select, because, its change can bring the difference of above-mentioned state.

Claims

1. a method for designing that adopts state machine to realize Godson mainboard power-on and power-off and reset timing is characterized in that, uses programmable logic device (PLD) FPGA to realize, may further comprise the steps:

A, initial mainboard are the Idle state;

After B, the start, south bridge sends the high signal of Slp_s5=1;

2. a kind of method for designing that adopts state machine to realize Godson mainboard power-on and power-off and reset timing as claimed in claim 1, it is characterized in that: the described Idle state representation mainboard plug that just plugged in, this is only to treat electromechanics, described S0 state representation be the mainboard power-up state, described S5 state representation be the mainboard power-down state.