KR101741225B1 - A power saving apparatus and method of a computer system using SIO - Google Patents

Abstract

The present invention relates to a power saving apparatus and method of a computer system using an SIO. In a computer system having various operation modes (for example, S0-S5 modes), a 5VSB power source which is a first standby power source is used to drive a circuit only during a normal operation, and 3VSB which is a second standby power source is used for other operations, so electricity consumption is minimized. Minimum components are used by using an SIO. The power saving apparatus comprises: a super IO (19) provided with a power source from a power supply such as an SMPS (20) through an ATX power connector (60), and recognizing activation of a power button (13); a first switching unit (140) for outputting a first standby power source by controlling the super IO (19); a second switching unit (141) for outputting a second standby power source by controlling the super IO (19); a chipset (14) for receiving a power-on (PWBTN#) signal from the super IO (19), and notifying a current state (mode) through signal line terminals to the super IO (19) by responding thereto; and a first standby power source control signal generating unit (19a) and a second standby power source control signal generating unit (19b) for respectively generating control signals of the first standby power source and the second standby power source. The SIO (19) applies the second standby power source to a corresponding part in a general case, and controls to apply the first standby power source to the corresponding part when the corresponding part needs the first standby power source.

Description

Technical Field [0001] The present invention relates to a power saving apparatus and method for a computer system using a SIO,

The present invention relates to a technique for reducing the power consumption of a main board of a computer and a power supply unit supplied thereto. In the computer system, the 3VSB power supply is used instead of the 5VSB standby power supply, Port) or 5VSB power supply, and the remaining 3VSB is used to minimize power consumption, but the SIO is used to implement this with the minimum number of parts. To a power saving apparatus and method for a computer system of a computer system.

1, a power supply 20 such as an SMPS is connected to the SIO 12 of the main board 10 through 24 pins, one of which is connected to a standby Voltage (+ 5VSB).

When the user presses the power switch (not shown) of the PC case, the mechanically connected power button 13 is pressed, the power button 13 sends the first signal PWRBTN # to the SIO 12, The power supply 20 activates the power-on signal line PSON # with the power supply 20 and issues the second signal PWRBTN # _SB to the chipset 14. The power supply 20 is connected to the CPU 11 ) And the chipset 14 to inform it of the power supply signal, and then supply power to the main board.

Reference numeral 15 denotes a reset button of the chipset, 16 is a battery, 17 is a reset reset (17), and 18 is a LAN. In addition, AC, FWH, Super IO 19, AGP slot, PCI slot, IDE connected to the CPU and the chipset are connected.

Meanwhile, as described above, +5 V standby power is applied between the power supply 20 and the main board during non-operation, and standby power of about 1 W is required for recognizing the start button and recognizing the remote start do.

And this leads to a waste of energy, which is never high individually, and a huge amount of energy for a whole organization and even for a whole country.

In order to solve such a problem, there has been developed a socket having a switch which completely cuts off the power supply from the power socket itself to make the standby power zero (first prior art). On the other hand, Korean Patent Publication No. 2013-0043923 (Second conventional technique) for recognizing the on / off state of the power switch to completely shut off the power supply, such as the power supply device and the image forming apparatus including the power supply device.

However, in the case of the first prior art, in spite of the fact that it is practically possible for the user to sit in the outlet without turning off the power supply completely disconnected from the outlet, the second prior art is very complicated and expensive It is indispensable to mount such a device on a general PC.

Accordingly, the present inventor has proposed a computer power supply apparatus which is very simple but minimizes standby power automatically, and proposed Korean Patent No. 1328393 (name: computer power supply apparatus whose standby power is reduced) This will be described as a third prior art.

As shown in FIG. 2, the third prior art technology has a CPU 11, an SIO 12, a power button 13, a chipset 14, a reset button 15, a first battery 16, a LAN 18 ) And a super IO (19); An SMPS (20) for supplying power to the main board; A microcomputer 30 for controlling standby power supply of the SMPS; A power connector 60 for mediating signal and standby power connection between the main board and the SMPS; And a switching unit (40) for switching standby power on / off according to the control of the microcomputer. And the microcomputer 30 controls the standby power supplied to the main board by controlling the standby power (5VSB) of the power supply by the switching unit 40. [

2, the power supply apparatus of the third prior art includes an existing CPU 11, an SIO 12, a power button 13, a chipset 14, a reset button 15, A main board 10 having a power supply 16, a resetting reset 17, a LAN 18, a super IO 19, and the like, an SMPS 20 for supplying power to the main board, And a switching unit 40 for switching the standby power on / off according to the control of the microcomputer 30 and the microcomputer. The reference numeral 50 denotes a power switch of the PC case, and 60 denotes a power connector between the main board and the SMPS.

In the third prior art, the power connector 60 mediates signal and standby power connection between the main board 10 and the SMPS 20, and the SMPS 20 and the power connector are connected with 23 pins 1 is different from the conventional power supply of FIG. 1 in that a + 5V standby power line (+ 5VSB) which is one pin instead of a power connector is connected to the microcomputer 30 and the switching unit 40 instead of the power connector. The switching unit 40 may be a power switch IC or an FET circuit.

In addition, the microcomputer 30 receives the signal of either or both of the SMPS good signal (PS_ON #) and the power good signal (PWR_ON) from the SMPS 20 from the SMPS 20. The power good signal PWR_ON is also applied to the CPU 11 and the chipset 14.

Meanwhile, the microcomputer 30 also starts the standby power supply start operation by the switching signal CASE_PWR_BTN from the external case power switch 50, so that the standby power of +5 V (+ 5VSB) When the control signal 5VSB_SW of the microcomputer 30 is 'ON', the switching unit 40 applies the 5V standby signal P5V_STBY to the main board 10 through the switching unit 40, And the + 5V standby power (+ 5VSB) from the SMPS 20 is applied to the main board 10 as the 5V standby signal P5V_STBY.

From the SMPS (20) power connector to the mainboard (10) power connector, the PC's normal operating power goes to + 12V and -12V lines, + 5V standby power lines, + 3.3V power lines, and power hardening (PWR_ON) signals. However, the 5V standby power line (5VSB) goes to the switching device (40), and the standby power signal (P5V_STBY) goes from the switching device (40) back to the main board power connector.

Further, the standby power switch signal 5VSB_SW from the microcomputer 30 to the switching unit 40 and the power button signal MB_PWR_BTN to the main power button 12 go.

Conversely, the SMPS good (PS_ON #) signal goes from the mainboard 10 power connector to the SMPS 20 power connector.

First, the microcomputer 30 of the third prior art controls the standby power (5VSB) of the power supply by the switching unit 40 so as to control the power supplied to the main board When the power is off, the microcomputer senses the power cord PWR_ON and / or SMPS good signal (PS_ON #) between the connectors, and turns off the 5V standby power when the power is off. That is, in this case, since standby power is not supplied to the main board, the computer can not be turned on.

On the other hand, when the PC user presses the case power switch 50, the microcomputer 30 of the third prior art is activated by this signal, and the microcomputer controls the power good PWR_ON and / or the SMPS good PS_ON # And when the power is on, the control signal 5VSB_SW to the switching unit 40 is turned on so that the 5V standby power source 5VSB is applied to the main board. When the power button 13 of the main board is turned on, an input / output start command is issued to the SIO 12, and the SIO 12 transmits power supply completion signal PS_ON # to the SMPS 20 via the power connector 60. [ The SMPS transmits the PWR_ON signal to the main board 10 via the connector 60 and activates the main board operation power source (+12 V) when the situation is normal.

Therefore, according to the third prior art, standby power and computer start-up can be performed only by standby power of about 0.1 W corresponding to the standby power of the microcomputer without consuming standby power of 1 W corresponding to standby power of the computer activation system There are advantages.

By the way, the system is powered on. And 'off', recent PCs adopt the S1 to S5 mode, adopting various refined modes, thereby achieving the most efficient system operation with higher speed and resource utilization. For reference, the S0 mode is a computer operation mode, the S1 mode is a state in which the processor is in an idle state and is in a low power supply state or a state in which power is still supplied to the RAM, and S2 mode is a deep sleep mode However, in the S3 mode (power saving / standby mode), the power is still supplied to the RAM. In this case, the + 5V SB should not be turned off as the data is stored in the memory and the minimum power is maintained. At this time, depending on the type of DDR memory, VDD power is maintained at 1.2 ~ 1.5V, but power is supplied only to some parts such as memory and RTC. On the other hand, in S4 mode (hibernate mode), the data is stored on the hard disk and all the system power is turned off. That is, it is almost the same as the power OFF state. At this time, VDD power of memory is output as 0 V as when power is OFF. In other words, the VDD signal is 0 V in the OFF state of the system standby power and in the case of the S4 mode, and the system operation which is the standby power ON condition (Power ON state) and S3 (power saving / standby mode), the VDD signal outputs 1.2 to 1.5V.

Therefore, in the case of the system having the recent S0 to S5 mode, in the case of the third prior art, it is necessary to check all the states of the power source in order to block such standby power. 2) Checking some signals such as 'power good', and checking them. 1) When checking the current, an expensive analog-to-digital converter (ADC) and a peripheral circuit are required There is no cost-effective value to reduce standby power of 1W. 2) Also, when checking through signals such as 'power good', all power can not be checked by one signal. Therefore, Structure, which leads to a problem of low production efficiency.

On the other hand, a conventional general power-on operation will be described with reference to Figs. 3 to 7. Fig.

3, the PS_ON circuit 19a in the super IO 19 recognizes the power ON state when the power button is turned on, as shown in FIG. 3, The PS_ON # terminal of the 20-pin connector of the SIO 12 of the main board 10 is activated while communicating with the south bridge of the chipset 14 so that power is applied to the main board 10.

An example of the block diagram of the PS_ON circuit 19a of FIG. 3 is shown in detail in FIG. 4, when the switch S1 corresponding to the power button is pressed, the PS_ON circuit 19a is activated while falling to a low level, so that various voltages are applied from the SMPS to the main board (See the timing chart of Fig.

On the other hand, FIG. 6 shows another example of a conventional power-on operation concept. When power-on switching (PWR) is performed, the chipset 14 transmits the P.ON signal to the SIO 12, And the SIO 12 outputs the PON signal to the PS_ON # terminal of the connector of the main board so that the power is applied from the SMPS to the main board.

FIG. 7 is a timing chart of the signals of FIG. 6, and when the VAC is activated (AC power is applied), the PS_ON # signal is activated while falling to a low level and various voltages are applied from the SMPS to the main board, It responds with a good signal.

6, the PS_ON # signal (SMPS power on) is also turned on first by turning on the + 5V SB signal and then by connecting the south bridge and the Super I / O chipset , The PS_ON # signal is generated in the SMPS, and the connection and remodeling workability of the cable is poor, resulting in low productivity.

In order to solve the above problems, the inventor of the present invention has proposed a computer power supply apparatus which is very simple and automatically minimizes standby power even in a computer system having various operation modes, And proposed a computer power supply device that reduces standby power and has been patented as a patent No. 1623756. [ This will be described with reference to FIG. 2 and FIGS. 8 to 10. FIG.

FIG. 8 is a block diagram of a computer power supply apparatus in which standby power is reduced according to a fourth conventional technique, FIG. 9 is a detailed circuit diagram of a computer power supply apparatus in which standby power is reduced according to a fourth conventional technique, 4 is a flowchart of the operation of the microcomputer of the computer power supply apparatus in which the standby power according to the related art is reduced.

First, the invention of the fourth related art will be described with reference to the block diagram of FIG. 8. First, it is detected whether the PC power source 50 is 'on', and the ATX power cable from the SMPS 20 to the main board Activate the PS_ON # signal to the 'low' level, causing the line except the 5V SB line to go to the mainboard. At this time, the 5V SB line does not go directly to the main board but provides Vcc to the microcomputer 30 and the first switching unit 40 and activates them, thereby activating the power control signal PWR_CTRL, The first switching unit 40 sends the power output signal PWR_OUT to the 5V SB terminal of the mainboard so that the main board is operated while all the power is supplied to the main board do.

At this time, the microcomputer 30 applies the PS_ON # signal to the SMPS 20 to turn on the SMPS, and the signal and the common ground signal interlocked therewith are transmitted from the SMPS to the main board 10 via the ATX cable, The microcomputer 30 may directly supply the PS_ON # signal to the main board through the second switching unit 41 without passing through the SMPS, as shown in FIG. 8, , But it is also possible to apply it to the PS_ON # terminal of the power connector 60 through the power button 13, the PS_ON circuit 19a, and the main board.

9, the on / off state of the PC power 'on' switch 50 is provided through the switching input (SW_IN) terminal (pin 16 of the chip) of the microcomputer 30 .

Thereafter, the microcomputer 30 activates the common ground terminal (turns from 'high' to 'low') so that all of the 5V, 3.3V, 12V, power cord (PWR_OK) So that various powers are applied from the SMPS to the main board. In addition, the PS_ON # signal may be output to the SMPS 20 through the PS_ON # terminal (pin 2 of the chip) and may be connected to the corresponding terminal of the power connector 60 of the main board 10 through the ATX power cable 9, the SW_OUT signal is output to the second switching unit 41 through the fifth terminal of the microcomputer, and the switching signal is output to the super IO 19 through the power button # 13 in the main board To the corresponding terminal of the power connector 60 by activating the PS_ON circuit 19a.

The power control signal PWR_CTRL is output through the 14th pin of the microcomputer 30 to activate the first and third transistors Q1 and Q3 of the switching unit 40 to output the power output PWR_OUT signal To the 5V standby signal terminal of the connector of the main board 10. This means that the main board (computer) including the function of the memory finally operates.

Lastly, the voltage supplied to the memory (for example, DDR3) of the main board 10 is sensed by the fourth transistor Q4 of the sensing unit 70, and the result is the power GD_PWR Pin 15 of the chip).

The operation of the microcomputer of the fourth conventional art will be described once again with reference to FIG.

First, the microcomputer 30 of the present invention is operated when the system standby power is in the off state (in a state in which the AC power is not inputted). (S1). In such a case, is the PC power switch "on"? The power control signal PWR_CTRL (PWR_CTRL) is set to the power control signal PWR_CTRL (step S2). If the power control signal PWR_CTRL The switching unit 40 sends the power output signal PWR_OUT to the 5V SB terminal of the mainboard so that all the power is supplied to the main board S3). At the same time, the power button # 13 is activated and the PS_ON # signal is activated to operate the main board (S4 ').

That is, the microcomputer 30 receives a signal that the PC power switch is 'on', activates the power control signal PWR_CTRL to the first switching unit 40, and outputs the power output signal PWR_OUT) to the 5V SB terminal of the main board to supply all the power to the main board (S3) and to output the switching-out signal (SW_OUT) to another second switching unit 41 The transistor Q2 of the second switching unit 41 is turned on and the PS_ON # signal is applied to the power button 13 of the main board so that the power button 13 and the super I / The PS_ON # terminal of the connector 60 is activated through the PS_ON circuit 19a of the controller 19 to operate the main board (S4 ').

Thereafter, the voltage V _DD supplied to the memory 10a of the main board is checked (S5), and it is determined whether it is less than a predetermined voltage (for example, 0.7 V) (S6). If the voltage is abnormal ), The 5V SB power 'on' state is maintained and power supply to the main board is continued. Otherwise, the memory is considered to have stopped operating, and the power control signal PWR_CTRL is deactivated, The switching unit 40 disables the power output signal PWR_OUT and turns off the system standby power in step S7.

That is, as described above in the related art, the + 5V SB should not be turned off in the S3 mode (power saving / standby mode), while in the S4 mode (the maximum power saving mode) Turn off all power. That is, in the S4 mode and the S5 mode in which the power is OFF, 0V is output. In other words, the VDD signal is 0 V in the OFF state of the system standby power and in the case of the S4 mode, and the system operation which is the standby power ON condition (Power ON state) and S3 (power saving / standby mode), the VDD signal outputs 1.2 to 1.5V. Therefore, in S5 and S6, the voltage V _DD supplied to the memory is checked (S5), and it is determined whether or not it is less than a predetermined voltage (Vr: 0.7 V, for example) The power 'on' state is maintained, and less than (V _DD ≪ Vr), the system standby power is turned off (S7).

The fourth prior art recognizes the S3 and S4 modes by a relatively simple method of checking the voltage (V _DD ) supplied to the memory and continues to supply the 5V standby power in the S3 mode, In the S4 mode, the standby power is cut off to save power in the dash mode. However, there is an advantage that it can be performed without additional cable construction.

However, in S3 (standby / power saving mode), in addition to the specific mode, there is no need to supply standby power of 5 V, and only standby power of about 3 V is sufficient.

In addition, in the above-mentioned conventional techniques, since the mode recognition such as S3 and S4 is checked with a voltage in a secondary device such as a memory, a separate device for checking the mode is necessary. In addition, A wiring to the microcomputer and a separate cable are required. In addition, although the possibility is very low, there is a problem that the system can not accurately sense the inconsistency between the secondary device such as the current mode and the memory due to the error of the system.

Korean Patent Publication No. 2013-0043923 (Patent Application No. 2011-0108115) Korea Patent No. 1328393 (name: computer power supply device for saving standby power) Korean Patent No. 1623756 (Title: Standby power cutoff method of standby power cutoff device using system memory power)

In the computer system having various operation modes (for example, S0 to S5 mode), the present invention is a little more advanced in the technology for blocking standby power currently being actively developed, so that even in S3 mode, It is necessary to use the 5VSB power supply for the circuit operation only in the normal operation and the 3VSB power supply for the rest of the operation so as to minimize the power consumption but use the SIO And more particularly, to a power saving apparatus and method for a computer system of a computer system.

Furthermore, according to the present invention, 5V standby power is supplied even in the standby mode in a special situation such as charging the smartphone using the USB, and by utilizing the SIO, Implementation has its purpose.

According to an aspect of the present invention, there is provided an apparatus for reducing power consumption of a computer system using an SIO according to an aspect of the present invention includes a first standby power source as a standby power source, The present invention relates to a power saving device for a computer system using an SIO that controls a second standby power supply with a lower voltage than a power supply to selectively apply a second standby power supply even when the computer system is in operation. A super IO 19 receiving power from the power supply and recognizing when the power button 13 is activated; A first switching unit 140 for selectively outputting the first standby power through a first switching device 10d 'turned on / off under the control of the super IO 19; A voltage regulator 10e and a second switching device 10e 'for dropping the first standby power supplied from the power supply such as the SMPS 20 through the ATX power connector 60 to the second standby power supply And the second standby power source that is lowered by the voltage regulator 10e is always supplied to the operation power supply of the super IO 19 while the second standby power is turned on and off by the control of the super IO 19, A second switching unit 141 for selectively outputting the second standby power through the element 10e '; A chipset 14 receiving a power on (PWBTN #) signal from the super I / O 19 and informing the super I / O 19 of the current state (mode) through signal line terminals; A first standby power supply control signal generating unit 19a and a second standby power supply control signal generating unit 19b which are located in the super IO 19 and generate control signals of the first standby power supply and the second standby power supply, ; When the power is switched on, the super IO 19 controls the first standby power supply to be supplied to the corresponding part. If the second standby power is stabilized even while the computer system is operating, the super IO The first standby power source 19 controls the second standby power source to be supplied to the corresponding part in place of the first standby power source. When the power source is in the power off state, the super standby IO 19 supplies both the first standby power source and the second standby power source The super-IO 19 controls the second standby power source to be in a normal state when the second standby power source is stabilized, The first standby power source is controlled to apply the first standby power source to the corresponding part, and when the first standby power source is required, And the data terminals D + and D- of at least one USB are short-circuited when the external connection electric device is being used.

Preferably, the 5VSB power source as the first standby power source and the 3VSB power source as the second standby power source are connected to the USB ports 101 and 102 via the first constant voltage diode ZD1 and the second constant voltage diode ZD2, , And they are controlled by the terminals 'GPIO 1' and 'GPIO 2' connected through the resistors R3 to R6 and the diodes D1 to D2, respectively.

According to another aspect of the present invention, there is provided a method for power saving a computer system using an SIO, the method comprising: (c) determining whether the second standby power source is stable during operation of the computer system ); (d) If it is determined that the second standby power source is not in a stable state as a result of the determination in step (c), the control unit continuously checks whether the first standby power source is required. (S19, S20) of applying the first standby power supply to a corresponding portion of the entire system, or otherwise applying the second standby power supply to a corresponding portion of the entire system; (e) determining whether the apparatus is in a standby mode after step (d) (S31); (f) interrupting various operation power sources when the result of step (e) is 'yes' (S33); (i) determining whether power is off (S39); And (j) shutting off all the standby power supply if the determination result in step (i) is 'YES' (S41); And a control unit.

Preferably, step (d) further comprises: (d1) continuously checking if the second standby power supply is not in a stable state, and when the second standby power supply is in a stable state, (S19); (d2) a step (S21) of searching whether or not the first standby power source needs to be used after the step (d1); (d3) judging that it is necessary to use the first standby power source in the step (d2) (S23) of applying the first standby power source to the corresponding region when the first standby power source is turned on; (d4) a step (S27) of searching whether or not the necessity of using the first standby power source has disappeared since the step (d3); And (d5) when the necessity of using the first standby power source does not disappear in the step (d4), if it is unnecessary to use the first standby power source, A step (S29) of applying a second standby power supply to the corresponding region; .

Preferably, in the step (d), the first standby power source is required to charge the external device through the USB port.

More preferably, in step (d1), the step (S19) of supplying the second standby power supply to a corresponding part of the entire system sets 5VSB = 'L', 3VSB = 'H' (L) and GPIO_2 = 'H'. In step (d3), the step (S23) of supplying the first standby power supply to the corresponding part of the entire system is performed by setting 5VSB = 'H' 3VSB = "L", and GPIO_1 = "H" and GPIO_2 = "L".

Also, preferably, between step (f) and step (i), (g) step (S35) of determining whether or not the wakeup state is present after step (f); And (h) if it is determined to be YES in step (g), applying various operation power sources to the entire system to transition to an operational state (S37); Wherein the power saving method further includes the steps of:

Also preferably, before step (c), (a) determining whether the power switch is in an 'on' state (S11); And (b) if the power switch is not in the ON state as a result of the determination in step (a), continuously checking the power switch, and if it is YES, applying the first standby power source and various operating power sources to the entire system S13); And further comprising:

According to the apparatus and method for reducing power consumption of a computer system using the SIO according to the present invention, energy savings can be achieved by minimizing standby power cutoff and operation power by using minimum components in a computer system having various operation modes, 5VSB power is used only when necessary, and the remaining standby power supply uses 3VSB, so that power loss through standby power is minimized even during operation. Furthermore, the power of the USB port is usually 3VSB It minimizes the power consumption by using the minimum power consumption by minimizing power consumption and intelligent power management that automatically detects and changes the power when 5VSB, such as charging the smartphone, is needed.

Other objects and advantages of the present invention will become apparent from the detailed description of the embodiments with reference to the attached drawings.

1 is a conceptual diagram of a conventional computer power supply;
2 is a block diagram of a computer power supply in which standby power is reduced according to the third prior art.
3 is a view for explaining a concept of a conventional general power-on operation;
4 is a block diagram of the PS_ON circuit 19a of Fig.
5 is a timing chart of the signals of FIG. 3;
FIG. 6 is another example of a concept of a conventional general power-on operation; FIG.
FIG. 7 is a timing chart of the signals of FIG. 6; FIG.
FIG. 8 is a block diagram of a computer power supply in which standby power is reduced according to a fourth prior art; FIG.
FIG. 9 is a detailed circuit diagram of a computer power supply apparatus in which standby power is reduced according to a fourth prior art; FIG.
FIG. 10 is a flowchart illustrating an operation of a microcomputer of a computer power supply apparatus according to a fourth prior art in which standby power is reduced. FIG.
11 is a system configuration diagram of a prior invention related to the present invention;
FIG. 12 is a system configuration diagram showing only the components directly related to the present invention among the inventive system related to the present invention; FIG.
FIG. 13 is a flowchart of the operation of the super IO of a computer system in which the power consumption is reduced according to the present invention related to the present invention. FIG.
14 is a system configuration diagram according to the present invention.
FIG. 15 is a flowchart of the operation of the super IO of a computer system in which power is reduced according to the present invention. FIG.
16 is a flowchart of the operation of the subroutine relating to the USB port charging mode process of FIG.

Hereinafter, preferred embodiments according to the present invention will be described in detail with reference to the accompanying drawings.

It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the invention, You will know.

For reference, Korean Patent Application No. 2016-0087595 (a power saving apparatus and method of a computer system using a GPIO port, and a computer system utilizing the same) (hereinafter referred to as the " ), And the contents of the specification of the above patent application are also taken into consideration in the specification of the present application. However, the technology of the above-mentioned prior invention is not a known technology disclosed before the filing of the present application.

(Prior invention relating to the present invention)

First, an embodiment of a method and an apparatus for measuring the operating state of a computer system of the present invention will be described with reference to Figs. 11 to 13. Fig.

FIG. 11 is a system configuration diagram of a prior invention according to the present invention related to the present invention, FIG. 12 is a system configuration diagram showing only components directly related to the present invention among systems of the prior invention related to the present invention, Fig. 2 is a flowchart illustrating a super IO operation of a computer system in which power of the invention is reduced.

11 and 12, the power saving device of the computer system of the first aspect of the present invention includes a first switching unit 40 and a second switching unit 40 between the super IO 19 and the ATX power connector 60 in the main board, And a second switching unit 41 is added between the chip set (PCH) 19 and the chipset (PCH) 14.

As shown in FIG. 2, the power supply in the general computer system is performed through a power supply such as the SMPS 20 through the ATX power connector 60 to the main board 10, for example, through a 5VSB power line The power saving is performed through a device such as the microcomputer 30 that performs appropriate control.

11, the super-IO 19 receives power from a power supply such as the SMPS 20 through the ATX power connector 60. More specifically, the power button 13 The power state detector 19b in the super IO 19 recognizes it and outputs a power on signal PWRON # to the chipset 14. In response, the chipset 14 receives the power on signal from the super IO 19, The power state detector 19b in the super IO 19 responds to the current power state (mode) via the SLP_4 and SLP_3 signal line terminals via the first switching unit 40 and the ATX power connector 60 to start the super IO 19 operation. 11, the functions of the 'System IO' 12 (see 'SIO' in FIGS. 1 and 2) are usually performed by the chipset 14, and the 'SIO' Super IO '.

On the other hand, in the case of the present invention, when the power state detector 19b in the super IO 19 recognizes activation of the power button 13 and outputs a power-on (PWRON #) signal to the chipset 14, (Mode) through the 'SLP_4' and the 'SLP_3' signal line terminals from the chipset 14 is the same as that of the prior art. However, according to the present invention, a different operation is performed through the GPIO port . For reference, generally, the Super IO chip has about 50 general purpose input output (GPIO) ports, which can be programmed to a specific purpose port by the BIOS, 'GPIO A' port and 'GPIO B' port.

The power state detector 19b of the super IO 19 determines whether the current power state is the S4 mode (the maximum power saving mode) through the SLP_4 signal line terminal from the chipset 14, L 'signal to the control terminal of the third transistor Q3 of the first switching unit 40 through the port of the ATX power connector 60 and at the same time the super IO 19 activates the PSON # . The signal 5VSB_ATX of the output terminal OUT of the first switching unit 40 is turned on by the switching operation of the third transistor Q3 and the first transistor Q1 of the first switching unit 40, (5V) voltage is applied to the PMOS 10d and is therefore applied to the PMOS 10d and the LDO 10e, which are a kind of voltage regulators. The 5VSB, which is the output of the PMOS 10d, becomes the first operating power of the system, 2 switching unit 41 and the output 3VSB of the LDO 10e is applied to the operation power source of the super IO 19 as the second operation power. Therefore, by using the super IO chip 19 and the 'GPIO B' port, it is possible to save power when the computer system is started, without using any additional device as compared with the prior art.

Subsequently, the super IO 19 determines whether the current power state is proceeding to the S3 mode (power saving / standby mode). If the current power state is S3 through the 'SLP_3' signal line terminal from the chipset 14, L "signal to the input side of the second switching unit 41 through the 'GPIO A' port of the super IO 19 when the mode is determined to be a power saving / standby mode, The switching unit 41 applies the output of the second switching unit 41 to the power supply terminal (3VSB / 5VSB terminal) of the super IO and the chipset 14 and the 'PWRBTN #' terminal of the chipset with the low voltage (3VSB) do.

At this time, when the 'H' signal is input to the input side by the peripheral devices such as resistances R3 to R5 and the capacitors C2 to C3 and the voltage regulator 41a, the second switching unit 41 In this case (power saving / standby mode), if only the minimum power supply is maintained and high voltage of 5V is not needed, it is controlled by low voltage (3VSB) so that the high voltage (5VSB) The total power consumption can be saved.

Subsequently, the super I / O 19 determines whether the current power state proceeds to the S3 mode (power saving / standby mode) and then proceeds to the operation mode S2 or less (i.e., S0 (computer operation mode) (Hereinafter, referred to as an 'S2 mode or an operation mode'), the current power state is switched to the mode S2 or less through the 'SLP_3' signal line terminal from the chipset 14 H 'signal to the input side of the second switching unit 41 through the' GPIO A 'port of the super I / O 19 when it is determined that the first switching unit (operation mode) 41 is applied to the power supply terminal (3VSB / 5VSB terminal) of the super IO and chipset 14 and the 'PWRBTN #' terminal of the chipset with the output of the second switching unit 41 being a high voltage (5VSB).

On the other hand, if the current power state (mode) is determined through the SLP_4 and SLP_3 signal line terminals from the chipset 14 and the SLP_4 is 'L', the computer system is already in the hibernation mode H 'at the input side of the second switching unit 41 through the' GPIO A 'port. If the' SLP_3 'signal line is' H', the system is woken up. Signal to the power supply terminal (3VSB / 5VSB terminal) of the super IO and chipset 14 and the 'PWRBTN #' terminal of the chipset by setting the output of the second switching unit 41 to a high voltage (5VSB) do.

Of course, when the current power state (mode) is determined through the SLP_4 and SLP_3 signal line terminals from the chipset 14 and the SLP_4 is L and the SLP_3 is L, H 'signal to the input side of the second switching unit 41 through the' GPIO A 'port and outputs the output of the second switching unit 41 to the high voltage (5VSB) .

Finally, since the computer system is operating as described above, the 'H' signal is continuously output to the input side of the second switching unit 41 through the 'GPIO A' port to output the output of the second switching unit 41 to the high voltage The power state detector 19b of the super IO 19 controls the third transistor Q3 of the first switching unit 40 via the GPIO B port, The output terminal of the first switching unit 40 is turned on by the switching operation of the third transistor Q3 and the first transistor Q1 of the first switching unit 40, The zero voltage (0V) is applied to the signal 5VSB_ATX of the output terminal OUT and the output of the PMOS 10d and the LDO 10e also becomes 0 V. Eventually, the operation of the super IO 19 is turned off, By using the super IO chip 19 and the ' GPIO B ' port, It is possible to prevent the power consumption at an early stage in the end of the system, thereby enabling the overall power saving.

Now, a power saving method of a computer system using the GPIO port of the above-mentioned invention will be described with reference to Figs. 11 to 13, particularly with reference mainly to Fig.

13, when the computer system is started, the power state detector 19b in the super IO 19 checks whether a power on (PWRON #) signal is generated (S11), and a power on (PWRON # SLP_4 "and" SLP_3 "signal lines from the chipset 14 in response to the power on (PWRON #) signal, if the power on (PWRON #) signal has not been generated (for example, if the power button has not been turned on) The current power state (mode) is checked. First, it is checked whether the 'SLP_4' signal line from the chipset 14 is 'H' (S12).

The power state detector 19b of the super I / O 19 determines that the GPIO B port is connected to the GPIO B port because the current power state is determined to be the S4 mode (the maximum power saving mode) when the SLP_4 signal line is' A high voltage is applied to the signal 5VSB_ATX of the output terminal OUT of the first switching unit 40 by outputting an L signal to the first switching unit 40 through the first switching unit 40, At the same time, the super IO 19 activates the PSON # signal (S15) and outputs it to the ATX power connector 60 so that the super IO 19 is activated.

The super IO 19 checks whether the 'SLP_3' signal line from the chipset 14 is 'H' (S17) and determines whether the current power state goes to S3 mode (power save / standby mode) (SLP_3 = 'H') is determined to be the S3 mode (power save / standby mode) through the 'SLP_3' signal line terminal from the chipset 14, L 'signal to the input side of the second switching unit 41 through the' GPIO A 'port in step S18. The second switching unit 41 then outputs the output of the second switching unit 41 (3VSB / 5VSB) of the chipset 14 and the 'PWRBTN #' terminal of the chipset as the low voltage (3VSB).

Thereafter, the super IO 19 checks whether the SLP_3 signal line is 'L' (S19) after the current power supply state proceeds to the S3 mode (power saving / standby mode) GPIO A 'of the super IO 19 is determined to be in a mode (operation mode) under the current power state through the SLP_3 signal line terminal from the chipset 14, The second switching unit 41 outputs the output of the second switching unit 41 as a high voltage (5VSB) to the input side of the second switching unit 41 through the port To the power supply terminal (3VSB / 5VSB terminal) of the super IO and chipset 14 and the 'PWRBTN #' terminal of the chipset. This results in a successful boot.

On the other hand, if it is determined in step S17 that the 'SLP_3' signal line is not 'H', it is checked whether the PWR_OFF state is satisfied (S32) And if it is not (power off), it is determined to be a boot error (S33).

If the SLP_3 is not 'L' in step S19, it is determined that the booting process is out of the normal booting process. Therefore, the process proceeds to step S32. In step S32, If it is not power-off, the process proceeds to step S19 and repeats. If the power is off, it is determined as a boot error (S33).

On the other hand, if it is determined in step S12 that 'SLP_4' is 'L', it indicates that the boot has already been performed. In this case as well, it is determined whether the 'SLP_3' signal line is 'H' (Step S14). If the SLP_3 is 'L', it means that the mode is the mode S2 (operation mode). Accordingly, the process proceeds to step S20, and the 'GPIO A' H "signal to the input side of the second switching unit 41 through the port of the second switching unit 41 and the second switching unit 41 outputs the output of the second switching unit 41 as the high voltage (5VSB) To the power supply terminal (3VSB / 5VSB terminal) of the chipset 14 and the 'PWRBTN #' terminal of the chipset.

However, if it is determined in step S14 that 'SLP_3' = 'H', it indicates that the system is in the S3 mode (standby / full-duplex mode) while operating after booting. , The process directly proceeds to step S20 and outputs 'H' signal to the input side of the second switching unit 41 through the 'GPIO A' port of the super IO 19. That is, in this case, since the S3 mode is the same as the step S18, the step S18 shows a state in which the S3 mode is changed from the S2 mode to the S3 mode, The process immediately goes to the step S20 and shifts to the operation mode.

Finally, when the booting has been successfully performed and the process proceeds to the sub-S2 mode (operation mode) (S11, S12, S1, S15, S17 to S20) (S21). If it is determined in step S21 that power-off is to be performed, GPIO = 'H', and output through the first switching unit 40 The system is terminated (S23). On the contrary, if the voltage is not turned off in the step S21, the process returns to the step S12 (S41) SLP_4 'and' SLP_3 'signal lines from the chipset 14 to determine whether to proceed with the next power state (mode).

As a result, according to the power saving method of the computer system using the GPIO port according to the above-mentioned invention, the GPIO port of the super IO chip is programmed through the BIOS without any additional hardware or cable installation work, It is possible to easily detect the current operating state of the system, and it is possible to save power at booting by only the first switching unit 40. [

In addition, it is possible to save power by applying 3VSB operating voltage instead of 5VSB even in S3 mode during boot, and switch to 3VSB operating voltage immediately after S4 mode in operation, There is an advantage that the second switching unit 41 can be operated without any additional sensing device or cable operation.

(Embodiment of the present invention)

Hereinafter, an embodiment of a method and an apparatus for measuring the operating state of the computer system of the present invention will be described with reference to Figs. 14 to 16. Fig.

FIG. 14 is a system configuration diagram according to the present invention, FIG. 15 is an operational flowchart of a super IO of a computer system in which power is reduced according to the present invention, FIG. 16 is a flowchart of a subroutine operation FIG.

14, in the main board, the super IO 19 is connected to the PMOS 10d and the ATX power connector 60 for the ATX power connector 60, And the LDO 10e is requested to apply the standby power of 5VSB and 3VSB, respectively.

At this time, the application of the first standby power of 5VSB through the PMOS 10d is controlled by the 5VSB control signal (5VSB On / off signal) generated by the 5VSB control signal generator 19a controlling the first switching element 10d ' The first switching device 10d 'is turned on by the 5VSB_ON signal applied to the first switching device 10d' of the first switching unit 140 so that the 5VSB standby power source Power supply) is applied to the chipset 14 and the super IO 19 or the like so that the first standby power supply of 5 V is supplied to the corresponding part requiring standby power of the entire computer system.

On the other hand, the application of the second standby power of 3VSB through the LDO 10e is controlled by the 3VSB control signal (3VSB On / off signal) generated by the 3VSB control signal generator 19b controlling the second switching element 10e ' The second switching device 10e 'is turned on as the 3VSB_ON signal is applied to the second switching device 10e' of the second switching unit 141 so that the 3VSB standby power is supplied to the chipset 14e by the LDO 10e And the super IO 19 so that a second standby power of 3 V is supplied to a corresponding portion requiring standby power of the entire computer system. However, the second standby power supply must be always supplied to the super IO 19 by the operation power of the super IO 19.

The 5VSB control signal generator 19a and the 3VSB control signal generator 19b will be described later.

On the other hand, the super IO 19 receives the on / off signal PANSW # of the system power button 13 and outputs the activation control signal to the chipset 14. First, the super IO 19 outputs the power button signal PWBTN # And outputs a 5VSB ON signal (5VSB_ON) to the switching unit (140) and simultaneously outputs a PSON # signal to the ATX power connector (60) to output ATX_5VSB Is stabilized to 5VSB by the PMOS 10d so that the first standby power of 5V is supplied to the system. The ATX_5VSB from the ATX power connector 60 is sensed by the SLP_SUS_FET device.

Meanwhile, the ATX_5VSB from the ATX power connector 60 is also applied to the second switching unit 141 and converted to 3V by the LDO 10e, which is recognized by the super IO 19 through the 3VSB_S terminal, The super IO 19 detects the application of the 3VSB power, and outputs the 3VSB initial signal RSMRST # to the chipset 14.

On the other hand, the chipset 14 detects the 3VSB initial signal RSMRST # through the RSMRST # terminal. If the signal is 'H', the chipset 14 outputs the second Standby power is applied, and whether the current mode is the operation mode is notified to the super IO through the SUSB # terminal and the SUSC # terminal.

For example, the SUSB # terminal signal is a signal for generating an inversion signal for every mode change such as S5-> S0-> S3-> S0-> S5, and the SUSC # terminal signal is 'L' It is a signal to output 'H' at S5.

Accordingly, when the 3VSB initial signal RSMRST # is 'H', the super IO 19 once sets the 5VSB control signal (5VSB On / off signal) to 'L' through the 5VSB control signal generator 19a, The 3VSB control signal generating unit 19b sets the 3VSB control signal (3VSB On / off signal) to 'H' so that the first switching device 10d 'of the first switching unit 140 is turned off, The second power source of 3VSB is applied to the entire system instead of the first power of 5VSB by controlling the second switching element 10e 'of the first switching element 141 to be turned on.

Thereafter, the Super IO 19 determines whether the mode is the S3 mode through the SUSB # terminal signal and the SUSC # terminal signal. If the mode is the S3 mode, the Super IO 19 sets the PS_ON # signal to 'H' S0 mode), the PS_ON # signal is set to 'L' because it is not in the standby mode.

On the other hand, in the case of the operating state, it is checked whether or not the power is off through the SUSC # terminal signal at predetermined time intervals, and if the power off (SUSC # = 'H'), the 5VSB control signal generating unit 19a and 3VSB The 5VSB control signal (5VSB On / off signal) and the 3VSB control signal (3VSB On / off signal) are both set to 'L' through the control signal generation unit 19b and the first switching unit The device 10d 'and the second switching device 10e' of the second switching unit 141 are all turned off so that all the power supplies of 5VSB and 3VSB are cut off.

As described above, in the standby mode according to the present invention, standby power is supplied instead of 5V by supplying standby power of 3V. However, when 5VSB is required, Intelligent power management that automatically detects and changes power to 5VSB is required.

For example, if you are charging a device such as a smart phone using a charging cable through a USB port, or you are using an external device (such as a small fan or smart headphone connected to a smartphone) , The data terminals (D + and D-) of the USB are short-circuited. Whether or not the 5V is required through the USB port can be judged as whether USB D + and D- are short-circuited.

In this embodiment, the port for checking the USB D + / D- in the Super I / O 19 designates a separate GPIO port as 'USB D +' and 'USB D-'. The detection circuit is provided for each USB port from the USB 1 101 to the USB n 102.

14, a 5VSB power source and a 3VSB power source are connected to the first and second constant voltage diodes ZD1 and ZD1, respectively, in each of the USB ports 101 and 102, And whether they are applied or not is controlled by the terminals GPIO1 and GPIO2 connected through the resistors R3 to R6 and the diodes D1 to D2.

That is, if 'GPIO 1' connected to 5VSB is 'Low', USB power 5VSB is OFF. If GPIO 2 is 'Low', USB power 3VSB is turned OFF. At this time, , And among them, 'GPIO 1' is controlled to 'High' when charging using the charging cable to the USB port, so that 5VSB is turned on.

As a result, according to the present invention, the standby mode is determined in an extremely simple manner by using the super I / O 19. In the standby mode, 3V standby power is applied instead of 5V to reduce power consumption, It is possible to realize a power saving device of a computer system using SIO which automatically supplies 5VSB power when it is necessary.

Now, a power saving method of a computer system using the SIO of the present invention will be described with reference to Figs. 14 to 16, particularly Figs. 15 and 16. Fig.

15, when the computer system is started, the super IO 19 checks whether the power on (PANSW #) signal of the system power button 13 is generated (S11), and the power on (PANSW # If the power-on (PANSW #) signal has been generated, the 5VSB_ON signal is set to 'H' to supply the standby power (S13) in response to the power ON (PANSW # , The PS_ON # signal is set to 'L', and all the operation power (3 V, 5 V) is applied to the first switch unit 140, the second switch unit 141, the super-ON 19 and other devices through the ATX power connector 60 , 12V, and the like) (S15).

In the present invention, it is determined whether the 3VSB branched from the 5VSB is stable, that is, the 3VBS initial signal (RSMRST #) is checked (S17) , And if RSMRST # = 'H', 5VSB = 'L', and 3VSB = 5VSB if the RSMRST # is not 'H' 'H', so that 3VSB power is supplied to the corresponding part of the entire system instead of 5VSB (S19).

Now, it is searched whether the 5VSB needs to be used, such as whether it is charging the smartphone using the USB port, which is the core of the present invention, and if necessary, 5VSB power is applied to the corresponding part of the whole system, Subsequently, the 3VSB is applied to the corresponding part of the entire system (S20).

Thereafter, it is determined whether or not the operation mode is advanced to the standby mode (S3 mode) (S31). If it is not the S3 mode, it is checked continuously (i.e., . If the operation mode is the S3 mode, the power supply of 12V or the like is cut off by setting PS_ON # = 'H' (S33), and it is checked whether or not the power is woken up again (S35) In other words, it is determined whether or not the power is turned off, and the operation is continued unless the power is off). When the wakeup is performed, the operation state is changed to PS_ON # = 'L' again (S37).

Finally, it is determined whether or not SUSC # = 'H' (S39). If it is determined that the power is off, the process returns to step S20, = 'L' and 3VSB_ON = 'L' (S41), all the standby power sources are shut off and the system is terminated (S43).

If NO in step S31 and step S35, the process goes to step S39 to determine whether or not SUSC # = 'H' to determine whether or not the power is off. If the power is off, the system is terminated, Otherwise, the process returns to step S20 and continues.

In step S31, there are various methods for determining whether the mode is the S3 mode. For example, it can be determined that the mode is the S3 mode when 3 VSB = 0V and the S0 mode when 3 VSB = 3.3V.

Now, finally, the USB port charging subroutine S20 will be described with reference to FIG.

First, it is determined whether or not the USB port is being charged (S21). It can be determined that the 'USB D +' terminal and the 'USB D-' terminal are short-circuited as described above.

That is, when charging a device such as a smart phone using a charging cable via a USB port or using an external connection electric device of a smart phone, the data terminals (D + and D-) of the USB are short-circuited 5VSB = 'H', 3VSB = 'L', GPIO_1 = 'H' and GPIO_2 = 'L' to control the 5VSB voltage to be applied to the corresponding USB port (S23). On the other hand, if not (GPIO_1 = 'H' and GPIO_2 = 'L'), the 3VSB voltage is applied to the corresponding USB port (S25) You can do this.

If charging is completed, 5VSB = 'L', 3VSB = 'H', GPIO_1 = 'L' and GPIO_2 = 'H' The process proceeds to step S31 while allowing the 3VSB voltage to be applied to the USB port (S29). If not (NO), the process proceeds to step S39 to check whether or not the power is off, Proceed from step S21.

According to the apparatus and method for reducing power consumption of a computer system using the SIO of the present invention, a low-voltage 3VSB voltage is applied instead of a 5VSB power to reduce overall power consumption, By selectively applying 5VSB power only when 5VSB, such as charging a smart phone using a port, is absolutely necessary, it is possible to reduce the total power consumption without affecting the existing system.

While the present invention has been described in connection with what is presently considered to be practical exemplary embodiments, it is to be understood that the invention is not limited to the disclosed embodiments, but, on the contrary, Of course.

(Prior art and prior invention)
10: main board 10a: memory
10b: ROM BIOS 10c: OS
10d: PMOS (P-type MOS) 10e: LDO (Low Dropout Voltage Regulator)
11: CPU 12: SIO (System IO)
13: Power button 14: Chipset
15: reset button 16: first battery
17: RESET RESET 18: LAN
19: Super IO (Super IO) 19a: PS_ON circuit
19b: Power state detector
20: Power supply (SMPS) 30: Microcomputer
40: first switching unit 41: second switching unit
50: Case power switch 60: Power connector
70: V _DD sensing unit
(Invention)
140: first switching unit 141: second switching unit
10d ': first switching element 10e': second switching element
19a: 5VSB control signal generation unit 19b: 3VSB control signal generation unit

Claims (8)

The first standby power supply, which is a normal standby power supply, and the second standby power supply, which is lower in voltage than the first standby power supply, are selectively applied to a corresponding portion requiring a standby power supply of the computer system even in a state where the computer system is in operation As a power saving device for a computer system using SIO,
A super IO 19 that receives power from a power supply such as the SMPS 20 via an ATX power connector 60 and recognizes when the power button 13 is activated;
A first switching unit 140 for selectively outputting the first standby power through a first switching device 10d 'turned on / off under the control of the super IO 19;
A voltage regulator 10e and a second switching device 10e 'for dropping the first standby power supplied from the power supply such as the SMPS 20 through the ATX power connector 60 to the second standby power supply And the second standby power source that is lowered by the voltage regulator 10e is always supplied to the operation power supply of the super IO 19 while the second standby power is turned on and off by the control of the super IO 19, A second switching unit 141 for selectively outputting the second standby power through the element 10e ';
A chipset 14 receiving a power on (PWBTN #) signal from the super I / O 19 and informing the super I / O 19 of the current state (mode) through signal line terminals; And
A first standby power supply control signal generator (19a) and a second standby power supply control signal generator (19b) which are located in the super IO (19) and generate control signals for the first standby power supply and the second standby power supply, respectively;
/ RTI >
When the power switch is turned on, the super IO 19 controls the first standby power supply to be supplied to the corresponding part. If the second standby power is stabilized even when the computer system is in operation, the super IO 19 The super-IO 19 controls the first standby power supply and the second standby power supply to be stopped when the second standby power supply is in the power off state, ,
The super IO 19 may be configured such that when the second standby power source is stabilized and the second standby power source is applied to the corresponding part, 1 < / RTI > standby power to the corresponding site,
The case where the first standby power source is required is a case in which an external device is charged using a charging cable through a USB port or an external connection electrical device is in use and at least one data terminal D + ) Is short-circuited. The power saving device of the computer system using the SIO. The method according to claim 1,
The 5VSB power source as the first standby power source and the 3VSB power source as the second standby power source are commonly connected and applied to the USB ports 101 and 102 through the first constant voltage diode ZD1 and the second constant voltage diode ZD2, And the power supply is controlled by the terminals 'GPIO 1' and 'GPIO 2' connected through the resistors R3 to R6 and the diodes D1 to D2. . A power saving method of a computer system using an SIO using a power saving device of a computer system using the SIO of claim 1,
(c) during operation of the computer system, determining whether the second standby power supply is stable (S17);
(d) If it is determined that the second standby power source is not in a stable state as a result of the determination in step (c), the control unit continuously checks whether the first standby power source is required. Applying the first standby power to the corresponding portion of the computer system, otherwise continuing to apply the second standby power to the corresponding portion of the computer system (S19, S20);
(e) determining whether the apparatus is in a standby mode after step (d) (S31);
(f) interrupting various operation power sources when the result of step (e) is 'yes'(S33);
(i) determining whether power is off (S39); And
(j) blocking all the standby power supplies (S41) if the determination result in the step (i) is 'YES';
And a power saving method for a computer system using the SIO. The method of claim 3,
The step (d)
(S19) of causing the second standby power source to be supplied to the corresponding portion of the computer system when the second standby power source is in a stable state, ;
(d2) a step (S21) of searching whether the first standby power source needs to be used after the step (d1)
(d3) when it is determined in the step (d2) that the first standby power source needs to be used, the step (S23) of applying the first standby power source to the corresponding site;
(d4) a step (S27) of searching whether or not the necessity of using the first standby power source has disappeared since the step (d3); And
(d5) If the necessity of using the first standby power source does not disappear in the step (d4), the control unit continues to perform the operation. If the necessity to use the first standby power source is lost, 2) applying a standby power to the corresponding part (S29);
And a power saving method of the computer system using the SIO. The method of claim 3,
Wherein the first standby power source is required when the external device is charged through the USB port in step (d). 5. The method of claim 4,
In step (d1), the step (S19) of supplying the second standby power supply to the corresponding part of the computer system is performed by setting 5VSB = 'L', 3VSB = 'H', GPIO_1 = 'L' GPIO_2 = " H "
In step (d3), the step (S23) of supplying the first standby power supply to the corresponding part of the computer system is performed by setting 5VSB = 'H', 3VSB = 'L', GPIO_1 = 'H' And controlling GPIO_2 = 'L'. The power saving method of the computer system using the SIO. 4. The method of claim 3, further comprising, between step (f) and step (i)
(g) determining whether the wakeup state is present after the step (f) (S35); And
(h) a step (S37) of applying various operation power sources to the entire system and transitioning to an operating state when the result of the determination in step (g) is 'yes';
Wherein the power saving method further includes the steps of: The method of claim 3,
Prior to step (c)
(a) determining whether the power switch is in the ON state (S11); And
(b) if it is determined that the power switch is not in the ON state as a result of the checking in step (a), the control unit continuously checks the first standby power source and the various operation power sources in step S13 );
Wherein the power saving method further includes the steps of:

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