KR101739501B1 - A power saving method of a computer system - Google Patents

Abstract

The present invention relates to a method for blocking standby power of a computer system and reducing energy, which establishes power saving measures against a long-term idle state or an S3 mode. The invention is capable of making a technology of minimizing power consumption. The method of the present invention comprises: a super IO receiving power through an ATX power connector, and recognizing the receiving of the power through a PIC (119) when a power button is activated; the PIC (119) inserted between the super IO and the power button, receiving power through an ATX power connector, recognizing and reporting the activation of the power button to the super IO when the power button is activated, and performing a USB interfacing; a first power switching unit (140) inserted between the super IO and the ATX power connector, and receiving an input of a standby power on/off signal of the PIC (119) to control the outputting of an operation voltage; a chipset (14) receiving an input of a power-on signal from the super IO, and in response, reporting a current power mode; a second power switching unit (141) controlling at least one PIC (151) by PCI_ON# signal of the PIC (119); and a ROM BIOS programming to allow the outputting of the super IO to be performed in accordance with the current mode. The PIC (119) controls an operation of a CPU to be sufficiently slowed to save energy by the operation of LTI_processor_off of an OS, and controls the operation of LTI_processor_off to be started when the long-term idle mode is determined by a signal from the chipset and the super IO. Moreover, the PIC (119) controls an original operation mode to be restored when a computer system becomes a wake-up mode later.

Description

[0001] The present invention relates to a power saving method of a computer system,

The present invention relates to a technique for reducing the power consumption of a main board of a computer and a power supply unit supplied thereto, and provides a method for power saving in a specific mode and for interrupting standby power by utilizing a power state signal of the system, And more particularly, to a method for reducing standby power and energy consumption in a computer system capable of reducing energy consumption in a long-term idle mode by lowering the CPU speed and eliminating unnecessary processes.

1, a power supply 20 such as an SMPS is connected to the SIO 12 of the main board 10 through 24 pins, one of which is connected to a standby Voltage (+ 5VSB).

When the user presses the power switch (not shown) of the PC case, the mechanically connected power button 13 is pressed, the power button 13 sends the first signal PWRBTN # to the SIO 12, The power supply 20 activates the power-on signal line PSON # with the power supply 20 and issues the second signal PWRBTN # _SB to the chipset 14. The power supply 20 is connected to the CPU 11 ) And the chipset 14 to inform it of the power supply signal, and then supply power to the main board.

Reference numeral 15 denotes a reset button of the chipset, 16 is a battery, 17 is a reset reset (17), and 18 is a LAN. In addition, AC, FWH, Super IO 19, AGP slot, PCI slot, IDE connected to the CPU and the chipset are connected.

Meanwhile, as described above, +5 V standby power is applied between the power supply 20 and the main board during non-operation, and standby power of about 1 W is required for recognizing the start button and recognizing the remote start do.

And this leads to a waste of energy, which is never high individually, and a huge amount of energy for a whole organization and even for a whole country.

In order to solve such a problem, there has been developed a socket having a switch which completely cuts off the power supply from the power socket itself to make the standby power zero (first prior art). On the other hand, Korean Patent Publication No. 2013-0043923 (Second conventional technique) for recognizing the on / off state of the power switch to completely shut off the power supply, such as the power supply device and the image forming apparatus including the power supply device.

However, in the case of the first prior art, in spite of the fact that it is practically possible for the user to sit in the outlet without turning off the power supply completely disconnected from the outlet, the second prior art is very complicated and expensive It is indispensable to mount such a device on a general PC.

Accordingly, the present inventor has proposed a computer power supply apparatus which is very simple but minimizes standby power automatically, and proposed Korean Patent No. 1328393 (name: computer power supply apparatus whose standby power is reduced) This will be described as a third prior art.

As shown in FIG. 2, the third prior art technology has a CPU 11, an SIO 12, a power button 13, a chipset 14, a reset button 15, a first battery 16, a LAN 18 ) And a super IO (19); An SMPS (20) for supplying power to the main board; A microcomputer 30 for controlling standby power supply of the SMPS; A power connector 60 for mediating signal and standby power connection between the main board and the SMPS; And a switching unit (40) for switching standby power on / off according to the control of the microcomputer. And the microcomputer 30 controls the standby power supplied to the main board by controlling the standby power (5VSB) of the power supply by the switching unit 40. [

2, the power supply apparatus of the third prior art includes an existing CPU 11, an SIO 12, a power button 13, a chipset 14, a reset button 15, A main board 10 having a power supply 16, a resetting reset 17, a LAN 18, a super IO 19, and the like, an SMPS 20 for supplying power to the main board, And a switching unit 40 for switching the standby power on / off according to the control of the microcomputer 30 and the microcomputer. The reference numeral 50 denotes a power switch of the PC case, and 60 denotes a power connector between the main board and the SMPS.

In the third prior art, the power connector 60 mediates signal and standby power connection between the main board 10 and the SMPS 20, and the SMPS 20 and the power connector are connected with 23 pins 1 is different from the conventional power supply of FIG. 1 in that a + 5V standby power line (+ 5VSB) which is one pin instead of a power connector is connected to the microcomputer 30 and the switching unit 40 instead of the power connector. The switching unit 40 may be a power switch IC or an FET circuit.

In addition, the microcomputer 30 receives the signal of either or both of the SMPS good signal (PS_ON #) and the power good signal (PWR_ON) from the SMPS 20 from the SMPS 20. The power good signal PWR_ON is also applied to the CPU 11 and the chipset 14.

Meanwhile, the microcomputer 30 also starts the standby power supply start operation by the switching signal CASE_PWR_BTN from the external case power switch 50, so that the standby power of +5 V (+ 5VSB) When the control signal 5VSB_SW of the microcomputer 30 is 'ON', the switching unit 40 applies the 5V standby signal P5V_STBY to the main board 10 through the switching unit 40, And the + 5V standby power (+ 5VSB) from the SMPS 20 is applied to the main board 10 as the 5V standby signal P5V_STBY.

From the SMPS (20) power connector to the mainboard (10) power connector, the PC's normal operating power goes to + 12V and -12V lines, + 5V standby power lines, + 3.3V power lines, and power hardening (PWR_ON) signals. However, the 5V standby power line (5VSB) goes to the switching device (40), and the standby power signal (P5V_STBY) goes from the switching device (40) back to the main board power connector.

Further, the standby power switch signal 5VSB_SW from the microcomputer 30 to the switching unit 40 and the power button signal MB_PWR_BTN to the main power button 12 go.

Conversely, the SMPS good (PS_ON #) signal goes from the mainboard 10 power connector to the SMPS 20 power connector.

First, the microcomputer 30 of the third prior art controls the standby power (5VSB) of the power supply by the switching unit 40 so as to control the power supplied to the main board When the power is off, the microcomputer senses the power cord PWR_ON and / or SMPS good signal (PS_ON #) between the connectors, and turns off the 5V standby power when the power is off. That is, in this case, since standby power is not supplied to the main board, the computer can not be turned on.

On the other hand, when the PC user presses the case power switch 50, the microcomputer 30 of the third prior art is activated by this signal, and the microcomputer controls the power good PWR_ON and / or the SMPS good PS_ON # And when the power is on, the control signal 5VSB_SW to the switching unit 40 is turned on so that the 5V standby power source 5VSB is applied to the main board. When the power button 13 of the main board is turned on, an input / output start command is issued to the SIO 12, and the SIO 12 transmits power supply completion signal PS_ON # to the SMPS 20 via the power connector 60. [ The SMPS transmits the PWR_ON signal to the main board 10 via the connector 60 and activates the main board operation power source (+12 V) when the situation is normal.

Therefore, according to the third prior art, standby power and computer start-up can be performed only by standby power of about 0.1 W corresponding to the standby power of the microcomputer without consuming standby power of 1 W corresponding to standby power of the computer activation system There are advantages.

By the way, the system is powered on. And 'off', recent PCs adopt the S1 to S5 mode, adopting various refined modes, thereby achieving the most efficient system operation with higher speed and resource utilization. For reference, the S0 mode is a computer operation mode, the S1 mode is a state in which the processor is in an idle state and is in a low power supply state or a state in which power is still supplied to the RAM, and S2 mode is a deep sleep mode However, in the S3 mode (power saving / standby mode), the power is still supplied to the RAM. In this case, the + 5V SB should not be turned off as the data is stored in the memory and the minimum power is maintained. At this time, depending on the type of DDR memory, VDD power is maintained at 1.2 ~ 1.5V, but power is supplied only to some parts such as memory and RTC. On the other hand, in S4 mode (hibernate mode), the data is stored on the hard disk and all the system power is turned off. That is, it is almost the same as the power OFF state. At this time, VDD power of memory is output as 0 V as when power is OFF. In other words, the VDD signal is 0 V in the OFF state of the system standby power and in the case of the S4 mode, and the system operation which is the standby power ON condition (Power ON state) and S3 (power saving / standby mode), the VDD signal outputs 1.2 to 1.5V.

Therefore, in the case of the system having the recent S0 to S5 mode, in the case of the third prior art, it is necessary to check all the states of the power source in order to block such standby power. 2) Checking some signals such as 'power good', and checking them. 1) When checking the current, an expensive analog-to-digital converter (ADC) and a peripheral circuit are required There is no cost-effective value to reduce standby power of 1W. 2) Also, when checking through signals such as 'power good', all power can not be checked by one signal. Therefore, Structure, which leads to a problem of low production efficiency.

On the other hand, a conventional general power-on operation will be described with reference to Figs. 3 to 7. Fig.

3, the PS_ON circuit 19a in the super IO 19 recognizes the power ON state when the power button is turned on, as shown in FIG. 3, The PS_ON # terminal of the 20-pin connector of the SIO 12 of the main board 10 is activated while communicating with the south bridge of the chipset 14 so that power is applied to the main board 10.

An example of the block diagram of the PS_ON circuit 19a of FIG. 3 is shown in detail in FIG. 4, when the switch S1 corresponding to the power button is pressed, the PS_ON circuit 19a is activated while falling to a low level, so that various voltages are applied from the SMPS to the main board (See the timing chart of Fig.

On the other hand, FIG. 6 shows another example of a conventional power-on operation concept. When power-on switching (PWR) is performed, the chipset 14 transmits the P.ON signal to the SIO 12, And the SIO 12 outputs the PON signal to the PS_ON # terminal of the connector of the main board so that the power is applied from the SMPS to the main board.

FIG. 7 is a timing chart of the signals of FIG. 6, and when the VAC is activated (AC power is applied), the PS_ON # signal is activated while falling to a low level and various voltages are applied from the SMPS to the main board, It responds with a good signal.

6, the PS_ON # signal (SMPS power on) is also turned on first by turning on the + 5V SB signal and then by connecting the south bridge and the Super I / O chipset , The PS_ON # signal is generated in the SMPS, and the connection and remodeling workability of the cable is poor, resulting in low productivity.

In order to solve the above problems, the inventor of the present invention has proposed a computer power supply apparatus which is very simple and automatically minimizes standby power even in a computer system having various operation modes, And proposed a computer power supply device that reduces standby power and has been patented as a patent No. 1623756. [ This will be described with reference to FIG. 2 and FIGS. 8 to 10. FIG.

FIG. 8 is a block diagram of a computer power supply apparatus in which standby power is reduced according to a fourth conventional technique, FIG. 9 is a detailed circuit diagram of a computer power supply apparatus in which standby power is reduced according to a fourth conventional technique, 4 is a flowchart of the operation of the microcomputer of the computer power supply apparatus in which the standby power according to the related art is reduced.

First, the invention of the fourth related art will be described with reference to the block diagram of FIG. 8. First, it is detected whether the PC power source 50 is 'on', and the ATX power cable from the SMPS 20 to the main board Activate the PS_ON # signal to the 'low' level, causing the line except the 5V SB line to go to the mainboard. At this time, the 5V SB line does not go directly to the main board but provides Vcc to the microcomputer 30 and the first switching unit 40 and activates them, thereby activating the power control signal PWR_CTRL, The first switching unit 40 sends the power output signal PWR_OUT to the 5V SB terminal of the mainboard so that the main board is operated while all the power is supplied to the main board do.

At this time, the microcomputer 30 applies the PS_ON # signal to the SMPS 20 to turn on the SMPS, and the signal and the common ground signal interlocked therewith are transmitted from the SMPS to the main board 10 via the ATX cable, The microcomputer 30 may directly supply the PS_ON # signal to the main board through the second switching unit 41 without passing through the SMPS, as shown in FIG. 8, , But it is also possible to apply it to the PS_ON # terminal of the power connector 60 through the power button 13, the PS_ON circuit 19a, and the main board.

9, the on / off state of the PC power 'on' switch 50 is provided through the switching input (SW_IN) terminal (pin 16 of the chip) of the microcomputer 30 .

Thereafter, the microcomputer 30 activates the common ground terminal (turns from 'high' to 'low') so that all of the 5V, 3.3V, 12V, power cord (PWR_OK) So that various powers are applied from the SMPS to the main board. In addition, the PS_ON # signal may be output to the SMPS 20 through the PS_ON # terminal (pin 2 of the chip) and may be connected to the corresponding terminal of the power connector 60 of the main board 10 through the ATX power cable 9, the SW_OUT signal is output to the second switching unit 41 through the fifth terminal of the microcomputer, and the switching signal is output to the super IO 19 through the power button # 13 in the main board To the corresponding terminal of the power connector 60 by activating the PS_ON circuit 19a.

The power control signal PWR_CTRL is output through the 14th pin of the microcomputer 30 to activate the first and third transistors Q1 and Q3 of the switching unit 40 to output the power output PWR_OUT signal To the 5V standby signal terminal of the connector of the main board 10. This means that the main board (computer) including the function of the memory finally operates.

Lastly, the voltage supplied to the memory (for example, DDR3) of the main board 10 is sensed by the fourth transistor Q4 of the sensing unit 70, and the result is the power GD_PWR Pin 15 of the chip).

The operation of the microcomputer of the fourth conventional art will be described once again with reference to FIG.

First, the microcomputer 30 of the present invention is operated when the system standby power is in the off state (in a state in which the AC power is not inputted). (S1). In such a case, is the PC power switch "on"? The power control signal PWR_CTRL (PWR_CTRL) is set to the power control signal PWR_CTRL (step S2). If the power control signal PWR_CTRL The switching unit 40 sends the power output signal PWR_OUT to the 5V SB terminal of the mainboard so that all the power is supplied to the main board S3). At the same time, the power button # 13 is activated and the PS_ON # signal is activated to operate the main board (S4 ').

That is, the microcomputer 30 receives a signal that the PC power switch is 'on', activates the power control signal PWR_CTRL to the first switching unit 40, and outputs the power output signal PWR_OUT) to the 5V SB terminal of the main board to supply all the power to the main board (S3) and to output the switching-out signal (SW_OUT) to another second switching unit 41 The transistor Q2 of the second switching unit 41 is turned on and the PS_ON # signal is applied to the power button 13 of the main board so that the power button 13 and the super I / The PS_ON # terminal of the connector 60 is activated through the PS_ON circuit 19a of the controller 19 to operate the main board (S4 ').

Thereafter, the voltage V _DD supplied to the memory 10a of the main board is checked (S5), and it is determined whether it is less than a predetermined voltage (for example, 0.7 V) (S6). If the voltage is abnormal ), The 5V SB power 'on' state is maintained and power supply to the main board is continued. Otherwise, the memory is considered to have stopped operating, and the power control signal PWR_CTRL is deactivated, The switching unit 40 disables the power output signal PWR_OUT and turns off the system standby power in step S7.

That is, as described above in the related art, the + 5V SB should not be turned off in the S3 mode (power saving / standby mode), while in the S4 mode (the maximum power saving mode) Turn off all power. That is, in the S4 mode and the S5 mode in which the power is OFF, 0V is output. In other words, the VDD signal is 0 V in the OFF state of the system standby power and in the case of the S4 mode, and the system operation which is the standby power ON condition (Power ON state) and S3 (power saving / standby mode), the VDD signal outputs 1.2 to 1.5V. Therefore, in S5 and S6, the voltage V _DD supplied to the memory is checked (S5), and it is determined whether or not it is less than a predetermined voltage (Vr: 0.7 V, for example) The power 'on' state is maintained, and less than (V _DD ≪ Vr), the system standby power is turned off (S7).

The fourth prior art recognizes the S3 and S4 modes by a relatively simple method of checking the voltage (V _DD ) supplied to the memory and continues to supply the 5V standby power in the S3 mode, In the S4 mode, the standby power is cut off to save power in the dash mode. However, there is an advantage that it can be performed without additional cable construction.

However, in S3 (standby / power saving mode), there is no need to supply a standby power of 5 V, and only a standby power of about 3 V is sufficient. However, the fourth prior art does not provide such a standby power supply.

In addition, in the above-mentioned conventional techniques, since the mode recognition such as S3 and S4 is checked with a voltage in a secondary device such as a memory, a separate device for checking the mode is necessary. In addition, A wiring to the microcomputer and a separate cable are required. In addition, although the possibility is very low, there is a problem that the system can not accurately sense the inconsistency between the secondary device such as the current mode and the memory due to the error of the system.

Korean Patent Publication No. 2013-0043923 (Patent Application No. 2011-0108115) Korea Patent No. 1328393 (name: computer power supply device for saving standby power) Korean Patent No. 1623756 (Title: Standby power cutoff method of standby power cutoff device using system memory power)

In a computer system having various operation modes (for example, S0 to S5 modes), the present invention is slightly advanced in a technology for blocking standby power currently being actively developed, The present invention aims at implementing a technique capable of minimizing power consumption by providing standby power cut-off and energy saving method that have established countermeasures.

According to an aspect of the present invention, there is provided a method of interrupting standby power and saving energy in a computer system, the method comprising: receiving power from a power supply such as the SMPS (20) through an ATX power connector (60) A super IO 19 recognizing it via the PIC 119 when the control unit 13 is activated; Is inserted between the super IO 19 and the power button 13 and is supplied with power from a power supply such as the SMPS 20 through the ATX power connector 60 and is recognized when the power button 13 is activated A PIC (119) for notifying the super IO (19) and performing USB interfacing; A first power switching unit inserted between the super IO 19 and the ATX power connector 60 for receiving standby power ON / OFF signals of the PIC 119 and controlling whether an operation voltage 5VSB_ATX is output 140); A chipset 14 receiving a power on (PWRON #) signal from the super IO 19 and informing the super IO 19 of the current power state (mode) through 'SLP' signal line terminals; A second power switching unit 141 for controlling at least one PIC 151 by a PCI_ON # signal of the PIC 119; And a ROM BIOS 10b for programming to output the super IO 19 according to the current mode; The PIC 119 determines that the LTI of the OS 10c is in a long-term idle mode when it is determined by the signal from the chipset 14 and the super I / (Long-Term Idle_Processor_off) operation saves energy while allowing the operation of the CPU 11 to be relatively slower than that in the operation mode, causing the LTI_processor off operation to be started, (A) the PIC 119 and the super I / O 19 are connected to the standby power cut-off and energy saving device of the computer system using the standby power cut-off and energy saving device of the computer system, Checking whether a power-on (PWRON #) signal is generated (S11); (b) If the PWRON # signal has not been generated as a result of the determination in step (a), the 5VSB ON # signal is set to 'L' if a PWRON # And supplies the standby power to the first power switch 140 and the super-ON 19 via the ATX power connector 60 and the other devices to the other devices by setting the PONSWH # signal to 'L' and the PS_ON # Supplying operating power (S12); (c) during operation of the computer system, determining whether the computer is in a long-term idle state (S13); (d) If it is not in the long-term idle state as a result of the judgment in the step (c), it continues to check. If it is YES, CPU clock is dropped and a PCI ON # H 'and deactivating the add-on card (S14); (e) If the result of the determination in step (c) is 'YES', the PIC 119 outputs a 'LTI_Processor_off' signal to the OS to perform a 'RUN Energy saver program' The current state ('a' State) and stopping processes that are not essential processes (S51 to S56); (f) determining whether the computer system is woken up (S16); (g) If the result of step (f) is 'YES', the 'LTI_Processor_on' operation is executed and the stored current state 'a' (S17), activating the add-on card with the 'PCI ON #' signal set to 'L' (S18), returning the CPU clock to its original state as in the normal operation state; (h) checking the power off (PWR_OFF) signal (S19); And (i) if it is determined in step (h) that it is not in the power off state, the process returns to step (c) and continues, and if the power off button is pressed, the 5VSB ON # Turning off the standby power supply (S20); And a control unit.

Preferably, when the PIC 119 is determined to be in a standby mode during a long-term idle mode by a signal from the chipset 14 and the super I / O 19 , 'RUN Suspend to RAM' is performed. After storing the current state in the RAM, the CPU enters the standby mode (S3 mode) in which only the RAM memory is supplied with the minimum power and the other resources are shut off, And to return to a normal operation state when it is determined that the wake-up state is established.

According to another aspect of the present invention, there is provided a method of interrupting standby power and saving energy in a computer system, comprising the steps of: (c) determining whether the computer system is in a long-term idle state during operation of the computer system; (d) If it is not in the long-term idle state as a result of the judgment in the step (c), it continues to check. If it is YES, CPU clock is dropped to a sufficient degree, Quot; H " and deactivating the add-on card (S14); (e) If the result of the determination in step (c) is 'YES', the PIC 119 outputs a 'LTI_Processor_off' signal to the OS to perform a 'RUN Energy saver program' The current state ('a' State) and stopping processes that are not essential processes (S51 to S56); (f) determining whether the computer system is woken up (S16); (g) If the result of step (f) is 'YES', the 'LTI_Processor_on' operation is executed and the stored current state 'a' (S17), activating the add-on card with the 'PCI ON #' signal set to 'L' (S18), returning the CPU clock to its original state as in the normal operation state; (j) determining whether the wakeup state is not the standby mode (S3 mode) (S21); (k) If it is not the standby mode (S3 mode) as a result of the determination in the step (j), the process proceeds to the step (f) and continues to perform. If the result is 'yes', the 'RUN Suspend to RAM' (S22) of entering a standby mode (S3 mode) in which a minimum current is supplied only to the RAM memory and a power supply is cut off to another resource after storing the current state in the RAM; And (l) after step (k), determining whether the apparatus is in a standby mode wakeup state (S23); And if the wakeup state is not satisfied, the process proceeds to the step (g) to execute the 'LTI_Processor_on' operation, and if the CPU The clock is returned to its original state as in the normal operation state and the 'PCI ON #' signal is set to 'L' to activate the add-on card.

According to another aspect of the present invention, there is provided a method for shutting down standby power and saving energy in a computer system, comprising the steps of: (c) determining whether the computer system is in a long-term idle state during operation of the computer system; (d) If it is not in the long-term idle state as a result of the judgment in the step (c), it continues to check. If it is YES, CPU clock is dropped to a sufficient degree, Quot; H " and deactivating the add-on card (S14); (e) If the result of the determination in step (c) is 'YES', the PIC 119 outputs a 'LTI_Processor_off' signal to the OS to perform a 'RUN Energy saver program' The current state ('a' State) and stopping processes that are not essential processes (S51 to S56); (f) determining whether the computer system is woken up (S16); And (g) if it is determined in step (f) that 'YES', the 'LTI_Processor_on' operation is executed and the stored current state 'a' (S17), activating the add-on card with the 'PCI ON #' signal set to 'L' (S18), returning the CPU clock to its original state as in the normal operation state; Wherein the step (e) comprises: (e1) the OS 10c calls a list of 'LTI_Processor_off'(S52); (e2) the OS 10c confirms the process being executed in the processor manager and stores the current state ('a' state) information in preparation for the return (S53); (e3) determining (S54) whether the 'Processor ID' of the 'LTI_Processor_off' target process on the 'LTI_Processor_off' list is the same as the process being executed; (e4) if the result of the determination in the step (e3) is not the same, the process is continuously executed for the next process, and the same process as the process on the list is terminated (process turning off) (S55); And (e5) determining whether the steps (e3) and (e4) have been performed on all processes on the 'LTI_Processor_off' list (S56); If it is determined in step (e5) that all processes on the 'LTI_Processor_off' list have not been performed, the process proceeds to step (e3) to continue execution. If yes, ). ≪ / RTI >

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According to the present invention, there is provided a standby power interruption and energy saving method in which a power saving measure for a long-term idle state or an S3 mode is established in a computer system having various operation modes So that power consumption can be minimized.

Other objects and advantages of the present invention will become apparent from the detailed description of the embodiments with reference to the attached drawings.

1 is a conceptual diagram of a conventional computer power supply;
2 is a block diagram of a computer power supply in which standby power is reduced according to the third prior art.
3 is a view for explaining a concept of a conventional general power-on operation;
4 is a block diagram of the PS_ON circuit 19a of Fig.
5 is a timing chart of the signals of FIG. 3;
FIG. 6 is another example of a concept of a conventional general power-on operation; FIG.
FIG. 7 is a timing chart of the signals of FIG. 6; FIG.
FIG. 8 is a block diagram of a computer power supply in which standby power is reduced according to a fourth prior art; FIG.
FIG. 9 is a detailed circuit diagram of a computer power supply apparatus in which standby power is reduced according to a fourth prior art; FIG.
FIG. 10 is a flowchart illustrating an operation of a microcomputer of a computer power supply apparatus according to a fourth prior art in which standby power is reduced. FIG.
11 is a system configuration diagram of a prior invention related to the present invention;
FIG. 12 is a system configuration diagram showing only the components directly related to the present invention among the inventive system related to the present invention; FIG.
FIG. 13 is a flowchart of the operation of the super IO of a computer system in which the power consumption is reduced according to the present invention related to the present invention. FIG.
FIG. 14 is a system configuration diagram showing only components directly related to the present invention among the systems according to the present invention; FIG.
15 is a flowchart illustrating an operation of the standby power cutoff and energy saving method according to the present invention.
16 is a subroutine flowchart of an LTI processor off operation among the standby power cutoff and energy saving methods according to the present invention.
FIG. 17 is a graph showing the test conditions for the comparison of the power consumption and the standby power cut-off and energy saving method according to the present invention and the conventional power consumption method.
FIG. 18 is a table of power consumption vs. standby power cutoff and energy saving method according to the present invention, and FIG.

Hereinafter, preferred embodiments according to the present invention will be described in detail with reference to the accompanying drawings.

It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the invention, You will know.

For reference, Korean Patent Application No. 2016-0087595 (a power saving apparatus and method of a computer system using a GPIO port, and a computer system utilizing the same) (hereinafter referred to as the " ), And the contents of the specification of the above patent application are also taken into consideration in the specification of the present application. However, the technology of the above-mentioned prior invention is not a known technology disclosed before the filing of the present application.

(Prior invention relating to the present invention)

First, an embodiment of a method and an apparatus for measuring the operating state of a computer system of the present invention will be described with reference to Figs. 11 to 13. Fig.

FIG. 11 is a system configuration diagram of a prior invention according to the present invention related to the present invention, FIG. 12 is a system configuration diagram showing only components directly related to the present invention among systems of the prior invention related to the present invention, Fig. 2 is a flowchart illustrating a super IO operation of a computer system in which power of the invention is reduced.

11 and 12, the power saving device of the computer system of the first aspect of the present invention includes a first switching unit 40 and a second switching unit 40 between the super IO 19 and the ATX power connector 60 in the main board, And a second switching unit 41 is added between the chip set (PCH) 19 and the chipset (PCH) 14.

As shown in FIG. 2, the power supply in the general computer system is performed through a power supply such as the SMPS 20 through the ATX power connector 60 to the main board 10, for example, through a 5VSB power line The power saving is performed through a device such as the microcomputer 30 that performs appropriate control.

11, the super-IO 19 receives power from a power supply such as the SMPS 20 through the ATX power connector 60. More specifically, the power button 13 The power state detector 19b in the super IO 19 recognizes it and outputs a power on signal PWRON # to the chipset 14. In response, the chipset 14 receives the power on signal from the super IO 19, The power state detector 19b in the super IO 19 responds to the current power state (mode) via the SLP_4 and SLP_3 signal line terminals via the first switching unit 40 and the ATX power connector 60 to start the super IO 19 operation.

On the other hand, in the case of the present invention, when the power state detector 19b in the super IO 19 recognizes activation of the power button 13 and outputs a power-on (PWRON #) signal to the chipset 14, (Mode) through the 'SLP_4' and the 'SLP_3' signal line terminals from the chipset 14 is the same as that of the prior art. However, according to the present invention, a different operation is performed through the GPIO port . For reference, generally, the Super IO chip has about 50 general purpose input output (GPIO) ports, which can be programmed to a specific purpose port by the BIOS, 'GPIO A' port and 'GPIO B' port.

The power state detector 19b of the super IO 19 determines whether the current power state is the S4 mode (the maximum power saving mode) through the SLP_4 signal line terminal from the chipset 14, L 'signal to the control terminal of the third transistor Q3 of the first switching unit 40 through the port of the ATX power connector 60 and at the same time the super IO 19 activates the PSON # . The signal 5VSB_ATX of the output terminal OUT of the first switching unit 40 is turned on by the switching operation of the third transistor Q3 and the first transistor Q1 of the first switching unit 40, (5V) voltage is applied to the PMOS 10d and is therefore applied to the PMOS 10d and the LDO 10e, which are a kind of voltage regulators. The 5VSB, which is the output of the PMOS 10d, becomes the first operating power of the system, 2 switching unit 41 and the output 3VSB of the LDO 10e is applied to the operation power source of the super IO 19 as the second operation power. Therefore, by using the super IO chip 19 and the 'GPIO B' port, it is possible to save power when the computer system is started, without using any additional device as compared with the prior art.

Subsequently, the super IO 19 determines whether the current power state is proceeding to the S3 mode (power saving / standby mode). If the current power state is S3 through the 'SLP_3' signal line terminal from the chipset 14, L "signal to the input side of the second switching unit 41 through the 'GPIO A' port of the super IO 19 when the mode is determined to be a power saving / standby mode, The switching unit 41 applies the output of the second switching unit 41 to the power supply terminal (3VSB / 5VSB terminal) of the super IO and the chipset 14 and the 'PWRBTN #' terminal of the chipset with the low voltage (3VSB) do.

At this time, when the 'H' signal is input to the input side by the peripheral devices such as resistances R3 to R5 and the capacitors C2 to C3 and the voltage regulator 41a, the second switching unit 41 In this case (power saving / standby mode), if only the minimum power supply is maintained and high voltage of 5V is not needed, it is controlled by low voltage (3VSB) so that the high voltage (5VSB) The total power consumption can be saved.

Subsequently, the super I / O 19 determines whether the current power state proceeds to the S3 mode (power saving / standby mode) and then proceeds to the operation mode S2 or less (i.e., S0 (computer operation mode) (Hereinafter, referred to as an 'S2 mode or an operation mode'), the current power state is switched to the mode S2 or less through the 'SLP_3' signal line terminal from the chipset 14 H 'signal to the input side of the second switching unit 41 through the' GPIO A 'port of the super I / O 19 when it is determined that the first switching unit (operation mode) 41 is applied to the power supply terminal (3VSB / 5VSB terminal) of the super IO and chipset 14 and the 'PWRBTN #' terminal of the chipset with the output of the second switching unit 41 being a high voltage (5VSB).

On the other hand, if the current power state (mode) is determined through the SLP_4 and SLP_3 signal line terminals from the chipset 14 and the SLP_4 is 'L', the computer system is already in the hibernation mode H 'at the input side of the second switching unit 41 through the' GPIO A 'port. If the' SLP_3 'signal line is' H', the system is woken up. Signal to the power supply terminal (3VSB / 5VSB terminal) of the super IO and chipset 14 and the 'PWRBTN #' terminal of the chipset by setting the output of the second switching unit 41 to a high voltage (5VSB) do.

Of course, when the current power state (mode) is determined through the SLP_4 and SLP_3 signal line terminals from the chipset 14 and the SLP_4 is L and the SLP_3 is L, H 'signal to the input side of the second switching unit 41 through the' GPIO A 'port and outputs the output of the second switching unit 41 to the high voltage (5VSB) .

Finally, since the computer system is operating as described above, the 'H' signal is continuously output to the input side of the second switching unit 41 through the 'GPIO A' port to output the output of the second switching unit 41 to the high voltage The power state detector 19b of the super IO 19 controls the third transistor Q3 of the first switching unit 40 via the GPIO B port, The output terminal of the first switching unit 40 is turned on by the switching operation of the third transistor Q3 and the first transistor Q1 of the first switching unit 40, The zero voltage (0V) is applied to the signal 5VSB_ATX of the output terminal OUT and the output of the PMOS 10d and the LDO 10e also becomes 0 V. Eventually, the operation of the super IO 19 is turned off, By using the super IO chip 19 and the ' GPIO B ' port, It is possible to prevent the power consumption at an early stage in the end of the system, thereby enabling the overall power saving.

Now, a power saving method of a computer system using the GPIO port of the above-mentioned invention will be described with reference to Figs. 11 to 13, particularly with reference mainly to Fig.

13, when the computer system is started, the power state detector 19b in the super IO 19 checks whether a power on (PWRON #) signal is generated (S11), and a power on (PWRON # SLP_4 "and" SLP_3 "signal lines from the chipset 14 in response to the power on (PWRON #) signal, if the power on (PWRON #) signal has not been generated (for example, if the power button has not been turned on) The current power state (mode) is checked. First, it is checked whether the 'SLP_4' signal line from the chipset 14 is 'H' (S12).

The power state detector 19b of the super I / O 19 determines that the GPIO B port is connected to the GPIO B port because the current power state is determined to be the S4 mode (the maximum power saving mode) when the SLP_4 signal line is' A high voltage is applied to the signal 5VSB_ATX of the output terminal OUT of the first switching unit 40 by outputting an L signal to the first switching unit 40 through the first switching unit 40, At the same time, the super IO 19 activates the PSON # signal (S15) and outputs it to the ATX power connector 60 so that the super IO 19 is activated.

The super IO 19 checks whether the 'SLP_3' signal line from the chipset 14 is 'H' (S17) and determines whether the current power state goes to S3 mode (power save / standby mode) (SLP_3 = 'H') is determined to be the S3 mode (power save / standby mode) through the 'SLP_3' signal line terminal from the chipset 14, L 'signal to the input side of the second switching unit 41 through the' GPIO A 'port in step S18. The second switching unit 41 then outputs the output of the second switching unit 41 (3VSB / 5VSB) of the chipset 14 and the 'PWRBTN #' terminal of the chipset as the low voltage (3VSB).

Thereafter, the super IO 19 checks whether the SLP_3 signal line is 'L' (S19) after the current power supply state proceeds to the S3 mode (power saving / standby mode) GPIO A 'of the super IO 19 is determined to be in a mode (operation mode) under the current power state through the SLP_3 signal line terminal from the chipset 14, The second switching unit 41 outputs the output of the second switching unit 41 as a high voltage (5VSB) to the input side of the second switching unit 41 through the port To the power supply terminal (3VSB / 5VSB terminal) of the super IO and chipset 14 and the 'PWRBTN #' terminal of the chipset. This results in a successful boot.

On the other hand, if it is determined in step S17 that the 'SLP_3' signal line is not 'H', it is checked whether the PWR_OFF state is satisfied (S32) And if it is not (power off), it is determined to be a boot error (S33).

If the SLP_3 is not 'L' in step S19, it is determined that the booting process is out of the normal booting process. Therefore, the process proceeds to step S32. In step S32, If it is not power-off, the process proceeds to step S19 and repeats. If the power is off, it is determined as a boot error (S33).

On the other hand, if it is determined in step S12 that 'SLP_4' is 'L', it indicates that the boot has already been performed. In this case as well, it is determined whether the 'SLP_3' signal line is 'H' (Step S14). If the SLP_3 is 'L', it means that the mode is the mode S2 (operation mode). Accordingly, the process proceeds to step S20, and the 'GPIO A' H "signal to the input side of the second switching unit 41 through the port of the second switching unit 41 and the second switching unit 41 outputs the output of the second switching unit 41 as the high voltage (5VSB) To the power supply terminal (3VSB / 5VSB terminal) of the chipset 14 and the 'PWRBTN #' terminal of the chipset.

However, if it is determined in step S14 that 'SLP_3' = 'H', it indicates that the system is in the S3 mode (standby / full-duplex mode) while operating after booting. , The process directly proceeds to step S20 and outputs 'H' signal to the input side of the second switching unit 41 through the 'GPIO A' port of the super IO 19. That is, in this case, since the S3 mode is the same as the step S18, the step S18 shows a state in which the S3 mode is changed from the S2 mode to the S3 mode, The process immediately goes to the step S20 and shifts to the operation mode.

Finally, when the booting has been successfully performed and the process proceeds to the sub-S2 mode (operation mode) (S11, S12, S1, S15, S17 to S20) (S21). If it is determined in step S21 that power-off is to be performed, GPIO = 'H', and output through the first switching unit 40 The system is terminated (S23). On the contrary, if the voltage is not turned off in the step S21, the process returns to the step S12 (S41) SLP_4 'and' SLP_3 'signal lines from the chipset 14 to determine whether to proceed with the next power state (mode).

As a result, according to the power saving method of the computer system using the GPIO port according to the above-mentioned invention, the GPIO port of the super IO chip is programmed through the BIOS without any additional hardware or cable installation work, It is possible to easily detect the current operating state of the system, and it is possible to save power at booting by only the first switching unit 40. [

In addition, it is possible to save power by applying 3VSB operating voltage instead of 5VSB even in S3 mode during boot, and switch to 3VSB operating voltage immediately after S4 mode in operation, There is an advantage that the second switching unit 41 can be operated without any additional sensing device or cable operation.

(Embodiment of the present invention)

Hereinafter, an embodiment of a method and an apparatus for measuring the operating state of the computer system of the present invention will be described with reference to FIG. 14 to FIG.

FIG. 14 is a system configuration diagram showing only components directly related to the present invention among the systems according to the present invention, FIG. 15 is a flowchart illustrating an operation of the standby power cutoff and energy saving method according to the present invention, Among the standby power cutoff and energy saving methods, a subroutine flowchart of the LTI processor off operation is shown.

14, the computer system according to the present invention may also include a first power switching unit 70 between the super IO 19 and the ATX power connector 60 in the main board, as shown in FIG. 14, And a second power switching unit 141 is additionally provided between the super IO 19 and the PCI slot (PCI & PCIe) 151. In addition, in the present invention, it is activated by the 5VSB voltage (5VSB_PWR) from the ATX power connector 60 and receives the ON / OFF signal of the power button 13 and the power ON switch PONSWH O # signal to the first power switching unit 140 and the PCI_ON # signal to the second power switching unit 141 in response to the PS_ON # signal of the super I / (119). The first power switching unit 140 and the second power switching unit 141 may be configured in a manner similar to the first switching unit 40 and the second switching unit 41 in the above- have.

In addition, the PIC 119 exchanges a CPU_Clock signal and a SYS_OFF signal with the OS 10c instead of the super I / O 19 (in this case, the OS 10c provides a CPU_Clock_drop signal to the CPU 11) Receives the RPM information from the CPU_PAN switching unit 129, and performs USB interfacing.

The CPU_PAN switching unit 129 receives the PWM signal and the fan control signal from the super I / O 19 to control the fan, and provides RPM status information of the current fan to the PIC 119.

The first power switching unit 140 is activated by the 5VSB voltage 5VSB_PWR from the ATX power connector 60 and the super I / O 19, the ROM BIOS 10d and the PCH 14 5VSB_ATX is applied.

As shown in FIG. 2, the power supply in the general computer system is performed through a power supply such as the SMPS 20 through the ATX power connector 60 to the main board 10, for example, through a 5VSB power line The power saving is performed through a device such as the microcomputer 30 that performs appropriate control.

In the present invention, power is supplied from a power supply such as the SMPS 20 through the ATX power connector 60 in the super IO 19, and more specifically, referring to FIG. 14, The super IO 19 recognizes it via the PIC 119 and outputs a power on signal PWRON # to the chipset 14 in response to which the chipset 14 is connected to the super IO 19 SLP 'signal line terminals such as' SLP_4' and 'SLP_3' signal line terminals, the super IO 19 notifies the first power switching unit 140 of the current power state (mode) The operation power supply 5VSB_PWR is supplied from the ATX power connector 60 to start the super IO 19 operation.

On the other hand, in the case of the present invention, when the super IO 19 and the PIC 119 connected thereto recognize activation of the power button 13 and output a power-on (PWRON #) signal to the chipset 14, The present invention is similar to the conventional technology in that the current power state (mode) is grasped through the 'SLP' signal line terminals from the chipset 14, but the present invention is applicable to a long-term idle mode, Through the 'CPU_Clock' port of the PIC 119 in accordance with the instruction. For reference, when the system is in idle mode in which no operation is performed in the operation mode (S0 mode) and the idle mode is longer than idle mode (for example, 2 minutes or more), the PC is turned on Since no operation is performed, it can be confirmed through monitor pixel detection, screen saver, process operation status, and so on. Thereafter, when the idle state continues for a further period of time (for example, 20 minutes), the current state is stored in the RAM and the operation shifts to the standby mode (S3 mode) in which all operations except for the RAM memory are terminated.

That is, when it is determined that the current power state is the long-term idle mode through the 'SLP' signal line terminal and other operation state detection from the chipset 14, the PIC 119 transmits the ' And the PIC 119 activates the PCI_ON # signal and outputs the signal to the second power switching unit 141. The second power switching unit 141 outputs the ' As a result, the operation of the CPU 11 is sufficiently (for example, 50% or more) slowed down by the LTI_process off operation of the OS 10c to save energy, and the LTI_Processor_off operation is started (See Fig. 15), whereby operation not directly required for the minimum operation of the system such as LAN, VGA, and sound is stopped, and the Add_on card is also turned off. Thus, it is possible to save energy in the long-term idle mode of the computer system without using a separate additional device as compared to the prior art. For reference, 'LTI_Processor_off' stores the current state in the RAM 10a so that it can be recovered at the time of wake-up in the short-term idle mode, and the 'LTI_Processor_off' The target process is terminated. 'LTI_Processor_off' Examples of target processes include network-related processes, VGA-related processes, and host processes.

On the other hand, continue to determine whether the wake-up state, if a wake-up state to the original pre-stored operating the reduction ( 'LTI_Processor_on' process, but the operation mode process, 'a' The system returns to the normal operation mode by turning on the various add-on cards by returning the CPU clock to the original state and returning the PCI_ON # to the L state), the idle state without being woken up (Power saving / standby mode) through the 'SLP' signal line terminal from the chipset 14, it is determined whether the current power state is the S3 mode ), It stores the current state in the RAM, enters the standby mode in which the minimum power is supplied only to the RAM memory and the power is shut off to the other resources.

Now, the standby power cutoff and energy saving method of the computer system of the present invention will be described with reference to Figs. 14 to 17, particularly Figs. 15 and 16. Fig.

15, when the computer system is started, the PIC 119 and the super IO 19 check whether a PWRON # signal is generated (S11), and if a power on (PWRON #) signal is not generated If the power ON (PWRON #) signal has been generated, the 5VSB ON # signal is set to 'L' to supply the standby power, and the PONSWH # Signal to 'L' and the PS_ON # signal to 'L' to supply operating power to the first power switch 140, the super-ON 19 and other devices through the ATX power connector 60 (S12) .

Now, it is determined whether a long-term idle state is present (S13) through the 'SLP' signal line terminals from the chipset 14 and the pixel sensing of other monitors, a screen saver, a process operation state, CPU clock 'is outputted to the OS 10c as' L', and the CPU clock is dropped to a sufficient degree (preferably, 50% or more) by the OS 10c and the 'PCI ON #' signal is set to 'H' to turn off the add-on card, thereby minimizing energy consumption (S14).

In addition, the OS 10c outputs a signal 'LTI_Processor_off', and the OS 10c performs a 'RUN Energy saver program' in response to the 'LTI_Processor_off' signal as shown in FIG. 16 (S51) .

First, the OS 10c calls a list of 'LTI_Processor_off' (S52). Examples of these LTI_Processor_off target processes include a network related process, a VGA related process, a HOST process, and the like.

The OS 10c stores the current status information 'a' in step S53 in order to check and restore the process running in the processor manager (step S53). Then, the OS 10c sets the ' Processor ID 'of the LTI_Processor_off' target process is equal to each other (S54). If they are not the same, the process is continuously executed for the next process, and the same process as the process on the list is terminated (process off) (S55) .

Then, it is determined whether all the processes on the 'LTI_Processor_off' list have been performed on all the processes on the 'LTI_Processor_off' list (S56). If not, the processes on S54 and S55 are performed on all the processes on the 'LTI_Processor_off' list , And if it is performed for all the processes on the 'LTI_Processor_off' list, the process returns to step S16 of the main flow chart of FIG.

15, it is determined whether or not wake-up from the long-distance idle mode (S16), which is performed by detecting the pixel of the 'SLP' signal line terminals and other monitors, Screen saver, process operation status, and so on.

Thus, when the system is woken up from the long-term idle mode (for example, when the user moves the mouse or presses the keyboard button), the 'LTI_Processor_on' operation is executed, 'a' (S17), the CPU clock is returned to its original state as in the normal operation state, and the 'PCI ON #' signal is set to 'L' to activate the add-on card (S18).

Finally, the power-off (PWR_OFF) signal is checked (S19). If it is not in the power off state, the process returns to step S13 and continues. If the power off button is pressed, the 5VSB ON # The power is turned off (S20), and the entire system is terminated (S30).

If it is determined in step S16 that it is not the wakeup state, it is determined whether the mode is the S3 mode (S21). If it is not the S3 mode, the mode is still the long-term idle state. If the state is shifted to the S3 mode, 'RUN Suspend to RAM' is executed. That is, after storing the current state in the RAM, the standby state in which the minimum power is supplied only to the RAM memory, Mode (S3 mode) (S22).

After that, is it in standby mode again? (Step S23). If it is not the wakeup state, it continues to perform the wakeup. If wakeup occurs, the process proceeds to step S17 to execute the 'LTI_Processor_on' operation 'a' (S17 to S18), and activates the add-on card by setting the 'PCI ON #' signal to 'L' to return the CPU clock to its original state as in the normal operation state.

According to the computer system of the present invention, the power off, standby mode (S3), and long-term idle mode are checked during operation of the computer system, Energy savings can be realized. The long-term idle mode detects the pixel change of the monitor, detects the current system status by detecting keyboard or mouse input, drops the CPU speed by more than 50% in the long-term idle mode, and eliminates unnecessary processes Can be easily implemented. Of course, in the standby mode (S3), power to all resources except the RAM is shut off, and when the power is turned off, the standby power is completely cut off even to the RAM.

FIG. 17 shows test conditions (measurement conditions and hardware specifications) for the standby power cut-off and energy saving method according to the present invention and for the power consumption in the case of the prior art, and FIG. And the power consumption in the case of the prior art. The test method is the result of testing by the "Standby Power Reduction Program Operation Regulations" (No. 2014-36), and the rated power was AC 220V, 50 ~ 60Hz, 300W.

As shown in FIG. 18, 38.6 W is consumed at the time of 'LTI_Processor_on', but it is consumed only 36.9 W at the time of 'LTI_Processor_off' under the same condition, so that power of 1.7 W is saved. For example, in the above experiment, the processes turned off in the long-term idle mode include 'clint server runtime process', 'SMPHost', 'DCOM Server process launcher', 'service host: Unistack Server Group' Svc ',' Service Host: WIA ',' Service Host: Network Service ', and' Service Host: .Local Service '.

While the present invention has been described in connection with what is presently considered to be practical exemplary embodiments, it is to be understood that the invention is not limited to the disclosed embodiments, but, on the contrary, Of course.

(Prior art and prior invention)
10: main board 10a: memory
10b: ROM BIOS 10c: OS
10d: PMOS (P-type MOS) 10e: LDO (Low Dropout Voltage Regulator)
11: CPU 12: SIO (System IO)
13: Power button 14: Chipset
15: reset button 16: first battery
17: RESET RESET 18: LAN
19: Super IO (Super IO) 19a: PS_ON circuit
19c: Power state detector
20: Power supply (SMPS) 30: Microcomputer
40: first switching unit 41: second switching unit
50: Case power switch 60: Power connector
70: V _DD sensing unit
(Invention)
140: first power switching unit 141: second power switching unit
119: PIC 129: CPU_FAN control unit

Claims (6)

A super IO 19 that receives power from a power supply such as the SMPS 20 via an ATX power connector 60 and recognizes the power button 13 through the PIC 119 when the power button 13 is activated; Is inserted between the super IO 19 and the power button 13 and is supplied with power from a power supply such as the SMPS 20 through the ATX power connector 60 and is recognized when the power button 13 is activated A PIC (119) for notifying the super IO (19) and performing USB interfacing; A first power switching unit inserted between the super IO 19 and the ATX power connector 60 for receiving standby power ON / OFF signals of the PIC 119 and controlling whether an operation voltage 5VSB_ATX is output 140); A chipset 14 receiving a power on (PWRON #) signal from the super IO 19 and informing the super IO 19 of the current power state (mode) through 'SLP' signal line terminals; A second power switching unit 141 for controlling at least one PIC 151 by a PCI_ON # signal of the PIC 119; And a ROM BIOS 10b for programming to output the super IO 19 according to the current mode; The PIC 119 determines that the LTI of the OS 10c is in a long-term idle mode when it is determined by the signal from the chipset 14 and the super I / (Long-Term Idle_Processor_off) operation saves energy while allowing the operation of the CPU 11 to be relatively slower than that in the operation mode, causing the LTI_processor off operation to be started, Up state of the computer system using the standby power cut-off and energy saving device,
(a) checking whether the PIC 119 and the super IO 19 generate a PWRON # signal (S11);
(b) If the PWRON # signal has not been generated as a result of the determination in step (a), the 5VSB ON # signal is set to 'L' if a PWRON # And supplies the standby power to the first power switch 140 and the super-ON 19 via the ATX power connector 60 and the other devices to the other devices by setting the PONSWH # signal to 'L' and the PS_ON # Supplying operating power (S12);
(c) during operation of the computer system, determining whether the computer is in a long-term idle state (S13);
(d) If it is not in the long-term idle state as a result of the judgment in the step (c), it continues to check. If it is YES, CPU clock is dropped and a PCI ON # H 'and deactivating the add-on card (S14);
(e) If the result of the determination in step (c) is 'YES', the PIC 119 outputs a 'LTI_Processor_off' signal to the OS to perform a 'RUN Energy saver program' The current state ('a' State) and stopping processes that are not essential processes (S51 to S56);
(f) determining whether the computer system is woken up (S16);
(g) If the result of step (f) is 'YES', the 'LTI_Processor_on' operation is executed and the stored current state 'a' (S17), activating the add-on card with the 'PCI ON #' signal set to 'L' (S18), returning the CPU clock to its original state as in the normal operation state;
(h) checking the power off (PWR_OFF) signal (S19); And
(i) If it is determined in step (h) that the power off state is not satisfied, the process returns to step (c) and continues. If the power off button is pressed, the 5VSB ON # Turning off the power supply (S20); And a standby power cut-off and energy saving method of the computer system. The method according to claim 1,
When it is determined by the signal from the chipset 14 and the super I / O 19 that the PIC 119 is transitioned to the standby mode during the long-term idle mode, the PIC 119 transmits' RUN Suspend (S3 mode) in which the minimum power is supplied only to the RAM memory and the other resources are shut off, and the wake-up operation is performed during the standby mode after the current state is stored in the RAM, And to return to a normal operation state when it is determined that the standby state is in the standby state. A super IO 19 that receives power from a power supply such as the SMPS 20 via an ATX power connector 60 and recognizes the power button 13 through the PIC 119 when the power button 13 is activated; Is inserted between the super IO 19 and the power button 13 and is supplied with power from a power supply such as the SMPS 20 through the ATX power connector 60 and is recognized when the power button 13 is activated A PIC (119) for notifying the super IO (19) and performing USB interfacing; A first power switching unit inserted between the super IO 19 and the ATX power connector 60 for receiving standby power ON / OFF signals of the PIC 119 and controlling whether an operation voltage 5VSB_ATX is output 140); A chipset 14 receiving a power on (PWRON #) signal from the super IO 19 and informing the super IO 19 of the current power state (mode) through 'SLP' signal line terminals; A second power switching unit 141 for controlling at least one PIC 151 by a PCI_ON # signal of the PIC 119; And a ROM BIOS 10b for programming to output the super IO 19 according to the current mode; The PIC 119 determines that the LTI of the OS 10c is in a long-term idle mode when it is determined by the signal from the chipset 14 and the super I / (Long-Term Idle_Processor_off) operation saves energy while allowing the operation of the CPU 11 to be relatively slower than that in the operation mode, causing the LTI_processor off operation to be started, Up state of the computer system using the standby power cut-off and energy saving device,
(c) during operation of the computer system, determining whether the computer is in a long-term idle state (S13);
(d) If it is not in the long-term idle state as a result of the judgment in the step (c), it continues to check. If it is YES, CPU clock is dropped and a PCI ON # H 'and deactivating the add-on card (S14);
(e) If the result of the determination in step (c) is 'YES', the PIC 119 outputs a 'LTI_Processor_off' signal to the OS to perform a 'RUN Energy saver program' The current state ('a' State) and stopping processes that are not essential processes (S51 to S56);
(f) determining whether the computer system is woken up (S16); And
(g) If the result of step (f) is 'YES', the 'LTI_Processor_on' operation is executed and the stored current state 'a' (S17), activating the add-on card with the 'PCI ON #' signal set to 'L' (S18), returning the CPU clock to its original state as in the normal operation state;
/ RTI >
(j) determining whether the wakeup state is not the standby mode (S3 mode) (S21);
(k) If it is not the standby mode (S3 mode) as a result of the determination in the step (j), the process proceeds to the step (f) and continues to perform. If the result is 'yes', the 'RUN Suspend to RAM' (S22) of entering a standby mode (S3 mode) in which a minimum current is supplied only to the RAM memory and a power supply is cut off to another resource after storing the current state in the RAM; And
(l) determining whether the wakeup state is in a standby mode after step (k) (S23);
,
As a result of the determination in step (1), if it is not the wakeup state, the LTI_Processor_on operation is continuously performed. If the wakeup state is present, the process proceeds to step (g) And the 'PCI ON #' signal is set to 'L' to activate the add-on card. Wherein the standby power cutoff and the energy saving method of the computer system are performed. A super IO 19 that receives power from a power supply such as the SMPS 20 via an ATX power connector 60 and recognizes the power button 13 through the PIC 119 when the power button 13 is activated; Is inserted between the super IO 19 and the power button 13 and is supplied with power from a power supply such as the SMPS 20 through the ATX power connector 60 and is recognized when the power button 13 is activated A PIC (119) for notifying the super IO (19) and performing USB interfacing; A first power switching unit inserted between the super IO 19 and the ATX power connector 60 for receiving standby power ON / OFF signals of the PIC 119 and controlling whether an operation voltage 5VSB_ATX is output 140); A chipset 14 receiving a power on (PWRON #) signal from the super IO 19 and informing the super IO 19 of the current power state (mode) through 'SLP' signal line terminals; A second power switching unit 141 for controlling at least one PIC 151 by a PCI_ON # signal of the PIC 119; And a ROM BIOS 10b for programming to output the super IO 19 according to the current mode; The PIC 119 determines that the LTI of the OS 10c is in a long-term idle mode when it is determined by the signal from the chipset 14 and the super I / (Long-Term Idle_Processor_off) operation saves energy while allowing the operation of the CPU 11 to be relatively slower than that in the operation mode, causing the LTI_processor off operation to be started, Up state of the computer system using the standby power cut-off and energy saving device,
(c) during operation of the computer system, determining whether the computer is in a long-term idle state (S13);
(d) If it is not in the long-term idle state as a result of the judgment in the step (c), it continues to check. If it is YES, CPU clock is dropped and a PCI ON # H 'and deactivating the add-on card (S14);
(e) If the result of the determination in step (c) is 'YES', the PIC 119 outputs a 'LTI_Processor_off' signal to the OS to perform a 'RUN Energy saver program' The current state ('a' State) and stopping processes that are not essential processes (S51 to S56);
(f) determining whether the computer system is woken up (S16); And
(g) If the result of step (f) is 'YES', the 'LTI_Processor_on' operation is executed and the stored current state 'a' (S17), activating the add-on card with the 'PCI ON #' signal set to 'L' (S18), returning the CPU clock to its original state as in the normal operation state;
/ RTI >
The step (e)
(e1) the OS 10c calls (S52) a list of 'LTI_Processor_off';
(e2) the OS 10c confirms the process being executed in the processor manager and stores the current state ('a' state) information in preparation for the return (S53);
(e3) determining (S54) whether the 'Processor ID' of the 'LTI_Processor_off' target process on the 'LTI_Processor_off' list is the same as the process being executed;
(e4) if the result of the determination in the step (e3) is not the same, the process is continuously executed for the next process, and the same process as the process on the list is terminated (process turning off) (S55); And
(e5) determining whether the steps (e3) and (e4) have been performed for all processes on the 'LTI_Processor_off' list (S56);
Lt; / RTI >
If it is determined in step (e5) that all processes on the 'LTI_Processor_off' list have not been performed, the process proceeds to step (e3) to continue execution. If yes, the process proceeds to step (f) Wherein the standby power cut-off and the energy saving method of the computer system are performed. The method of claim 3,
The step (e)
(e1) the OS 10c calls (S52) a list of 'LTI_Processor_off';
(e2) the OS 10c confirms the process being executed in the processor manager and stores the current state ('a' state) information in preparation for the return (S53);
(e3) determining (S54) whether the 'Processor ID' of the 'LTI_Processor_off' target process on the 'LTI_Processor_off' list is the same as the process being executed;
(e4) if the result of the determination in the step (e3) is not the same, the process is continuously executed for the next process, and the same process as the process on the list is terminated (process turning off) (S55); And
(e5) determining whether the steps (e3) and (e4) have been performed for all processes on the 'LTI_Processor_off' list (S56);
Lt; / RTI >
If it is determined in step (e5) that all processes on the 'LTI_Processor_off' list have not been performed, the process proceeds to step (e3) to continue execution. If yes, the process proceeds to step (f) Wherein the standby power cut-off and the energy saving method of the computer system are performed. The method according to claim 1,
The step (e)
(e1) the OS 10c calls (S52) a list of 'LTI_Processor_off';
(e2) the OS 10c confirms the process being executed in the processor manager and stores the current state ('a' state) information in preparation for the return (S53);
(e3) determining (S54) whether the 'Processor ID' of the 'LTI_Processor_off' target process on the 'LTI_Processor_off' list is the same as the process being executed;
(e4) if the result of the determination in the step (e3) is not the same, the process is continuously executed for the next process, and the same process as the process on the list is terminated (process turning off) (S55); And
(e5) determining whether the steps (e3) and (e4) have been performed for all processes on the 'LTI_Processor_off' list (S56);
Lt; / RTI >
If it is determined in step (e5) that all processes on the 'LTI_Processor_off' list have not been performed, the process proceeds to step (e3) to continue execution. If yes, the process proceeds to step (f) Wherein the standby power cut-off and the energy saving method of the computer system are performed.

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