KR101623756B1 - A method for interrupting power supply in an apparatus for interrupting power supply utilizing the voltage supplied to the system memory - Google Patents

A method for interrupting power supply in an apparatus for interrupting power supply utilizing the voltage supplied to the system memory Download PDF

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Publication number
KR101623756B1
KR101623756B1 KR1020150186076A KR20150186076A KR101623756B1 KR 101623756 B1 KR101623756 B1 KR 101623756B1 KR 1020150186076 A KR1020150186076 A KR 1020150186076A KR 20150186076 A KR20150186076 A KR 20150186076A KR 101623756 B1 KR101623756 B1 KR 101623756B1
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South Korea
Prior art keywords
power
main board
switching device
signal
pwr
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KR1020150186076A
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Korean (ko)
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정성일
최성식
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사회복지법인 한국소아마비협회
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
    • G06F1/3234—Power saving characterised by the action undertaken
    • G06F1/3287—Power saving characterised by the action undertaken by switching off individual functional units in the computer system
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
    • G06F1/3206—Monitoring of events, devices or parameters that trigger a change in power modality
    • G06F1/3215—Monitoring of peripheral devices
    • G06F1/3225—Monitoring of peripheral devices of memory devices
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
    • G06F1/3234—Power saving characterised by the action undertaken
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
    • G06F1/3234—Power saving characterised by the action undertaken
    • G06F1/3296—Power saving characterised by the action undertaken by lowering the supply or operating voltage
    • Y02B60/121—

Abstract

According to the present invention, a method for interrupting standby power by using a system memory power supply is performed by a standby power interrupting device including a main board, a microcomputer, an SMPS, a power connector, a first switching device, and a detection unit which detects a voltage (V_DD) supplied to a memory and notifies the microcomputer of the detected voltage. The method for interrupting standby power by using a system memory power supply comprises the steps of: determining whether a PC power switch is turned ″on″; when the PC power switch is turned ″on″, activating a power control signal (PWR_CTRL), outputting the power control signal (PWR_CTRL) to the first switching device, and transferring a power output signal (PWR_OUT) to a 5V SB terminal of the main board; operating the main board by outputting a switching signal (SW_OUT) to the second switching device to turn on a transistor of the second switching device and applying a PS_ON# signal to a power button of the main board to activate a PS_ON# terminal of a connector through the power button and a PS-ON# circuit of a super I/O in the main board; checking a voltage (V_DD) supplied to a system memory of the main board; determining whether the checked voltage (V_DD) is less than a certain reference voltage (Vr); and when the checked voltage (V_DD) is equal to or greater than the certain reference voltage (Vr), maintaining a 5V SB power ″on″ state as it is, and when the checked voltage (V_DD) is less than the certain reference voltage (Vr), deactivating the power control signal (PWR_CTRL) to output the power control signal (PWR_CTRL) to the first switching device, so that the first power switching device disables the power output signal (PWR_OUT) to turn ″off″ system standby power in response to the outputting of the power control signal (PWR_CTRL).

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a standby power interruption method for a standby power interruption device utilizing system memory power,

The present invention relates to a standby power cut-off method for a power supply of a computer, and more particularly to a standby power cut-off method for a standby power cut-off device utilizing a system memory power providing a method for shutting off standby power by utilizing system memory power .

1, a power supply 20 such as an SMPS is connected to the SIO 12 of the main board 10 through 24 pins, one of which is connected to a standby Voltage (+ 5VSB).

When the user presses the power switch (not shown) of the PC case, the mechanically connected power button 13 is pressed, the power button 13 sends the first signal PWRBTN # to the SIO 12, The power supply 20 activates the power-on signal line PSON # with the power supply 20 and issues the second signal PWRBTN # _SB to the chipset 14. The power supply 20 is connected to the CPU 11 ) And the chipset 14 to inform it of the power supply signal, and then supply power to the main board.

Reference numeral 15 denotes a reset button of the chipset, 16 is a battery, 17 is a reset reset (17), and 18 is a LAN. In addition, AC, FWH, Super IO 19, AGP slot, PCI slot, IDE connected to the CPU and the chipset are connected.

Meanwhile, as described above, +5 V standby power is applied between the power supply 20 and the main board during non-operation, and standby power of about 1 W is required for recognizing the start button and recognizing the remote start do.

And this leads to a waste of energy, which is never high individually, and a huge amount of energy for a whole organization and even for a whole country.

In order to solve such a problem, there has been developed a socket having a switch which completely cuts off the power supply from the power socket itself to make the standby power zero (first prior art). On the other hand, Korean Patent Publication No. 2013-0043923 (Second conventional technique) for recognizing the on / off state of the power switch to completely shut off the power supply, such as the power supply device and the image forming apparatus including the power supply device.

However, in the case of the first prior art, in spite of the fact that it is practically possible for the user to sit in the outlet without turning off the power supply completely disconnected from the outlet, the second prior art is very complicated and expensive It is indispensable to mount such a device on a general PC.

Accordingly, the present inventor has proposed a computer power supply apparatus which is very simple but minimizes standby power automatically, and proposed Korean Patent No. 1328393 (name: computer power supply apparatus whose standby power is reduced) This will be described as a third prior art.

As shown in FIG. 2, the third prior art technology has a CPU 11, an SIO 12, a power button 13, a chipset 14, a reset button 15, a first battery 16, a LAN 18 ) And a super IO (19); An SMPS (20) for supplying power to the main board; A microcomputer 30 for controlling standby power supply of the SMPS; A power connector 60 for mediating signal and standby power connection between the main board and the SMPS; And a switching device (40) for switching standby power on / off according to the control of the microcomputer; The microcomputer 30 controls the standby power supplied to the main board by controlling the standby power (5VSB) of the power supply by the switching device 40. [

2, the power supply apparatus of the third prior art includes an existing CPU 11, an SIO 12, a power button 13, a chipset 14, a reset button 15, A main board 10 having a power supply 16, a resetting reset 17, a LAN 18, a super IO 19, and the like, an SMPS 20 for supplying power to the main board, And a switching device 40 for switching the standby power on / off according to the control of the microcomputer 30 and the microcomputer. The reference numeral 50 denotes a power switch of the PC case, and 60 denotes a power connector between the main board and the SMPS.

In the present invention, the power connector 60 mediates signal and standby power connection between the main board 10 and the SMPS 20, and the SMPS 20 and the power connector are connected by 23 pins, The + 5V standby power line (+ 5VSB), which is one pin, is connected to the microcomputer 30 and the switching element 40 instead of the power connector, which is different from the conventional power supply of FIG. The switching device 40 may be a power switch IC or an FET circuit.

In addition, the microcomputer 30 receives the signal of either or both of the SMPS good signal (PS_ON #) and the power good signal (PWR_ON) from the SMPS 20 from the SMPS 20. The power good signal PWR_ON is also applied to the CPU 11 and the chipset 14.

Meanwhile, the microcomputer 30 also starts the standby power supply start operation by the switching signal CASE_PWR_BTN from the external case power switch 50, so that the standby power of +5 V (+ 5VSB) The control signal 5VSB_SW of the microcomputer 30 is applied to the main board 10 as a 5V standby signal P5V_STBY through the switching element 40. When the control signal 5VSB_SW of the microcomputer 30 is' And the + 5V standby power (+ 5VSB) from the SMPS 20 is applied to the main board 10 as the 5V standby signal P5V_STBY.

From the SMPS (20) power connector to the mainboard (10) power connector, the PC's normal operating power goes to + 12V and -12V lines, + 5V standby power lines, + 3.3V power lines, and power hardening (PWR_ON) signals. However, the 5V standby power line (5VSB) goes to the switching device (40), and the standby power signal (P5V_STBY) goes from the switching device (40) back to the main board power connector.

Further, the standby power switch signal 5VSB_SW from the microcomputer 30 to the switching element 40 and the power button signal MB_PWR_BTN to the main power button 12 go.

Conversely, the SMPS good (PS_ON #) signal goes from the mainboard 10 power connector to the SMPS 20 power connector.

First, the microcomputer 30 of the third prior art controls the standby power (5VSB) of the power supply by the switching device 40 to control the power supplied to the main board When the power is off, the microcomputer senses the power cord PWR_ON and / or SMPS good signal (PS_ON #) between the connectors, and turns off the 5V standby power when the power is off. That is, in this case, since standby power is not supplied to the main board, the computer can not be turned on.

On the other hand, when the PC user presses the case power switch 50, the microcomputer 30 of the present invention is activated by this signal, and the microcomputer converts the power cord PWR_ON and / or the SMPS good signal PS_ON # When the power is on, the control signal 5VSB_SW to the switching element 40 is turned on so that the 5V standby power source 5VSB is applied to the main board. When the power button 13 of the main board is turned on, an input / output start command is issued to the SIO 12, and the SIO 12 transmits power supply completion signal PS_ON # to the SMPS 20 via the power connector 60. [ The SMPS transmits the PWR_ON signal to the main board 10 via the connector 60 and activates the main board operation power source (+12 V) when the situation is normal.

Therefore, according to the third prior art, standby power and computer start-up can be performed only by standby power of about 0.1 W corresponding to the standby power of the microcomputer without consuming standby power of 1 W corresponding to standby power of the computer activation system There are advantages.

By the way, the system is powered on. And 'off', recent PCs adopt the S1 to S5 mode, adopting various refined modes, thereby achieving the most efficient system operation with higher speed and resource utilization. For reference, the S0 mode is a computer operation mode, the S1 mode is a state in which the processor is in an idle state and is in a low power supply state or a state in which power is still supplied to the RAM, and S2 mode is a deep sleep mode However, in the S3 mode (power saving / standby mode), the power is still supplied to the RAM. In this case, the + 5V SB should not be turned off as the data is stored in the memory and the minimum power is maintained. At this time, depending on the type of DDR memory, VDD power is maintained at 1.2 ~ 1.5V, but power is supplied only to some parts such as memory and RTC. On the other hand, in S4 mode (hibernate mode), the data is stored on the hard disk and all the system power is turned off. That is, it is almost the same as the power OFF state. At this time, VDD power of memory is output as 0 V as when power is OFF. In other words, the VDD signal is 0 V in the OFF state of the system standby power and in the case of the S4 mode, and the system operation which is the standby power ON condition (Power ON state) and S3 (power saving / standby mode), the VDD signal outputs 1.2 to 1.5V.

Therefore, in the case of the system having the recent S0 to S5 mode, in the case of the third prior art, it is necessary to check all the states of the power source in order to block such standby power. 2) Checking some signals such as 'power good', and checking them. 1) When checking the current, an expensive analog-to-digital converter (ADC) and a peripheral circuit are required There is no cost-effective value to reduce standby power of 1W. 2) Also, when checking through signals such as 'power good', all power can not be checked by one signal. Therefore, Structure, which leads to a problem of low production efficiency.

On the other hand, a conventional general power-on operation will be described with reference to Figs. 3 to 7. Fig.

3, the PS_ON circuit 19a in the super IO 19 recognizes the power ON state when the power button is turned on, as shown in FIG. 3, The PS_ON # terminal of the 20-pin connector of the SIO 12 of the main board 10 is activated while communicating with the south bridge of the chipset 14 so that power is applied to the main board 10.

An example of the block diagram of the PS_ON circuit 19a of FIG. 3 is shown in detail in FIG. 4, when the switch S1 corresponding to the power button is pressed, the PS_ON circuit 19a is activated while falling to a low level, so that various voltages are applied from the SMPS to the main board (See the timing chart of Fig.

On the other hand, FIG. 6 shows another example of a conventional power-on operation concept. When power-on switching (PWR) is performed, the chipset 14 transmits the P.ON signal to the SIO 12, And the SIO 12 outputs the PON signal to the PS_ON # terminal of the connector of the main board so that the power is applied from the SMPS to the main board.

Figure 7 is a timing chart of the respective signals of Figure 6; When the VAC is activated (AC power is applied), the PS_ON # signal falls to a low level and is activated. Various voltages are applied from the SMPS to the main board, and the power is responded with a good signal.

6, the PS_ON # signal (SMPS power on) is also turned on first by turning on the + 5V SB signal and then by connecting the south bridge and the Super I / O chipset , The PS_ON # signal is generated in the SMPS, and the connection and remodeling workability of the cable is poor, resulting in low productivity.

Korean Patent Publication No. 2013-0043923 (Patent Application No. 2011-0108115) Korea Patent No. 1328393 (name: computer power supply device with reduced standby power)

The present invention is intended to provide a computer power supply device that is very simple and automatically minimizes standby power even in a computer system having various operation modes.

Furthermore, in order to make the product with the highest price efficiency by the method of cutting off the standby power, it is necessary to implement the technology with an extremely simple configuration. In order to increase the productivity, a system memory power supply The present invention provides a standby power cut-off method for a standby power cut-off device utilizing the above-described method.

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According to an aspect of the present invention, there is provided a method of isolating standby power using a system memory power supply, the method including: a main board; An SMPS (20) for supplying power to the main board; A microcomputer 30 for controlling standby power supply of the SMPS; A power connector 60 for mediating signal and standby power connection between the main board and the SMPS; And a first switching device (40) for switching standby power on / off according to the control of the microcomputer; The microcomputer 30 further includes a sensing unit 70 for sensing a voltage V DD supplied to the memory 10a of the main board 10 and notifying the microcomputer 30 of the sensed voltage V DD , Compares the voltage V DD sensed by the sensing unit 70 with the reference voltage Vr to control the standby power 5VSB of the power supply by the first switching device 40, The PS_ON # signal for starting the operation of the main board is directly transferred from the microcomputer 30 to the main board 10 via the second switching device 41, The standby power interruption method using the system memory power supply is characterized in that the standby power interruption method is carried out by the PS_ON circuit 19a of the microcomputer 30 ) Determining whether the PC power switch is 'on'(S2); (c) If it is determined to be YES in step (b), the power control signal PWR_CTRL is activated and output to the first switching device 40, and the first switching device 40 ) Sending the power output signal PWR_OUT to the 5V SB terminal of the main board (S3); (d) In addition to the step (c), a switching-out signal (SW_OUT) is outputted to the second switching device (41) to turn on the transistor (Q2) of the second switching device The PS_ON # signal is applied to the PS_ON # signal of the connector 60 via the power button 13 and the PS_ON circuit 19a of the super I / O 19 of the main board, Operating the main board (S4 '); (e) checking (S5) the voltage (V DD ) supplied to the system memory (10a) of the main board (10) after the step (d); (f) determining whether the voltage V DD supplied to the system memory 10a detected in the step (e) is less than a predetermined reference voltage Vr (S6); And (g) if it is determined in step (f) that the sensed voltage (V DD ) is equal to or greater than a predetermined reference voltage (Vr) The power control signal PWR_CTRL is deactivated and output to the first switching device 40. In response to the power control signal PWR_CTRL, the first switching device 40 outputs the power output signal PWR_CTRL to the first switching device 40, (S7) of disabling the system standby power (PWR_OUT) and turning off the system standby power; In step (f), it is determined whether the voltage V DD supplied to the system memory 10a is less than a predetermined reference voltage Vr, in a maximum power saving mode (S4 mode) or a power off mode (S5 mode).
The power control signal PWR_CTRL is output from the microcomputer 30 and is supplied to the first and third transistors Q1 and Q3 of the first switching device 40 in step (c) And outputs the power output PWR_OUT signal to the 5V SB terminal of the connector of the main board 10.
The voltage V DD supplied to the system memory 10a of the main board 10 may be supplied to the fourth transistor Q4 of the sensing unit 70 in step (e) And is notified to the microcomputer 30 through a power terminal (GD_PWR) of the microcomputer 30.

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According to the standby power cut-off method of the standby power cut-off device utilizing the system memory power supply according to the present invention, a method of checking the power supply (V DD ) supplied to the memory by the standby power reduction method, even in a computer system having various operation modes This signal can be used to determine the power supply status of the system. In case of "power on" and S3 (standby mode), it will be about 1.2 ~ 1.5V depending on the memory type. 0V ", it becomes possible to grasp the standby power cutoff condition in an extremely simple manner. That is, in a very simple manner, the standby power can be minimized to about 0.1 to 0.2 W at about 1 W of the conventional one, thereby providing a computer power supply capable of further saving energy.

The PS_ON # signal (SMPS power on) is also turned on first by turning on the + 5V SB signal and then connecting it to the power 'on' switch end of the main board as shown in FIG. 6 to connect the south bridge and the Super I / O chipset The PS_ON # signal is generated in the SMPS through the microcomputer. In the present invention, however, the microcomputer generates a signal directly to reduce the delay time and the hassle of cable connection.

Other objects and advantages of the present invention will become apparent from the detailed description of the embodiments with reference to the attached drawings.

1 is a conceptual diagram of a conventional computer power supply;
2 is a block diagram of a computer power supply in which standby power is reduced according to the third prior art.
3 is a view for explaining a concept of a conventional general power-on operation;
4 is a block diagram of the PS_ON circuit 19a of Fig.
5 is a timing chart of the signals of FIG. 3;
FIG. 6 is another example of a concept of a conventional general power-on operation; FIG.
FIG. 7 is a timing chart of the signals of FIG. 6; FIG.
8 is a block diagram of a computer power supply apparatus in which standby power is reduced according to the first embodiment of the present invention;
9 is a detailed circuit diagram of a computer power supply apparatus in which standby power is reduced according to the first embodiment of the present invention;
FIG. 10 is a flowchart illustrating the operation of the microcomputer of the computer power supply apparatus according to the first embodiment of the present invention in which standby power is reduced. FIG.
11 is a block diagram of a computer power supply apparatus in which standby power is reduced according to a second embodiment of the present invention;
12 is a detailed circuit diagram of a computer power supply apparatus in which standby power is reduced according to a second embodiment of the present invention;
FIG. 13 is a flowchart illustrating an operation of a microcomputer of a computer power supply apparatus that reduces standby power according to a second embodiment of the present invention. FIG.

Hereinafter, preferred embodiments according to the present invention will be described in detail with reference to the accompanying drawings.

It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the invention, You will know.

(Embodiment 1)

First, a computer power supply apparatus for reducing standby power according to the first embodiment of the present invention will be described with reference to FIG. 2 and FIG. 8 to FIG.

FIG. 8 is a block diagram of a computer power supply apparatus for reducing standby power according to the first embodiment of the present invention. FIG. 9 is a detailed circuit diagram of a computer power supply apparatus for reducing standby power according to the first embodiment of the present invention. And FIG. 10 is a flowchart illustrating the operation of the microcomputer of the computer power supply apparatus according to the first embodiment of the present invention in which standby power is reduced.

First, the invention of the first embodiment of the present invention will be described with reference to the block diagram of FIG. 8. First, it is detected whether the PC power source 50 is 'on', and the ATX power from the SMPS 20 to the main board Activate the PS_ON # signal on the cable to a "low" level, leaving the line except the 5V SB line to go to the mainboard. At this time, the 5V SB line does not directly go to the main board, but provides Vcc to the microcomputer 30 and the switching device 40 and activates them, thereby activating the power control signal PWR_CTRL, And the switching device 40 sends the power output signal PWR_OUT to the 5V SB terminal of the mainboard in response to the power supply, so that the main board is operated while all power is supplied to the main board.

Thereafter, the voltage supplied to the main board RAM (for example, the DDR memory 10a) is checked. If the voltage is equal to or higher than a predetermined voltage (the RAM is in operation), the 5V SB power ' The power supply signal PWR_CTRL is deactivated and outputted to the switching element 40. In response to the power control signal PWR_CTRL, the switching element 40 outputs a power output signal PWR_OUT) to disable the system standby power.

9, the on / off state of the PC power 'on' switch 50 is provided through the switching input (SW_IN) terminal (pin 16 of the chip) of the microcomputer 30 .

Thereafter, the microcomputer 30 outputs the PS_ON # signal to the SMPS 20 via the PS_ON # terminal (pin 2 of the chip) (see the green line in FIG. 9) , 5V, 3.3V, 12V, power cord (PWR_OK) signal lines, and the like are all connected at the same time by activating the common ground terminal (from "high" to "low" Activate to go to main board terminal. That is, various kinds of power are applied from the SMPS to the main board.

The power control signal PWR_CTRL is output through the 14th pin of the microcomputer 30 to activate the first and third transistors Q1 and Q3 of the switching device 40 to output the power output PWR_OUT signal To the 5V standby signal terminal of the connector of the main board 10. This means that the main board (computer) including the function of the memory finally operates.

Lastly, the voltage supplied to the memory (for example, DDR3) of the main board 10 is sensed by the fourth transistor Q4 of the sensing unit 70, and the result is the power GD_PWR Pin 15 of the chip).

The operation of the microcomputer of the first embodiment of the present invention will be described in detail with reference to FIG.

First, the microcomputer 30 of the present invention is operated when the system standby power is in the off state (in a state in which the AC power is not inputted). (S1). In such a case, is the PC power switch "on"? The power control signal PWR_CTRL (PWR_CTRL) is set to the power control signal PWR_CTRL (step S2). If the power control signal PWR_CTRL To the switching device 40 and the switching device 40 sends the power output signal PWR_OUT to the 5V SB terminal of the mainboard so that all the power is supplied to the main board S3). At the same time, the PS_ON # signal is activated to operate the main board (S4).

Thereafter, the voltage V DD supplied to the memory 10a of the main board is checked (S5), and it is determined whether it is less than a predetermined voltage (for example, 0.7 V) (S6). If the voltage is abnormal ), The 5V SB power 'on' state is maintained as it is and the power supply to the main board is continued. Otherwise, the memory is deemed to be stopped and the power control signal PWR_CTRL is deactivated, The switching device 40 disables the power output signal PWR_OUT and turns off the system standby power (S7).

That is, as described above in the related art, the + 5V SB should not be turned off in the S3 mode (power saving / standby mode), while in the S4 mode (the maximum power saving mode) Turn off all power. That is, in the S4 mode and the S5 mode in which the power is OFF, 0V is output. In other words, the VDD signal is 0 V in the OFF state of the system standby power and in the case of the S4 mode, and the system operation which is the standby power ON condition (Power ON state) and S3 (power saving / standby mode), the VDD signal outputs 1.2 to 1.5V. Therefore, in S5 and S6, the voltage V DD supplied to the memory is checked (S5), and it is determined whether or not it is less than a predetermined voltage (Vr: 0.7 V, for example) The power 'on' state is maintained, and less than (V DD ≪ Vr), the system standby power is turned off (S7). However, it will be understood by those skilled in the art that the voltage (V DD ) supplied to the memory is not necessarily limited to 0.7 V, and may be changed by any other new system.

(Second Embodiment)

Hereinafter, a computer power supply apparatus for reducing standby power according to a second embodiment of the present invention will be described with reference to FIGS. 11 to 13. FIG.

FIG. 11 is a block diagram of a computer power supply apparatus for reducing standby power according to a second embodiment of the present invention, and FIG. 12 is a detailed circuit diagram of a computer power supply apparatus for reducing standby power according to the second embodiment of the present invention. And FIG. 13 is a flowchart of the operation of the microcomputer of the computer power supply apparatus in which standby power is reduced according to the second embodiment of the present invention.

In the second embodiment, there is a difference in the application method of the PS_ON # signal as compared with the first embodiment (see S4 'in FIG. 13).

That is, in the method of this embodiment, the microcomputer applies the PS_ON # signal to the SMPS 20 to turn on the SMPS, and in response, the signal and the common ground signal interlocked therewith are transmitted from the SMPS to the main board 10 via the ATX cable Another signal and power source are applied to the main board so that the microcomputer 30 directly applies the PS_ON # signal to the main board without passing through the SMPS.

4 to 6, the microcomputer 30 receives a signal that the PC power switch is on and activates the power control signal PWR_CTRL to the first switching device 40, The power supply signal PWR_OUT is sent to the 5V SB terminal of the main board through the first switching device 40 so that all the power is supplied to the main board S3 and the second switching device 41 is turned on, The transistor Q2 of the second switching device 41 is turned on and the PS_ON # signal is applied to the power button 13 of the main board. The PS_ON # terminal of the connector 60 is activated through the power button 13 and the PS_ON circuit 19a of the main I / O 19 to operate the main board (S4 '). Thereafter, the other processes are the same as those in the first embodiment.

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The microcomputer 30 applies the PS_ON # signal directly to the power button 13 of the main board 10 through the second switching device 41 (see FIGS. 11 and 12) Signal to the PS_ON # terminal of the power connector 60 through the PS_ON circuit 19a of the main controller 19 to operate the main board. Instead, it is not necessary to give a signal directly to the system IO 12 from the power button 13 (see FIG. 2).

Therefore, according to the technology of the second embodiment, it is possible to provide a computer power supply device having a standby power cut-off device of a simple configuration which can perform a power saving operation more quickly and directly than the first embodiment and does not require a separate additional cable .

While the present invention has been described in connection with what is presently considered to be practical exemplary embodiments, it is to be understood that the invention is not limited to the disclosed embodiments, but, on the contrary, Of course.

10: Motherboard
11: CPU 12: SIO (System IO)
13: Power button 14: Chipset
15: reset button 16: first battery
17: RESET RESET 18: LAN
19: Power IO (Power IO) 19a: PS_ON circuit
20: Power supply (SMPS) 30: Microcomputer
40: first switching element 41: second switching element
50: Case power switch 60: Power connector
70: V DD sensing unit

Claims (8)

delete delete delete delete delete A main board 10;
An SMPS (20) for supplying power to the main board;
A microcomputer 30 for controlling standby power supply of the SMPS;
A power connector 60 for mediating signal and standby power connection between the main board and the SMPS; And
A first switching device (40) for switching standby power on / off according to the control of the microcomputer; And,
Further comprising a sensing unit (70) for sensing a voltage (V DD ) supplied to the memory (10a) of the main board (10a) and notifying the microcomputer (30)
The microcomputer 30 compares the voltage V DD sensed by the sensing unit 70 with the reference voltage Vr and controls the standby power 5VSB of the power supply by the first switching device 40 , The standby power supplied to the main board is controlled,
The PS_ON # signal for starting operation of the main board is directly transferred from the microcomputer 30 to the main board 10 through the second switching device 41 and is supplied to the main board 10 by the PS_ON circuit 19a Wherein the standby power interruption device is connected to the power connector (60) on the main board side. The standby power interruption method utilizes a system memory power supply,
(b) determining whether the microcomputer 30 is turned on (S2);
(c) If it is determined to be YES in step (b), the power control signal PWR_CTRL is activated and output to the first switching device 40, and the first switching device 40 ) Sending the power output signal PWR_OUT to the 5V SB terminal of the main board (S3);
(d) In addition to the step (c), a switching-out signal (SW_OUT) is outputted to the second switching device (41) to turn on the transistor (Q2) of the second switching device The PS_ON # signal is applied to the PS_ON # signal of the connector 60 via the power button 13 and the PS_ON circuit 19a of the super I / O 19 of the main board, Operating the main board (S4 ');
(e) checking (S5) the voltage (V DD ) supplied to the system memory (10a) of the main board (10) after the step (d);
(f) determining whether the voltage V DD supplied to the system memory 10a detected in the step (e) is less than a predetermined reference voltage Vr (S6); And
(g) If it is determined in step (f) that the sensed voltage (V DD ) is equal to or higher than the predetermined reference voltage (Vr), the power supply to the main board is maintained The power control signal PWR_CTRL is deactivated and output to the first switching device 40. In response to the power control signal PWR_CTRL, the first switching device 40 outputs the power output signal PWR_OUT) to turn off the system standby power (S7);
, ≪ / RTI &
In step (f), it is determined whether the voltage V DD supplied to the system memory 10a is less than the predetermined reference voltage Vr, in the maximum power saving mode (S4 mode) or the power off mode (S5 mode) And determining whether or not the standby power is turned off. The method according to claim 6,
In step (c), the power control signal PWR_CTRL is output from the microcomputer 30 to activate the first and third transistors Q1 and Q3 of the first switching device 40 , And outputs a power output (PWR_OUT) signal to the 5V SB terminal of the connector of the main board (10). The method according to claim 6,
In step (e), the voltage V DD supplied to the system memory 10a of the main board 10 is sensed by the fourth transistor Q4 of the sensing unit 70, Is informed to the microcomputer (30) through the power cord (GD_PWR) terminal of the microcomputer (30).
KR1020150186076A 2015-12-24 2015-12-24 A method for interrupting power supply in an apparatus for interrupting power supply utilizing the voltage supplied to the system memory KR101623756B1 (en)

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