KR101805879B1 - An apparatus and method for saving the energy consumption in a computer system by using the controling signals of a memory power supply controller(MPSC) - Google Patents

Abstract

The present invention relates to an apparatus and a method for saving energy of a computer system using a control signal of a memory power supply controller (MPSC), more specifically, to an apparatus which has a technology more advanced than a technology for blocking standby power which is currently being developed in a computer system having various operation modes (e.g., S0 to S5 modes) to minimize power consumption by using a 5VSB power source for driving a circuit during only a normal operation, and using 1.2 V for driving the remainder, and implements the same with only one switching device, and recognizes a sleep mode and blocks 5VSB in a software scheme. According to an aspect of the present invention, the apparatus for saving energy of a computer system using a control signal of an MPSC, which comprises: a main board (10) including a central processing unit (CPU) (11), a system IO (SIO) (19), a chipset (14), a memory (10a, 10a), and an MPSC (17) for controlling power supply of the memory; a switching mode power supply (SMPS) (20) connected to the main board through an advanced technology x-trended (ATX) power connector (16); and various peripheral devices. The apparatus of the present invention further comprises a lowest voltage supply unit (50) for blocking the supply of a 5VSB standby power to the ATX power connector (16) of the SMPS (20), and supplying the lowest voltage to the memory (10a, 10a) of the main board in the sleep mode. The determination of whether the lowest voltage supply unit (50) is in the sleep mode, is performed by a control signal of the MPSC.

Description

[0001] The present invention relates to an apparatus and a method for saving energy of a computer system using a control signal of an MPSC,

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a technique for optimizing a standby power of a main board of a computer and a power supply supplied thereto from a stand-by mode, By stopping the driving, standby power can be optimized. In particular, addition of simple switching element and PIC (Programmable IC) to MPSC (Memory Power Supply Controller) and energy saving of computer system using MPSC control signal solving this by software Apparatus and method.

1, a power supply 20 such as an SMPS is connected to the SIO 12 of the main board 10 through 24 pins, one of which is connected to a standby Voltage (+ 5VSB).

When the user presses the power switch (not shown) of the PC case, the mechanically connected power button 13 is pressed, the power button 13 sends the first signal PWRBTN # to the SIO 12, The power supply 20 activates the power-on signal line PSON # with the power supply 20 and issues the second signal PWRBTN # _SB to the chipset 14. The power supply 20 is connected to the CPU 11 ) And the chipset 14 to inform it of the power supply signal, and then supply power to the main board.

Reference numeral 15 denotes a reset button of the chipset, 16 is a battery, 17 is a reset reset (17), and 18 is a LAN. In addition, AC, FWH, Super IO 19, AGP slot, PCI slot, IDE connected to the CPU and the chipset are connected.

Meanwhile, as described above, +5 V standby power is applied between the power supply 20 and the main board during non-operation, and standby power of about 1 W is required for recognizing the start button and recognizing the remote start do.

And this leads to a waste of energy, which is never high individually, and a huge amount of energy for a whole organization and even for a whole country.

In order to solve such a problem, there has been developed a socket having a switch which completely cuts off the power supply from the power socket itself to make the standby power zero (first prior art). On the other hand, Korean Patent Publication No. 2013-0043923 (Second conventional technique) for recognizing the on / off state of the power switch to completely shut off the power supply, such as the power supply device and the image forming apparatus including the power supply device.

However, in the case of the first prior art, in spite of the fact that it is practically possible for the user to sit in the outlet without turning off the power supply completely disconnected from the outlet, the second prior art is very complicated and expensive It is indispensable to mount such a device on a general PC.

Accordingly, the present inventor has proposed a computer power supply apparatus which is very simple but minimizes standby power automatically, and proposed Korean Patent No. 1328393 (name: computer power supply apparatus whose standby power is reduced) This will be described as a third prior art.

As shown in FIG. 2, the third prior art technology has a CPU 11, an SIO 12, a power button 13, a chipset 14, a reset button 15, a first battery 16, a LAN 18 ) And a super IO (19); An SMPS (20) for supplying power to the main board; A microcomputer 30 for controlling standby power supply of the SMPS; A power connector 60 for mediating signal and standby power connection between the main board and the SMPS; And a switching unit (40) for switching standby power on / off according to the control of the microcomputer. And the microcomputer 30 controls the standby power supplied to the main board by controlling the standby power (5VSB) of the power supply by the switching unit 40. [

2, the power supply apparatus of the third prior art includes an existing CPU 11, an SIO 12, a power button 13, a chipset 14, a reset button 15, A main board 10 having a power supply 16, a resetting reset 17, a LAN 18, a super IO 19, and the like, an SMPS 20 for supplying power to the main board, And a switching unit 40 for switching the standby power on / off according to the control of the microcomputer 30 and the microcomputer. The reference numeral 50 denotes a power switch of the PC case, and 60 denotes a power connector between the main board and the SMPS.

In the third prior art, the power connector 60 mediates signal and standby power connection between the main board 10 and the SMPS 20, and the SMPS 20 and the power connector are connected with 23 pins 1 is different from the conventional power supply of FIG. 1 in that a + 5V standby power line (+ 5VSB) which is one pin instead of a power connector is connected to the microcomputer 30 and the switching unit 40 instead of the power connector. The switching unit 40 may be a power switch IC or an FET circuit.

In addition, the microcomputer 30 receives the signal of either or both of the SMPS good signal (PS_ON #) and the power good signal (PWR_ON) from the SMPS 20 from the SMPS 20. The power good signal PWR_ON is also applied to the CPU 11 and the chipset 14.

Meanwhile, the microcomputer 30 also starts the standby power supply start operation by the switching signal CASE_PWR_BTN from the external case power switch 50, so that the standby power of +5 V (+ 5VSB) When the control signal 5VSB_SW of the microcomputer 30 is 'ON', the switching unit 40 applies the 5V standby signal P5V_STBY to the main board 10 through the switching unit 40, And the + 5V standby power (+ 5VSB) from the SMPS 20 is applied to the main board 10 as the 5V standby signal P5V_STBY.

From the SMPS (20) power connector to the mainboard (10) power connector, the PC's normal operating power goes to + 12V and -12V lines, + 5V standby power lines, + 3.3V power lines, and power hardening (PWR_ON) signals. However, the 5V standby power line (5VSB) goes to the switching device (40), and the standby power signal (P5V_STBY) goes from the switching device (40) back to the main board power connector.

Further, the standby power switch signal 5VSB_SW from the microcomputer 30 to the switching unit 40 and the power button signal MB_PWR_BTN to the main power button 12 go.

Conversely, the SMPS good (PS_ON #) signal goes from the mainboard 10 power connector to the SMPS 20 power connector.

First, the microcomputer 30 of the third prior art controls the standby power (5VSB) of the power supply by the switching unit 40 so as to control the power supplied to the main board When the power is off, the microcomputer senses the power cord PWR_ON and / or SMPS good signal (PS_ON #) between the connectors, and turns off the 5V standby power when the power is off. That is, in this case, since standby power is not supplied to the main board, the computer can not be turned on.

On the other hand, when the PC user presses the case power switch 50, the microcomputer 30 of the third prior art is activated by this signal, and the microcomputer controls the power good PWR_ON and / or the SMPS good PS_ON # And when the power is on, the control signal 5VSB_SW to the switching unit 40 is turned on so that the 5V standby power source 5VSB is applied to the main board. When the power button 13 of the main board is turned on, an input / output start command is issued to the SIO 12, and the SIO 12 transmits power supply completion signal PS_ON # to the SMPS 20 via the power connector 60. [ The SMPS transmits the PWR_ON signal to the main board 10 via the connector 60 and activates the main board operation power source (+12 V) when the situation is normal.

Therefore, according to the third prior art, standby power and computer start-up can be performed only by standby power of about 0.1 W corresponding to the standby power of the microcomputer without consuming standby power of 1 W corresponding to standby power of the computer activation system There are advantages.

Unlike conventional systems that only have the system power 'on' and 'off' states, modern PCs adopt the S1 to S5 mode, adopting various granular modes and thus the most efficient System operation. For reference, the S0 mode is a computer operation mode, the S1 mode is a state in which the processor is in an idle state and is in a low power supply state or a state in which power is still supplied to the RAM, and S2 mode is a deep sleep mode However, in the S3 mode (power saving / standby mode), the power is still supplied to the RAM. In this case, the + 5V SB should not be turned off as the data is stored in the memory and the minimum power is maintained. At this time, depending on the type of DDR memory, VDD power is maintained at 1.2 ~ 1.5V, but power is supplied only to some parts such as memory and RTC. On the other hand, in S4 mode (hibernate mode), the data is stored on the hard disk and all the system power is turned off. That is, it is almost the same as the power OFF state. At this time, VDD power of memory is output as 0 V as when power is OFF. In other words, the VDD signal is 0 V in the OFF state of the system standby power and in the case of the S4 mode, and the system operation which is the standby power ON condition (Power ON state) and S3 (power saving / standby mode), the VDD signal outputs 1.2 to 1.5V.

Therefore, in the case of the system having the recent S0 to S5 mode, in the case of the third prior art, it is necessary to check all the states of the power source in order to block such standby power. 2) Checking some signals such as 'power good', and checking them. 1) When checking the current, an expensive analog-to-digital converter (ADC) and a peripheral circuit are required There is no cost-effective value to reduce standby power of 1W. 2) Also, when checking through signals such as 'power good', all power can not be checked by one signal. Therefore, Structure, which leads to a problem of low production efficiency.

On the other hand, a conventional general power-on operation will be described with reference to Figs. 3 to 7. Fig.

3, the PS_ON circuit 19a in the super IO 19 recognizes the power ON state when the power button is turned on, as shown in FIG. 3, The PS_ON # terminal of the 20-pin connector of the SIO 12 of the main board 10 is activated while communicating with the south bridge of the chipset 14 so that power is applied to the main board 10.

An example of the block diagram of the PS_ON circuit 19a of FIG. 3 is shown in detail in FIG. 4, when the switch S1 corresponding to the power button is pressed, the PS_ON circuit 19a is activated while falling to a low level, so that various voltages are applied from the SMPS to the main board (See the timing chart of Fig.

On the other hand, FIG. 6 shows another example of a conventional power-on operation concept. When power-on switching (PWR) is performed, the chipset 14 transmits the P.ON signal to the SIO 12, And the SIO 12 outputs the PON signal to the PS_ON # terminal of the connector of the main board so that the power is applied from the SMPS to the main board.

FIG. 7 is a timing chart of the signals of FIG. 6, and when the VAC is activated (AC power is applied), the PS_ON # signal is activated while falling to a low level and various voltages are applied from the SMPS to the main board, It responds with a good signal.

6, the PS_ON # signal (SMPS power on) is also turned on first by turning on the + 5V SB signal and then by connecting the south bridge and the Super I / O chipset , The PS_ON # signal is generated in the SMPS, and the connection and remodeling workability of the cable is poor, resulting in low productivity.

In order to solve the above problems, the inventor of the present invention has proposed a computer power supply apparatus which is very simple and automatically minimizes standby power even in a computer system having various operation modes, And proposed a computer power supply device that reduces standby power and has been patented as a patent No. 1623756. [ This will be described with reference to FIG. 2 and FIGS. 8 to 10. FIG.

FIG. 8 is a block diagram of a computer power supply apparatus in which standby power is reduced according to a fourth conventional technique, FIG. 9 is a detailed circuit diagram of a computer power supply apparatus in which standby power is reduced according to a fourth conventional technique, 4 is a flowchart of the operation of the microcomputer of the computer power supply apparatus in which the standby power according to the related art is reduced.

First, the invention of the fourth related art will be described with reference to the block diagram of FIG. 8. First, it is detected whether the PC power source 50 is 'on', and the ATX power cable from the SMPS 20 to the main board Activate the PS_ON # signal to the 'low' level, causing the line except the 5V SB line to go to the mainboard. At this time, the 5V SB line does not go directly to the main board but provides Vcc to the microcomputer 30 and the first switching unit 40 and activates them, thereby activating the power control signal PWR_CTRL, The first switching unit 40 sends the power output signal PWR_OUT to the 5V SB terminal of the mainboard so that the main board is operated while all the power is supplied to the main board do.

At this time, the microcomputer 30 applies the PS_ON # signal to the SMPS 20 to turn on the SMPS, and the signal and the common ground signal interlocked therewith are transmitted from the SMPS to the main board 10 via the ATX cable, The microcomputer 30 may directly supply the PS_ON # signal to the main board through the second switching unit 41 without passing through the SMPS, as shown in FIG. 8, , But it is also possible to apply it to the PS_ON # terminal of the power connector 60 through the power button 13, the PS_ON circuit 19a, and the main board.

9, the on / off state of the PC power 'on' switch 50 is provided through the switching input (SW_IN) terminal (pin 16 of the chip) of the microcomputer 30 .

Thereafter, the microcomputer 30 activates the common ground terminal (turns from 'high' to 'low') so that all of the 5V, 3.3V, 12V, power cord (PWR_OK) So that various powers are applied from the SMPS to the main board. In addition, the PS_ON # signal may be output to the SMPS 20 through the PS_ON # terminal (pin 2 of the chip) and may be connected to the corresponding terminal of the power connector 60 of the main board 10 through the ATX power cable 9, the SW_OUT signal is output to the second switching unit 41 through the fifth terminal of the microcomputer, and the switching signal is output to the super IO 19 through the power button # 13 in the main board To the corresponding terminal of the power connector 60 by activating the PS_ON circuit 19a.

The power control signal PWR_CTRL is output through the 14th pin of the microcomputer 30 to activate the first and third transistors Q1 and Q3 of the switching unit 40 to output the power output PWR_OUT signal To the 5V standby signal terminal of the connector of the main board 10. This means that the main board (computer) including the function of the memory finally operates.

Lastly, the voltage supplied to the memory (for example, DDR3) of the main board 10 is sensed by the fourth transistor Q4 of the sensing unit 70, and the result is the power GD_PWR Pin 15 of the chip).

The operation of the microcomputer of the fourth conventional art will be described once again with reference to FIG.

First, the microcomputer 30 of the present invention is operated when the system standby power is in the off state (in a state in which the AC power is not inputted). (S1). In such a case, is the PC power switch "on"? The power control signal PWR_CTRL (PWR_CTRL) is set to the power control signal PWR_CTRL (step S2). If the power control signal PWR_CTRL The switching unit 40 sends the power output signal PWR_OUT to the 5V SB terminal of the mainboard so that all the power is supplied to the main board S3). At the same time, the power button # 13 is activated and the PS_ON # signal is activated to operate the main board (S4 ').

That is, the microcomputer 30 receives a signal that the PC power switch is 'on', activates the power control signal PWR_CTRL to the first switching unit 40, and outputs the power output signal PWR_OUT) to the 5V SB terminal of the main board to supply all the power to the main board (S3) and to output the switching-out signal (SW_OUT) to another second switching unit 41 The transistor Q2 of the second switching unit 41 is turned on and the PS_ON # signal is applied to the power button 13 of the main board so that the power button 13 and the super I / The PS_ON # terminal of the connector 60 is activated through the PS_ON circuit 19a of the controller 19 to operate the main board (S4 ').

Thereafter, the voltage V _DD supplied to the memory 10a of the main board is checked (S5), and it is determined whether it is less than a predetermined voltage (for example, 0.7 V) (S6). If the voltage is abnormal ), The 5V SB power 'on' state is maintained and power supply to the main board is continued. Otherwise, the memory is considered to have stopped operating, and the power control signal PWR_CTRL is deactivated, The switching unit 40 disables the power output signal PWR_OUT and turns off the system standby power in step S7.

That is, as described above in the related art, the + 5V SB should not be turned off in the S3 mode (power saving / standby mode), while in the S4 mode (the maximum power saving mode) Turn off all power. That is, in the S4 mode and the S5 mode in which the power is OFF, 0V is output. In other words, the VDD signal is 0 V in the OFF state of the system standby power and in the case of the S4 mode, and the system operation which is the standby power ON condition (Power ON state) and S3 (power saving / standby mode), the VDD signal outputs 1.2 to 1.5V. Therefore, in S5 and S6, the voltage V _DD supplied to the memory is checked (S5), and it is determined whether or not it is less than a predetermined voltage (Vr: 0.7 V, for example) The power 'on' state is maintained, and less than (V _DD ≪ Vr), the system standby power is turned off (S7).

The fourth prior art recognizes the S3 and S4 modes by a relatively simple method of checking the voltage (V _DD ) supplied to the memory and continues to supply the 5V standby power in the S3 mode, In the S4 mode, the standby power is cut off to save power in the dash mode. However, there is an advantage that it can be performed without additional cable construction.

However, in S3 (standby / power saving mode), in addition to the specific mode, there is no need to supply standby power of 5 V, and only standby power of about 3 V is sufficient.

In addition, in the above-mentioned conventional techniques, since the mode recognition such as S3 and S4 is checked with a voltage in a secondary device such as a memory, a separate device for checking the mode is necessary. In addition, In addition, although there is a very low possibility of wiring to the microcomputer, there is a problem that the system can not accurately sense the inconsistency between the secondary device such as the current mode and the memory due to the error of the system. Mode, even if the memory and the like have to be supplied with a minimum amount of power, the countermeasures against it are insufficient.

Korean Patent Publication No. 2013-0043923 (Patent Application No. 2011-0108115) Korea Patent No. 1328393 (name: computer power supply device for saving standby power) Korean Patent No. 1623756 (Title: Standby power cutoff method of standby power cutoff device using system memory power)

The present invention provides a 5VSB power supply for circuit operation only in normal operation, in a computer system having various operation modes (for example, S0 to S5 mode) And the other driving is to use 1.2V to minimize the power consumption. However, it is realized by only one switching element, and the energy saving of the computer system using the control signal of MPSC which enables the sleep mode recognition and the 5VSB interruption by software Apparatus and method.

On the other hand, in the conventional technology using VDDQ, a transistor turned off when the voltage is lower than a specific voltage or a current flowing through the terminal is measured to check the power state. However, since the voltage flowing in the VDDQ is getting lower recently, it is not easy to unify the parts when using the transistor. In case of measuring the current, it is necessary to increase the capacity by using the pre-amp so that the measurement value can be accurately recognized. I have possession.

Thus, according to the present invention, through the VTT and VDDQ control signals output from the MPSC In addition to the standby power flowing into the system while sensing accurately, it is possible to save energy by stably supplying 1.2V to the memory while shutting off the 5VSB power even in the sleep mode. In order to support this technology, the technology can be implemented at a low cost by using a microcomputer for simple switching. Also, MPSC has an advantage that it can easily interface with the outside by connecting it to 'PCB artwork'.

According to one aspect of the present invention, there is provided an energy saving apparatus for a computer system using a control signal of an MPSC, including a CPU 11, an SIO 19, a chipset 14, memories 10a and 10a ' And an MPSC (17) for controlling the power supply of the memory, an SMPS (20) connected to the main board through an ATX power connector (16), and an MPSC The power supply of the 5VSB standby power to the ATX power connector 16 of the SMPS 20 is cut off and the memory 10a or 10a 'of the main board is turned off in the sleep mode, And the lowest voltage supplier 50 determines whether the lowest voltage supplier 50 is in the sleep mode or not based on the MPSC control signal, Supply of the 5VSB standby power supply to the ATX power connector 16 When the switching element 52 interrupts the supply of the 5VSB standby power supply to the ATX power connector 16 in the sleep mode, the 5VSB standby power supply is switched to the memory 10a, And a control unit 51 for controlling the switching device 52 and the converter 53 using the control signal of the MPSC. The control unit 51 controls the switching unit 52, And receives the control signals VTT_C and VDDQ_C of the MPSC from the MPSC 17 and outputs an output control signal to the switching device 52 and the converter 53. The register manager 10c ') Is configured to deactivate the' G1 register group ', which is a delay register at boot time, to suspend the boot delay operation which is not necessarily required at boot time, Child under politics In mode, is characterized in that so as to disable the 'G3 register group "is unnecessary register at a particular time does not use the register of' G2 register group, and the idle mode while, to reduce the energy system of the computer.

delete

Preferably, the controller 51 is a PIC 51.

delete

According to another aspect of the present invention, there is provided an energy saving method of a computer system using a control signal of an MPSC, comprising the steps of: (a) When the computer system is turned on (S11), the control unit 51 turns on the switching device 52 to supply 5VSB standby power to the entire system, (S12) of supplying all the operation power sources (3V, 5V, 12V, etc.) to the various devices in the step S12; (c) checking the control signal (VTT_C, VDDQ_C) of the MPSC to determine whether it is in an operation mode (S13); (e) checking whether the sleep mode is set as the control signal (VTT_C, VDDQ_C) of the MPSC as a result of the determination in step (c); (f) If it is determined in the step (e) that the sleep mode (S3 mode), the switch (52) for determining whether the 5VSB is supplied (S15) The second output control signal VDDQ_ON for turning on the operation of the converter 53 for supplying the lowest voltage to the memory while the 5VSB is blocked by issuing the first output control signal VSB_CTRL # Causing a voltage to be supplied to the memory (10a, 10a ') (S16); (g) After the step (f), it is determined whether or not the wakeup operation is performed (S17). If the wakeup does not occur, the wakeup operation is continuously performed. A step S18 of issuing a second output control signal VDDQ_ON for turning off the operation of the converter 53 by causing the signal VSB_CTRL # to be supplied so that the 5VSB is supplied so that the lowest voltage is cut off; (h) determining (S21) whether the control signal (VTT_C, VDDQ_C) of the MPSC is in the off mode if it is determined in the step (e) that the sleep mode is not the S3 mode. And (j) if it is determined in step (h) that the off mode is selected, the PS_ON # is set to 'H' to shut off all power supply (S22) (Step S23) of issuing a second output control signal (VDDQ_ON), which turns off the operation of the converter 53, while also causing the 5VSB supply to be stopped by issuing the output control signal VSB_CTRL # ); And a control unit.

Preferably, the step (S13) of determining whether or not the operation mode is the operation mode in the step (c) includes: when the VTT control signal VTT_C and the VDDQ control signal VDDQ_C are among the control signals VTT_C and VDDQ_C of the MPSC (S14) whether the sleep mode is the sleep mode in the step (e) is determined by determining whether the VTT control signal VTT_C is 'L' and the VDDQ control signal (VDDQ_C) is 'H' (S21) whether the VTT control signal (VTT_C) and the VDDQ control signal (VDDQ_C) are both 'L' or not is determined to be 'H' .

Also, preferably, (b) between the step (a) and the step (c), the register manager 10c 'deactivates the' G1 register group ', which is a register delayed at boot time, (S30) suspending a boot delay operation; (d) If it is determined in operation (c) that the operation mode is determined, the CPU usage is checked to check whether the CPU usage is less than a predetermined level (S31). If the CPU usage is above a certain level, Returning to step (e); and if it is less than a predetermined level, performing energy use optimization and proceeding to step (e); And (k) restoring the energy usage optimization in steps (b) and (d) to a normal state as a result of the determination in step (h) (S33 to S35); And further comprising:

More preferably, the optimization of the energy usage in the step (d) is performed by using the 'G2 register group', which is a register that the register manager 10c 'does not use for a specific time, and the' G3 register group ', which is an unnecessary register in the idle mode (K1), if it is determined in step (h) that the device is not in the off mode, the step (k) (S33) and (k2) step (k1) of checking whether a specific register corresponding to the G1 to G3 is called by the application register after the step (k1) (S34 If the register manager 10c 'has not been called as a result of the determination in the step (k2), the register manager 10c' activates the corresponding register and then proceeds to step (c) (Step S35).

According to the energy saving apparatus and method of the computer system using the control signal of the MPSC according to the present invention, in a computer system having various operation modes, energy consumption can be reduced by minimizing the operation power in the standby power mode using the minimum component Furthermore, it is possible to optimize standby power by operating only the devices that are absolutely required even during operation.

Other objects and advantages of the present invention will become apparent from the detailed description of the embodiments with reference to the attached drawings.

1 is a conceptual diagram of a conventional computer power supply;
2 is a block diagram of a computer power supply in which standby power is reduced according to the third prior art.
3 is a view for explaining a concept of a conventional general power-on operation;
4 is a block diagram of the PS_ON circuit 19a of Fig.
5 is a timing chart of the signals of FIG. 3;
FIG. 6 is another example of a concept of a conventional general power-on operation; FIG.
FIG. 7 is a timing chart of the signals of FIG. 6; FIG.
FIG. 8 is a block diagram of a computer power supply in which standby power is reduced according to a fourth prior art; FIG.
FIG. 9 is a detailed circuit diagram of a computer power supply apparatus in which standby power is reduced according to a fourth prior art; FIG.
FIG. 10 is a flowchart illustrating an operation of a microcomputer of a computer power supply apparatus according to a fourth prior art in which standby power is reduced. FIG.
11 is an overall schematic configuration view of a computer system according to a preferred embodiment of the present invention;
Figure 12a is a detailed circuit diagram of the power supply (SMPS) and MPSC portion of Figure 11;
12B is a detailed circuit diagram of the main board portion of FIG.
13 is an operational flowchart showing a method of operating a computer system according to the first embodiment of the present invention.
14 is a flowchart illustrating an operation method of a computer system according to a second embodiment of the present invention;

Hereinafter, preferred embodiments according to the present invention will be described in detail with reference to the accompanying drawings.

FIG. 12 is a detailed circuit diagram of the power supply (SMPS) and the MPSC portion of FIG. 11, FIG. 12B is a detailed circuit diagram of the main board portion of FIG. 11 FIG. 13 is a flowchart illustrating an operation method of a computer system according to the first embodiment of the present invention, and FIG. 14 is a flowchart illustrating an operation method of a computer system according to the second embodiment of the present invention.

It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the invention, You will know.

(A standby power optimizing apparatus of a computer system according to a preferred embodiment of the present invention)

First, an energy saving apparatus for a computer system using a control signal of the MPSC according to the best mode of the present invention will be described with reference to FIGS. 11 to 12B.

11, a minimum voltage supply unit 50 is interposed between a main board 10 and a power supply (SMPS) 20 so that a voltage of at least S3 mode (sleep mode) , The 5VSB voltage to the main board is cut off and the lowest voltage (for example, 12V, for example, 1.5 to 1.9V depending on the computer system) is supplied only to the memories 10a and 10a 'in the S3 mode (sleep mode).

That is, the switching element 52 for turning on / off the application of the first standby power supply of the normal standby voltage (5VSB) from the SMPS 20 to the ATX power connector 16 of the main board is connected to a separate PIC 51 . At this time, the switching device 52 is turned off in the PIC 51, the sleep mode (S3 mode) or the above modes (S4 and S5 modes), so that a normal standby power is not applied to the ATX power connector 16 , It is possible to save energy (approximately 1.2 W) consumed in the sleep mode (S3 mode) in particular. However, in the sleep mode (S3 mode), for example, the memory 10a or 10a 'like the DDR does not have a problem in the maximum power saving mode (S4 mode) or the off mode (S5 mode) (Using the lowest voltage of 1.2V to 1.9V), the 5VSB is lowered to the lowest voltage through the converter 53 and directly applied to the memories 10a and 10a '.

In this case, only the 5VSB terminal is connected to the lowest voltage supply unit 50, and the remaining various power sources (5V, 3.3V, 12V, etc.) are connected to the main connector and are commonly grounded. By the mode recognition of the current computer system by applying to the PIC 51 the VTT control signal VTT_C and the VDDQ control signal VDDQ_C received from the chipset 14 by the MPSC 17 in the main board 10. [

At this time, the PIC 51 recognizes the mode of the current computer system by the VTT control signal VTT_C and the VDDQ control signal VDDQ_C, and the truth table thereof is shown in Table 1 below.

<Table 1>

That is, when the VTT control signal VTT_C and the VDDQ control signal VDDQ_C are all at "H" (high), the PIC 51 recognized as the computer operation state (S0 to S2 mode) The 5VSB is supplied to the main board through the ATX power connector 16 by making the control signal VSB_CTRL # that turns on the switching element 52 that determines the ON state of the switching element 52 to 'L' (low) Since all voltages are applied to the main board 10 through the ATX power connector 16 as in the mode, an operating voltage is applied to the memory, so it is not necessary to separately apply the lowest voltage (1.2 V) for the memory, The converter control signal VDDQ_ON for turning on the operation of the converter 53 may be set to the "Off" state. More specifically, the terminal of the converter control signal VDDQ_ON is short-circuited with the ground, so that the output terminal of the converter is grounded.

On the other hand, when the VTT control signal VTT_C is 'L' but the VDDQ control signal VDDQ_C is 'H', the PIC 51 recognized as the sleep mode (S3 mode) determines whether 5 VSB is supplied The control signal VDDQ_ON for turning on the operation of the converter 53 is set to 'On' so that the 5VSB is cut off by setting the control signal VSB_CTRL # to turn off the switching element 52 to 'H' So that the voltage (voltage of 1.2V) is still supplied to the memory 10a, 10a '. More specifically, the converter control signal (VDDQ_ON) is grounded and open (floating) so that the operating voltage is applied to the control terminal of the converter 53 to perform the converting operation of the converter. So that the lowest voltage (1.2 V) is applied to the memory.

On the other hand, when both the VTT control signal VTT_C and the VDDQ control signal VDDQ_C are 'L', the PIC 51 recognized as the maximum power saving mode (S4 mode) to the computer power off state (S5 mode) , A control signal (VDDQ_ON) for turning on the operation of the converter (53) while turning off the switching element (52) for determining whether the 5VSB is to be supplied is set to 'H' ) Is also set to 'Off' so that the lowest voltage (voltage of 1.2V) is not supplied to the memories 10a and 10a '.

The PIC 51 is activated by receiving the power button 13 signal of the main board through the 'PWR_BTN #' terminal, and the 'VDDQ_ON' control signal is set to the OFF state of the internal switch interposed between the ground The output terminal of the converter is floated while the converting operation of the converter is performed, and the reference numeral 54 is a load added to the converter 53 together with the resistor and the capacitor.

The SMPS 20 and the MPSC 17 will now be described in detail. As shown in FIG. 12A (which is also described in detail in the specification of Japanese Patent No. 1640584 of the present invention), the first Various operating voltages (+5 V, +3.3 V and +12 V) from the transformer T1 are supplied to the main board through the ATX power connector 16 while the second transformer T2 and the voltage regulator 29 The 5VSB voltage from the ATX power connector 16 is supplied to the '5VSB' terminal of the ATX power connector 16 through the switching element 52 so that the switching element 52 is turned off, The main power supply to the main board including the dash power supply 5VSB is cut off, so that the power of about 1.2W is saved even in the sleep mode. However, in the sleep mode (S3 mode), minimum power must be supplied to the same memory (10a, 10a 'in FIG. 12B) as the DDR memory. The standby power source 5VSB is supplied with the lowest voltage 1.2V) and supplied to the memory, and these switching elements 52 and the converter 53 are again controlled by the PIC 51. [

In addition, the PIC 51 is controlled by the control signals 'VTT_C' and 'VDDQ_C' from the MPSC 17, which is a signal from the chipset (14 in FIG. 12B).

12B, the remaining configuration of the main board 10 will be described. When the SIO 19 is activated by switching the power button 13, the PIC 51 of the lowest voltage supply unit 50 is also activated It is necessary to check the operation of the keyboard or the mouse and to monitor the I / O device with the chipset 14 in the sleep mode or other boot mode. When the wakeup or other operation mode is changed, 5VSB standby power must be applied to the system.

Meanwhile, the CPU 11 interfaces with the HDMI connector through the 'Port B' and the 'Port C', and is connected to the LVDS connector through the 'Port D' to exchange information with the LVDS devices . Furthermore, the CPU 11 is also connected to an electronic data processing (eDP) apparatus 35 via a 'port E', and on the other hand, the DDR memories 10a and 10a ').

In addition, the chipset 14 is connected to the LAN and PCIe devices in a PCIe manner and is connected to the keyboard and mouse in PS2 or USB manner and is also connected to USB, SPI flash and serial ATA cables such as SATA3 . The chipset 14 is also connected to a watchdog, a fan, a communication module, a hardware monitor, a DIO, and a KB / MS via a hardware monitoring device.

On the other hand, the standby power source of 5VSB is turned on / off by the switching element 52 as described above, and is supplied as AVDD to the audio codec and audio amplifier of the entire system.

In addition, the standby power of the 5VSB may be supplied to the AVDD 33 via an interface such as USB 3.0, USB 2.0, SPI flash, a LAN connector such as an RJ-45, or a PCIe, after being depressed to 3VSB by a separate converter However, since it is not directly related to the present invention, detailed description will be omitted. In addition, a TPM, an audio codec, an audio input / output device, an audio amplifier, a speaker, and the like can be connected to the main board.

In particular, in the system of the present invention, the CPU 11 and the chipset 14 are designed to perform additional standby power optimization in the sleep mode in a manner programmed by the OS 10c according to the execution of the register manager 10c ' This will be described later with reference to Fig. 14 as a second embodiment.

According to the energy saving apparatus of the computer system using the control signal of the MPSC according to the present invention, a standby power minimizing method is provided by the simple switching device 52, and the added cost is minimized As a method of energy saving in the system standby mode, only the minimum voltage (1.2 V) of the memory power supply is supplied to the memory, and power to all the main power sources can be shut down even in the sleep mode. Because the time is reduced to smart phones, etc., it is optimized for power consumption reduction such as reduction of standby power interruption and energy consumption of sleep mode (S3). In addition, the performance of computers compared to the programs used for general office use is very high, and the multi-PCs that are used by multiple users on one computer share this performance, and the tendency to utilize the idle resources of the computers, And application programs. In addition, when a problem occurs in installing a program by a user or a problem with a virus, etc., the whole system is down or infected and there are many problems in usage. This reduces energy consumption by reducing the number of CPU cores or by turning off unused interfaces, depending on the program load you are using.

For example, there are 'Windows update', 'VACCINE', and 'SECURITY' related registers as registers that are delayed at boot time (hereinafter referred to as 'G1 register group' for convenience) 'Is disabled. Also, in the idle mode (IDLE mode) in which the CPU usage is equal to or less than a predetermined value even in the operation mode, a register that is not used for a specific time (hereinafter referred to as a 'G2 register group' G2 register group 'is temporarily disabled in the idle mode such as sleep mode, and in the idle mode, an unnecessary register (referred to as' G3 register group' in this specification) Network processor ',' Windows Service management ', etc., and also disable these' G3 register group 'in idle mode such as sleep mode. Also in the idle mode, it is preferable to turn off the network adapter.

Of course, when the sleep mode is cleared by checking the current operation state of the computer periodically, it is necessary to check whether all of the children are released. Once the network adapter is turned on, a specific register corresponding to G1 to G3 , It is called and it is necessary to activate the corresponding 'Z register'.

(A method for optimizing standby power of a computer system according to the first embodiment of the present invention)

Now, an energy saving method of the computer system using the control signal of the MPSC according to the first embodiment of the present invention will be described with reference mainly to FIG.

13, when the user presses the power button 13 to turn on the power and the computer system is started (S11), the PIC 51 in the present invention is also activated The switching element 52 is turned on by setting the signal VSB_CTRL # to "L", thereby supplying standby power to the entire system and setting the PS_ON # signal to "L" (3V, 5V, 12V, and the like) to the various devices at step S12.

The PIC 51 checks the VTT control signal VTT_C and the VDDQ control signal VDDQ_C, which are control signals of the MPSC. When the VTT control signal VTT_C and the VDDQ control signal VDDQ_C are both 'H (S0 to S2 mode), and if not, it is checked whether or not the sleep mode is set. In other words, the VTT control signal (VTT_C) is 'L' and the VDDQ control signal (VDDQ_C) is 'H' (S14).

If the result of the determination in step S14 is 'Yes', it indicates the entry into the sleep mode (S3 mode), so that 'STR (Suspend to RAM)' for storing the current state in the RAM is performed (S15) (S3 mode), the control signal (VSB_CTRL #) for turning off the switching element 52 for determining whether or not the 5VSB is supplied is set to 'H' so that the 5VSB is blocked. However, The control signal VDDQ_ON for turning on the operation of the switch 53 is set to On so that the lowest voltage (voltage of 1.2V) is supplied to the memories 10a and 10a '(S16). That is, in the present invention, the operation of all elements except the memory in the sleep mode is stopped.

If the wake-up occurs, the control signal VSB_CTRL # for turning off the switching element 52 is set to "L" (step S17). If the wake- The control signal VDDQ_ON for turning on the operation of the converter 53 is set to 'Off' (ground and short) so that the lowest voltage (voltage of 1.2V) is blocked (S18). Thereafter, the process returns to step S13, and the process is repeated.

If it is determined as NO in step S14, it is determined whether the VTT control signal VTT_C and the VDDQ control signal VDDQ_C are all L in step S21. Otherwise, In this case, since the power saving mode (S4 mode) or the power off mode (S5), PS_ON # is set to 'H' to cut off all power supply (S22 , The control signal VDDQ_ON for turning on the operation of the converter 53 is also set to 'Off' while the control signal VSB_CTRL # for turning off the switching device 52 is set to 'H' (Ground and short), so that the lowest voltage (voltage of 1.2V) is also cut off (S23), and the process is terminated (S24).

Therefore, as shown in Table 1, in the operation mode S0 to S2, the switching device 52 is turned on so that the 5VSB is applied to the main board through the power connector. In the sleep mode S3, The switching device 52 is turned off so that the 5VSB is blocked so that the lowest voltage output of the converter 53 is supplied only to the memories 10a and 10a ' The power supply is cut off and the standby power supply in the sleep mode is minimized with a very simple configuration using the existing MPSC control signal.

(A method for optimizing standby power of a computer system according to a second embodiment of the present invention)

Now, an energy saving method of the computer system using the control signal of the MPSC according to the second embodiment of the present invention will be described with reference mainly to Fig.

14, in step S12, the register manager 10c 'deactivates the' G1 register group ', which is a register delayed at boot time, so that it is not necessary at boot The operation for delaying the boot is temporarily stopped (S30), and then the operation S13 is performed.

If the result of the determination in step S13 is "Yes" (in the case of the operation mode), the SIO 19 checks whether or not the mode is the idle mode, thereby saving energy. In other words, And checks whether or not the CPU usage amount is less than a certain level (for example, 5 to 10%) (S31). If the CPU usage amount is not less than a predetermined level, the process returns to step S13 and is repeatedly performed. , The energy usage optimization is executed (S32). Specifically, in step S32, the register manager 10c 'deactivates the' G2 register group 'which is a register which is not used for a specific time and the' G3 register group 'which is an unnecessary register in the idle mode, and sets' DeviceSleepONDisconnect = 0' The network adapter is turned off (S32), and the above step S14 is performed.

Thus, according to the second embodiment, compared to the first embodiment, more energy can be saved in the boot mode or the idle mode.

If the result of the determination in step S21 is 'No' (operation mode) after step S21, the register manager and the network adapter must be returned to the original state without returning immediately. First, 'DeviceSleepONDisconnect = 1' After the network adapter is turned on (S33), the application register checks whether a specific register corresponding to G1 to G3 (called 'Z register' in this specification) has been called (S34). If it is not called, The register manager 10c 'activates the corresponding' Z register '(S35), and returns to the step S13.

According to the energy saving apparatus and method of the computer system using the control signal of the MPSC according to the present invention, i) the addition of a very simple switching device 52 using the control signal of the MPSC (the PIC is separately used in the embodiment , It is possible to easily configure it in other manners as long as the logical value of Table 1 is realized), the standby power of 5VSB is effectively stopped in the sleep mode of the computer system to reduce the power consumption (About 1.2W to 0.3W, about 0.9W can be saved), ii) the supply of the lowest voltage (1.2V) to the memory by the converter 53 is still possible, It can be realized without. iii) Furthermore, in the case of the second embodiment, additional energy saving is possible by further suspending additional operations by the register manager in boot mode or idle mode.

While the present invention has been described in connection with what is presently considered to be practical exemplary embodiments, it is to be understood that the invention is not limited to the disclosed embodiments, but, on the contrary, Of course.

(Prior art)
10: Motherboard
11: CPU 12: SIO (System IO)
13: Power button 14: Chipset
15: reset button 16: first battery
17: RESET RESET 18: LAN
19: Super IO (Super IO) 19a: PS_ON circuit
20: Power supply (SMPS) 30: Microcomputer
40: first switching unit 41: second switching unit
50: Case power switch 60: Power connector
70: V _DD sensing unit
(Invention)
10: main board 10a, 10a ': memory
10c: OS 10c ': Register manager (REG_MAN)
11: CPU
13: Power button 14: Chipset
16: ATX power connector 17: MPSC
19: SIO
20: Power Supply (SMPS) 29: Voltage Regulator
50: lowest voltage supply unit 51: PIC
52: switching element 53: converter

Claims (8)

A main board 10 including a CPU 11, an SIO 19, a chipset 14, memories 10a and 10a 'and an MPSC 17 for controlling the power supply of the memory, an ATX power connector 16 An SMPS 20 connected to the main board through a plurality of peripheral devices, and an MPSC control signal including various peripheral devices,
In the sleep mode, the lowest voltage supply unit 50 that cuts off the supply of the 5VSB standby power supply to the ATX power connector 16 of the SMPS 20 and supplies the lowest voltage to the memories 10a and 10a ' Including,
The determination as to whether the lowest voltage supply unit 50 is in the sleep mode is performed by the control signal of the MPSC,
The lowest voltage supply unit (50)
A switching element 52 for switching whether the 5VSB standby power is supplied to the ATX power connector 16,
Converter 53 for converting the 5VSB standby power supply to supply the 5VSB standby power to the memory 10a or 10a 'when the switching device 52 interrupts the supply of 5VSB standby power to the ATX power connector 16 in the sleep mode, Wow,
And a control unit 51 for controlling the switching device 52 and the converter 53 using a control signal of the MPSC,
The control unit 51 receives a control signal VTT_C and VDDQ_C of the MPSC from the MPSC 17 and outputs an output control signal to the switching device 52 and the converter 53,
The register manager 10c 'of the main board 10 deactivates the' G1 register group ', which is a register delayed at boot time, to suspend the boot delay operation which is not necessarily required at boot time The G2 register group which is not used for a specific period of time and the G3 register group which is an unnecessary register in the idle mode are deactivated in the idle mode in which the CPU usage is equal to or less than a predetermined value even in the sleep mode, Energy saving of the computer system using the control signal of the MPSC. delete The method according to claim 1,
Wherein the control unit (51) is a PIC (51). delete A main board 10 including a CPU 11, an SIO 19, a chipset 14, memories 10a and 10a 'and an MPSC 17 for controlling the power supply of the memory, an ATX power connector 16 The SMPS 20 is connected to the main board through the ATX power connector 16 of the SMPS 20, and various peripheral devices. In the sleep mode, the ATX power connector 16 And a lowest voltage supply unit 50 for shutting off the supply of the 5VSB standby power supply to the memory 10a and 10a 'of the main board, wherein the lowest voltage supply unit 50 is in the sleep mode The lowest voltage supply unit 50 includes a switching element 52 for switching whether the 5VSB standby power supply is supplied to the ATX power connector 16, The switching element 52 is connected to the ATX power connector 16 of the 5VSB standby power supply A converter 53 for converting the 5VSB standby power supply to the memory 10a or 10a 'when the 5VSB standby power is cut off, and a converter 53 for controlling the switching element 52 and the converter 53 using the control signal of the MPSC The control unit 51 receives the control signals VTT_C and VDDQ_C of the MPSC from the MPSC 17 and outputs the control signals VTT_C and VDDQ_C to the switching device 52 and the converter 53 A method for energy saving of a computer system using an MPSC control signal using an energy saving device of a computer system using a control signal of an MPSC for generating an output control signal,
(a) When the power is turned on and the computer system is started (S11), the controller 51 turns on the switching device 52 to supply 5VSB standby power to the entire system, and the ATX power connector 16 (S12) of supplying all the operation power sources (3V, 5V, 12V, etc.) to the various devices on the main board through the I /
(c) checking the control signal (VTT_C, VDDQ_C) of the MPSC to determine whether it is in an operation mode (S13);
(e) checking whether the sleep mode is set as the control signal (VTT_C, VDDQ_C) of the MPSC as a result of the determination in step (c);
(f) If it is determined in the step (e) that the sleep mode (S3 mode), the switch (52) for determining whether the 5VSB is supplied (S15) The second output control signal VDDQ_ON for turning on the operation of the converter 53 for supplying the lowest voltage to the memory while the 5VSB is blocked by issuing the first output control signal VSB_CTRL # Causing a voltage to be supplied to the memory (10a, 10a ') (S16);
(g) After the step (f), it is determined whether or not the wakeup operation is performed (S17). If the wakeup does not occur, the wakeup operation is continuously performed. A step S18 of issuing a second output control signal VDDQ_ON for turning off the operation of the converter 53 by causing the signal VSB_CTRL # to be supplied so that the 5VSB is supplied so that the lowest voltage is cut off;
(h) determining (S21) whether the control signal (VTT_C, VDDQ_C) of the MPSC is in the off mode if it is determined in the step (e) that the sleep mode is not the S3 mode. And
(j) If it is determined in step (h) that the off mode is selected, the PS_ON # is set to 'H' to shut off all power supply (S22) (S23) by issuing a second output control signal (VDDQ_ON), which turns off the operation of the converter (53) while blocking the 5VSB supply by issuing the control signal (VSB_CTRL #), ;
And a control signal of the MPSC. 6. The method of claim 5,
The step (S13) of determining whether the operation mode is the operation mode in the step (c) includes: if the VTT control signal VTT_C and the VDDQ control signal VDDQ_C are all 'H' out of the MPSC control signals VTT_C and VDDQ_C, , &Lt; / RTI &gt;
The step S14 of checking whether the sleep mode is the sleep mode in the step (e) is determined whether the VTT control signal VTT_C is 'L' and the VDDQ control signal VDDQ_C is 'H'
The MPSC determines whether the VTT control signal (VTT_C) and the VDDQ control signal (VDDQ_C) are both 'L' in step (S21) (METHOD OF ENERGY SAVING OF COMPUTER SYSTEM USING CONTROL SIGNAL) 6. The method of claim 5,
(b) Between step (a) and step (c), the register manager 10c 'deactivates the' G1 register group ', which is a register delayed at boot time, so as to delay booting Suspending operation (S30);
(d) If it is determined in operation (c) that the operation mode is determined, the CPU usage is checked to check whether the CPU usage is less than a predetermined level (S31). If the CPU usage is above a certain level, Returning to step (e); and if it is less than a predetermined level, performing energy use optimization and proceeding to step (e); And
(k) restoring the energy use optimization in the steps (b) and (d) to a normal state and returning to the step (c) if it is determined in step (h) Steps S33 to S35;
Further comprising the steps of: receiving a control signal from the MPSC; 8. The method of claim 7,
The optimization of the energy usage in the step (d) may be performed such that the register manager 10c 'deactivates the' G2 register group 'which is a register that is not used for a specific time and the' G3 register group 'which is an unnecessary register in the idle mode, &Quot; DeviceSleepONDisconnect = 0 &quot; to turn off the network adapter (S32)
The step (k)
(k1) a step (S33) of turning on the network adapter by setting 'DeviceSleepONDisconnect = 1' when it is not the off mode as a result of the judgment in the step (h)
(k2) after the step (k1), checking whether a specific register corresponding to the G1 to G3 is called by the application register (S34)
(k3) If it is not called as a result of the determination in the step (k2), the register manager 10c 'activates the corresponding register and then returns to the step (c)
And a control signal of the MPSC.

Images