CN111741518A - WiFi chip circuit and WiFi device - Google Patents
WiFi chip circuit and WiFi device Download PDFInfo
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04W—WIRELESS COMMUNICATION NETWORKS
- H04W52/00—Power management, e.g. TPC [Transmission Power Control], power saving or power classes
- H04W52/02—Power saving arrangements
- H04W52/0209—Power saving arrangements in terminal devices
- H04W52/0261—Power saving arrangements in terminal devices managing power supply demand, e.g. depending on battery level
- H04W52/0274—Power saving arrangements in terminal devices managing power supply demand, e.g. depending on battery level by switching on or off the equipment or parts thereof
- H04W52/028—Power saving arrangements in terminal devices managing power supply demand, e.g. depending on battery level by switching on or off the equipment or parts thereof switching on or off only a part of the equipment circuit blocks
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
- H04B1/38—Transceivers, i.e. devices in which transmitter and receiver form a structural unit and in which at least one part is used for functions of transmitting and receiving
- H04B1/40—Circuits
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D30/00—Reducing energy consumption in communication networks
- Y02D30/70—Reducing energy consumption in communication networks in wireless communication networks
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Abstract
The application discloses wiFi chip circuit includes: the system comprises a PMU module and an SOC module powered by the PMU module; the AON unit in the SOC module is always in a power supply state and used for generating a power-off instruction of a corresponding level according to the power consumption strategy instruction and sending the power-off instruction to the PMU module, so that the PMU module stops supplying power to the corresponding power unit in the SOC module according to the power-off instruction. In the application, the permanently powered AON unit is used for controlling the PMU module to stop supplying power to different power utilization units, so that power failure of corresponding levels in different power consumption strategies is realized, the aim of dynamically adjusting the low power consumption strategy is fulfilled, and higher flexibility is realized; meanwhile, the PMU module supplies power to different power utilization units respectively, so that the possibility of hanging up buses of all the power utilization units in the chip is reduced, and the reliability of the WiFi chip circuit in dormancy and awakening is improved. The application also correspondingly discloses a WiFi device with the same beneficial effect.
Description
Technical Field
The invention relates to the field of chip design, in particular to a WiFi chip circuit and a WiFi device.
Background
The low power consumption design is a necessary requirement of the current chip design, the common low power consumption scheme usually achieves the purpose of low power consumption through PMU (power management unit) and clock gate technologies, although the effect of low power consumption dormancy can be achieved, dynamic adjustment cannot be performed according to different use scenes, the flexibility is low, once the bus is not well processed in the process of dormancy and awakening, the chip bus is probably hung, and data recovery fails in the awakening process.
Therefore, how to provide a solution to the above technical problems is a problem to be solved by those skilled in the art.
Disclosure of Invention
In view of the above, the present invention provides a WiFi chip circuit and a WiFi device. The specific scheme is as follows:
a WiFi chip circuit comprising: the system comprises a PMU module and an SOC module powered by the PMU module;
the system comprises an SOC module and a Power Management Unit (PMU), wherein an AON unit in the SOC module is always in a power supply state and is used for generating a power failure instruction of a corresponding level according to a power consumption strategy instruction and sending the power failure instruction to the PMU module so that the PMU module stops supplying power to a corresponding power unit in the SOC module according to the power failure instruction.
Preferably, the AON unit includes a sleep control circuit, a backup circuit, and a reset circuit, wherein:
before generating a power-off instruction of a corresponding level according to the power consumption strategy instruction and sending the power-off instruction to the PMU module, the sleep control circuit generates a backup instruction according to the power consumption strategy instruction and sends the backup instruction to a backup circuit;
the backup circuit respectively performs data backup on the corresponding power utilization units according to the backup instruction, and sends feedback information to the sleep control circuit after the data backup is finished;
after receiving the feedback information, the sleep control circuit sends a first enabling signal with isolated power to the reset circuit;
the reset circuit sets the corresponding power utilization unit to be in a reset state according to the first enabling signal.
Preferably, the backup circuit includes:
the instruction fetching subunit is used for fetching a microcode command from the buffer according to the backup instruction;
an ALU subunit, configured to parse the microcode command;
and the data action subunit is used for moving the data in the buffer according to the analyzed microcode command.
Preferably, the power consumption policy instruction includes: an active state power consumption instruction, and/or a WiFi sleep instruction, and/or a clock sleep instruction, and/or a light sleep instruction, and/or a deep sleep instruction.
Preferably, the power consumption policy instruction specifically includes:
and the CPU generates and sends the power consumption strategy instruction to the AON unit according to the internal state of the WiFi chip circuit.
Preferably, the AON unit is further configured to:
and generating a power supply instruction of a corresponding level according to the awakening instruction and sending the power supply instruction to the PMU module so that the PMU module supplies power to a corresponding power utilization unit in the SOC module according to the awakening instruction.
Preferably, the wake-up instruction is specifically a sleep interrupt signal sent by the RTC circuit in the WiFi, the CPU, the peripheral interface, or the AON unit.
Preferably, the AON unit includes a wake-up interrupt circuit, a sleep control circuit, a backup circuit, and a reset circuit, wherein:
the wake-up interrupt circuit generates a corresponding power supply instruction according to the wake-up instruction and sends the power supply instruction to the sleep control circuit;
the sleep control circuit enables the PMU module according to the power supply instruction so that the PMU module supplies power to a corresponding power utilization unit in the SOC module according to the power supply instruction;
when the reset circuit receives a PLL LOCK signal of an ANA PLL unit in the SOC module, the reset circuit releases the reset signal of the SOC module, and the backup circuit restores backup data to a corresponding power utilization unit.
Correspondingly, the application also discloses a WiFi device, which comprises the WiFi chip circuit.
The application discloses wiFi chip circuit includes: the system comprises a PMU module and an SOC module powered by the PMU module; the system comprises an SOC module and a Power Management Unit (PMU), wherein an AON unit in the SOC module is always in a power supply state and is used for generating a power failure instruction of a corresponding level according to a power consumption strategy instruction and sending the power failure instruction to the PMU module so that the PMU module stops supplying power to a corresponding power unit in the SOC module according to the power failure instruction. In the application, the permanently powered AON unit is used for controlling the PMU module to stop supplying power to different power utilization units, so that power failure of corresponding levels in different power consumption strategies is realized, the aim of dynamically adjusting the low power consumption strategy is fulfilled, and higher flexibility is realized; meanwhile, the PMU module supplies power to different power utilization units respectively, so that the possibility of hanging up buses of all the power utilization units in the chip is reduced, and the reliability of the WiFi chip circuit in dormancy and awakening is improved.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the provided drawings without creative efforts.
Fig. 1 is a structural distribution diagram of a WiFi chip circuit in an embodiment of the invention;
FIG. 2 is a diagram illustrating a structure of an AON cell according to an embodiment of the present invention;
FIG. 3 is a structural diagram of a backup circuit according to an embodiment of the present invention;
FIG. 4 is a diagram illustrating the structure definition of a microcode command according to an embodiment of the present invention;
FIG. 5 is a flowchart illustrating a microcode command backup process according to an embodiment of the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
The purpose of low-power consumption is realized through PMU and clock gate technique usually to common low-power consumption scheme, though can reach the effect of low-power consumption dormancy, can't carry out dynamic adjustment according to the use scene of difference, the flexibility ratio is low on the one hand, in the in-process of dormancy and awakening, in case the bus is handled badly, probably leads to the chip bus to hang up, awakens the in-process data recovery failure of process.
In the application, the PMU module is controlled by using the AON (always on) unit which is permanently powered to stop supplying power to different power utilization units, so that power failure of corresponding levels in different power consumption strategies is realized, the aim of dynamically adjusting the low power consumption strategy is fulfilled, and higher flexibility is realized; meanwhile, the PMU module supplies power to different power utilization units respectively, so that the possibility of hanging up buses of all the power utilization units in the chip is reduced, and the reliability of the WiFi chip circuit in dormancy and awakening is improved.
The embodiment of the invention discloses a WiFi chip circuit, which is shown in figure 1 and comprises the following components: the system comprises a PMU module 1 and an SOC module 2 powered by the PMU module 1;
the AON unit 21 in the SOC module 2 is always in a power supply state, and is configured to generate a power-off instruction at a corresponding level according to the power consumption policy instruction and send the power-off instruction to the PMU module 1, so that the PMU module 1 stops supplying power to a corresponding power utilization unit in the SOC module 2 according to the power-off instruction.
It is understood that the AON unit 21 belongs to a never power-off region on the SOC (System on Chip) module 2, and as can be seen in fig. 1, the AON unit 21 is powered by an RTC-low dropout Regulator (RTC) unit in the PMU module 1. Meanwhile, the PMU module 1 further includes a BUCK unit, an IO33LDO unit, an RFLDO unit, a CLDO unit, etc., and may output voltages and currents of different voltage levels, including various power domains such as 3.3V, 2.5V, 1.8V, 1.1V, etc., so as to supply power to each power consuming unit in the SOC module 2. Fig. 1 is only an example of a WiFi chip circuit, where the PMU module 1 and the SOC module 2 are both designed according to conventional requirements, and power supply relationships, power consumption units, and power supply units are all designed by way of example, except fig. 1, the PMU module 1 and the SOC module 2 of other architectures may also implement the present embodiment, and this is not limited herein.
On the other hand, since the WiFi chip circuit in this embodiment has the PMU module 1 capable of converting voltage, the WiFi chip circuit does not need too many power pins, only needs two power pins, one of which is used as a power input of the RTCLDO unit, and the power pin is normally connected to an external battery and is in a normally open mode; the other may be the power input of other power supply units in the PMU module 1, and the power pin may be powered by other external facilities. Furthermore, it can be considered that only one power pin is provided as a power input of the PMU module 1, only the RTCLDO unit in the PMU module 1 needs to continuously supply power, and other power supply units determine whether to output corresponding voltages according to respective enable signals or power-off instructions on the basis of accessing the power input. Based on PMU module 1, the chip pin has effectively been practiced thrift to wiFi chip circuit in this embodiment to the place and route degree of difficulty and the wiring area of inside PCB have been reduced.
Further, the power consumption policy instructions include: an active power consumption instruction chip-active, and/or a WiFi sleep instruction WiFi-sleep, and/or a clock sleep instruction clock-sleep, and/or a light sleep instruction light-sleep, and/or a deep sleep instruction deep-sleep.
The power consumption policy instruction specifically includes:
the host driver, the WiFi or the peripheral interface sends the power consumption policy instruction to AON unit 21 through the CPU, and/or the CPU generates the power consumption policy instruction according to the internal state of the WiFi chip circuit and sends the power consumption policy instruction to AON unit 21.
Specifically, each power consumption policy instruction has the following characteristics when executed: activating a state power consumption instruction chip _ active, wherein all power consumption units of the WiFi chip circuit work, the chip is in a maximum power consumption mode, and when data loading in the EFUSE unit is completed, the PMU module 1 powers off the EFUSE unit; WiFi sleep instruction WiFi-sleep, the tx direction of WiFi unit is all powered off, part of rx direction works, CPU and part of peripheral equipment work, CPU can control PWM (pulse width Modulation) or I2S (Inter-IC Sound, Integrated Circuit built-in audio bus), I2C (Inter-Integrated Circuit, two-wire serial bus) to run under the mode, WiFi chip Circuit can decide whether to enter chip-active mode or light-sleep mode according to received WiFi command; a light sleep instruction light-sleep, wherein the tx direction of the WiFi unit is powered off, part of rx directions work, the CPU and the peripheral equipment are powered off, and the ANA PLL unit is powered off; the deep sleep instruction deep-sleep, only the RTC circuit remains to operate, and both the PMU module 1 and the SOC module 2 are powered off.
Further, after entering the power consumption mode corresponding to the power consumption policy instruction, the original low power consumption mode may be exited by interruption or wakeup, specifically, AON unit 21 is further configured to:
and generating a power supply instruction of a corresponding level according to the wake-up instruction and sending the power supply instruction to the PMU module 1, so that the PMU module 1 supplies power to a corresponding power utilization unit in the SOC module 2 according to the wake-up instruction.
The wake-up instruction is specifically a sleep interrupt signal sent by the RTC circuit in the WiFi, the CPU, the peripheral interface or the AON unit 21.
It is understood that, in different power consumption modes, the wake-up command may come from different places, such as when in the WiFi _ sleep power consumption state, the wake-up command may come from a sleep interrupt signal of WiFi, CPU, RTC (Real _ Time Clock) circuit, or external pin; when the power-off state is in the light-sleep power consumption state, the wake-up instruction can be a sleep interrupt signal from a CPU, an RTC circuit or an external pin; when in deep-sleep power consumption state, the wake-up command may come from an external RTC.
Wherein the RTC circuit is located in AON unit 21.
The application discloses wiFi chip circuit includes: the system comprises a PMU module and an SOC module powered by the PMU module; the system comprises an SOC module and a Power Management Unit (PMU), wherein an AON unit in the SOC module is always in a power supply state and is used for generating a power failure instruction of a corresponding level according to a power consumption strategy instruction and sending the power failure instruction to the PMU module so that the PMU module stops supplying power to a corresponding power unit in the SOC module according to the power failure instruction. In the application, the permanently powered AON unit is used for controlling the PMU module to stop supplying power to different power utilization units, so that power failure of corresponding levels in different power consumption strategies is realized, the aim of dynamically adjusting the low power consumption strategy is fulfilled, and higher flexibility is realized; meanwhile, the PMU module supplies power to different power utilization units respectively, so that the possibility of hanging up buses of all the power utilization units in the chip is reduced, and the reliability of the WiFi chip circuit in dormancy and awakening is improved.
The embodiment of the invention discloses a specific WiFi chip circuit, and compared with the previous embodiment, the technical scheme is further explained and optimized in the embodiment. Specifically, in the present embodiment, data backup during power consumption policy adjustment is added, see the structural distribution diagram of AON unit 21 shown in fig. 2.
Specifically, AON unit 21 includes a sleep control circuit sleep-ctrl, a backup circuit back-restore, and a reset circuit reset-unit, where:
before generating a power-off instruction of a corresponding level according to the power consumption strategy instruction and sending the power-off instruction to the PMU module 1, the sleep-control circuit sleep-ctrl generates a backup instruction according to the power consumption strategy instruction and sends the backup instruction to the backup circuit back-restore;
the backup circuit back-restore respectively performs data backup on the corresponding power utilization units according to the backup instruction, and sends feedback information to the sleep-ctrl circuit after the data backup is finished;
after receiving the feedback information, the sleep control circuit sleep-ctrl sends a first enable signal for power isolation to the reset-unit;
the reset circuit reset-unit sets the corresponding power utilization unit to be in a reset state according to the first enabling signal.
Similarly, when the wake-up is interrupted, data recovery of each power-using unit is also required, so that AON unit 21 includes a wake-up interrupt circuit wakeup-ctrl, a sleep control circuit sleep-ctrl, a backup circuit back-restore, and a reset circuit reset-unit, where:
the wakeup interrupt circuit wakeup-ctrl generates a corresponding power supply instruction according to the wakeup instruction and sends the power supply instruction to the sleep control circuit sleep-ctrl;
enabling the PMU module 1 by the sleep-ctrl circuit according to the power supply instruction, so that the PMU module 1 supplies power to a corresponding power unit in the SOC module 2 according to the power supply instruction;
when the reset circuit reset-unit receives the PLL LOCK signal of the ANA PLL unit in the SOC module 2, the reset signal of the SOC module 2 is released, and the backup circuit back-restore restores the backup data to the corresponding power utilization unit.
Further, AON unit 21 further includes the RTC circuit, WiFi-RX, clock-tree and buffer RAM all of which are shown in the previous embodiment.
Specifically, the work flow of the WiFi chip circuit including AON unit 21 in this embodiment is as follows:
firstly, electrifying process:
firstly, the RTC circuit is powered on, when the RTC circuit outputs a digital signal RTC _ rdy indicating that the AON unit 21 starts to work, the AON unit 21 outputs PMU _ enable signal to enable the PMU module 1;
when the PMU module 1 detects the PMU _ enable signal, the PMU module 1 starts to power on the power supply units corresponding to the sub-power domains, such as 3.3V, 2.5V, 1.8V, 1.1V, and the like;
when the power supply units of the sub power domains are powered on, the PMU module 1 outputs a vcore _ rdy signal and pulls down PMU _ rst _ n signal to enable the ANA PLL unit;
when the Reset unit module detects the PLL LOCK signal sent by the ANA PLL unit, the global Reset is released, and the WiFi chip circuit starts to work normally.
Entering a low power consumption process:
when the WiFi chip circuit normally works, a power consumption strategy instruction can be issued to the CPU through host driving, WiFi or other peripheral interfaces, or the CPU directly generates a desired power consumption strategy instruction after detecting the internal state of the chip, the CPU determines which part of circuits are powered off by the PMU or clocks according to the corresponding level of the power consumption strategy instruction, and when the power is powered off, the clocks are turned off certainly, but the clocks are not necessarily turned off when the power is turned off. The power consumption policy instructions mainly include the following types: entering a WiFi-sleep mode in the type one; type two, enter light-sleep mode; entering a deep-sleep mode in a type III; type four, turning off the EFUSE power supply; type five, some peripheral clocks are turned off. And after receiving the power consumption strategy instruction, the CPU prepares data to be backed up according to different types.
The CPU sends a power consumption strategy instruction to a sleep-ctrl circuit, and meanwhile, the CPU determines whether the CPU enters a sleep mode or not according to the type of the power consumption strategy instruction; the sleep control circuit sleep-ctrl analyzes the instruction type, generates control signals of each module, and sends a backup instruction to the backup circuit back-restore;
the backup circuit back-restore receives a backup instruction of the sleep control circuit sleep-ctrl, backups important data of a corresponding power utilization unit, and sends feedback information to the sleep control circuit sleep-ctrl after the backup is completed;
after receiving feedback information of a back-restore of a backup circuit, a sleep control circuit sleep-ctrl generates a power-off instruction and a first enabling signal according to different power consumption strategy instructions, and controls a reset circuit reset-ctrl to set a corresponding circuit to be in a reset state through the first enabling signal;
the PMU module 1 closes the power supply of the corresponding power utilization unit according to a power-off instruction sent by the sleep-ctrl circuit sleep-sleep, that is, enable signals of different power domains; if the power consumption strategy command is to enter deep-sleep mode at this time, the entire PMU module 1 is finally pulled down PMU _ enable signal.
And III, exiting the low power consumption process:
the interrupt controller sends a wake-up instruction of chip wake-up interrupt to a wake-up interrupt circuit wakeup-ctrl;
the Wakeup interrupt circuit Wakeup-ctrl generates different power supply instructions according to the received Wakeup instruction and sends the different power supply instructions to the sleep control circuit sleep-ctrl;
according to the received power supply instruction, the sleep control circuit sleep-ctrl firstly enables the PMU module 1, that is, pulls up PMU _ enable signal;
enabling the ANA PLL unit when AON unit 21 detects that the vcore _ rdy signal is valid and the pmu _ rst _ n signal is released; meanwhile, the sleep control circuit sleep-ctrl pulls down enable signals of different power domains.
When the ANA PLL unit generates the PLL LOCK signal, the reset circuit reset-ctrl releases the reset signal;
when the chip reset signal is released, the backup circuit back-restore restores the backup data to the designated position from the RAM;
when the backup circuit back-restore finishes all backup data recovery, the sleep-ctrl circuit sleep-ctrl exits the whole low-power flow and wakes up the CPU, and the WiFi chip circuit starts normal operation.
Wherein, when the chip is in different low power consumption states, the wake-up instruction can be originated from different places. If the chip is in the WiFi _ sleep state, the wake-up command may be from interrupts of WiFi, CPU, RTC, and external pin; when the chip is in a light-sleep state, the wake-up instruction can be from interrupts of a CPU, an RTC and an external pin; when the chip is in deep-sleep state, the wake-up command comes from the external RTC.
It can be understood that, by using the layout of AON unit 21 in this embodiment, different power consumption strategies can be flexibly selected, thereby effectively reducing the power consumption of the chip and achieving the optimal power saving purpose; meanwhile, a backup circuit back-restore is arranged to realize backup and recovery of important data, and power-on time of a chip is reduced. Due to the fact that state interaction exists among the plurality of power utilization units in the whole low-power-consumption entering and exiting processes, the situation that buses are hung up in the backup and recovery processes is effectively prevented.
The embodiment of the invention discloses a specific WiFi chip circuit, and compared with the previous embodiment, the technical scheme is further explained and optimized in the embodiment. Specifically, in this embodiment, data backup during power consumption policy adjustment is added, as shown in fig. 3, the backup circuit back-restore includes:
the instruction fetching subunit cmd-fetch is used for fetching the microcode command from the buffer according to the backup instruction;
an ALU (Arithmetic Logic Unit) subunit for parsing microcode commands;
and the data action subunit is used for moving the data in the buffer according to the analyzed microcode command.
The data action subunit mainly comprises data-burst and AHB-master, wherein AHB-master is connected to a bus through a master interface of the AHB and can read the value and address of a register and return the value and address to the data-burst, and the data-burst is responsible for writing in a buffer or the register in the backup and recovery processes. Other buses may be selected as an alternative to the AHB bus in this embodiment.
Specifically, the backup process of the backup circuit back-restore is as follows:
the sleep control circuit sleep-ctrl sends a backup instruction to the backup circuit back-restore, and the backup object includes types of umac register data, lmac register data, phy register data and the like;
the backup circuit back-restore fetches the micro-code command micro-code from the RAM through the fetch subunit cmd-fetch according to the received backup instruction;
the backup circuit back-restore firstly checks the bus status bit of each power consumption unit according to the micro-code command micro-code and reads the status of the corresponding register through ahb-master;
the backup circuit back-restore fetches the micro-code command micro-code again, including the length of backup, and stores the information such as the initial address of the data to be backed up.
The backup circuit back-restore fetches the micro-code command micro-code, and when the backup command is fetched, the register starts to be backed up.
The data recovery process is similar to the backup process, and can be derived, which is not described herein again.
Further, the micro-code command may have a structure defined as shown in fig. 4, where B3 is different types of instructions and can support up to 256 types; b2, B1, B0 are the immediate numbers of three bytes. As shown in fig. 5, in the backup process using microcode command micro-code, a backup space is initialized by a mem _ write instruction, including information such as a source address and a length; after the initialization is completed, a backup instruction is sent, then the backup circuit back-restore starts to fetch a source address, the data to be backed up is read from the source address, and the data to be backed up is written into a Random Access Memory (RAM) of the AON unit 21; and when the backup length reaches the configured length, the backup is completed, and feedback information is sent to the sleep-ctrl circuit sleep-ctrl.
It can be understood that, in the embodiment, the backup circuit back-restore implements data backup and recovery by using the microcode command and the ALU subunit, the microcode command effectively reduces the program amount of the software, and can simulate the software operation in the form of hardware of the ALU subunit when the software is in a sleep state, thereby improving the hardware flexibility.
Correspondingly, the embodiment of the application also discloses a WiFi device, which comprises the WiFi chip circuit in any one of the above embodiments.
It is understood that, for details of the WiFi device in this embodiment, reference may be made to the details of the WiFi chip circuit in the foregoing embodiments, and details are not described here.
The beneficial effects of the WiFi device in this embodiment are the same as those of the WiFi chip circuit in the above embodiments, and are not repeated here.
Finally, it should also be noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.
The WiFi chip circuit and the WiFi device provided by the present invention are introduced in detail, and a specific example is applied in the present document to explain the principle and the implementation of the present invention, and the description of the above embodiment is only used to help understanding the method and the core idea of the present invention; meanwhile, for a person skilled in the art, according to the idea of the present invention, there may be variations in the specific embodiments and the application scope, and in summary, the content of the present specification should not be construed as a limitation to the present invention.
Claims (9)
1. A WiFi chip circuit, comprising: the system comprises a PMU module and an SOC module powered by the PMU module;
the system comprises an SOC module and a Power Management Unit (PMU), wherein an AON unit in the SOC module is always in a power supply state and is used for generating a power failure instruction of a corresponding level according to a power consumption strategy instruction and sending the power failure instruction to the PMU module so that the PMU module stops supplying power to a corresponding power unit in the SOC module according to the power failure instruction.
2. The WiFi chip circuit of claim 1, wherein the AON unit comprises a sleep control circuit, a backup circuit, and a reset circuit, wherein:
before generating a power-off instruction of a corresponding level according to the power consumption strategy instruction and sending the power-off instruction to the PMU module, the sleep control circuit generates a backup instruction according to the power consumption strategy instruction and sends the backup instruction to a backup circuit;
the backup circuit respectively performs data backup on the corresponding power utilization units according to the backup instruction, and sends feedback information to the sleep control circuit after the data backup is finished;
after receiving the feedback information, the sleep control circuit sends a first enabling signal with isolated power to the reset circuit;
the reset circuit sets the corresponding power utilization unit to be in a reset state according to the first enabling signal.
3. The WiFi chip circuitry of claim 2, wherein the backup circuitry comprises:
the instruction fetching subunit is used for fetching a microcode command from the buffer according to the backup instruction;
an ALU subunit, configured to parse the microcode command;
and the data action subunit is used for moving the data in the buffer according to the analyzed microcode command.
4. The WiFi chip circuit of any one of claims 1-3, wherein the power consumption policy instructions comprise: an active state power consumption instruction, and/or a WiFi sleep instruction, and/or a clock sleep instruction, and/or a light sleep instruction, and/or a deep sleep instruction.
5. The WiFi chip circuit of claim 4, wherein the power consumption policy instructions specifically comprise:
and the CPU generates and sends the power consumption strategy instruction to the AON unit according to the internal state of the WiFi chip circuit.
6. The WiFi chip circuit of claim 4, wherein the AON unit is further configured to:
and generating a power supply instruction of a corresponding level according to the awakening instruction and sending the power supply instruction to the PMU module so that the PMU module supplies power to a corresponding power utilization unit in the SOC module according to the awakening instruction.
7. The WiFi chip circuit of claim 6, wherein the wake-up instruction is specifically based on a sleep interrupt signal sent by the RTC circuit in the WiFi, the CPU, the peripheral interface, or the AON unit.
8. The WiFi chip circuit of claim 6, wherein the AON unit comprises a wake-up interrupt circuit, a sleep control circuit, a backup circuit, and a reset circuit, wherein:
the wake-up interrupt circuit generates a corresponding power supply instruction according to the wake-up instruction and sends the power supply instruction to the sleep control circuit;
the sleep control circuit enables the PMU module according to the power supply instruction so that the PMU module supplies power to a corresponding power utilization unit in the SOC module according to the power supply instruction;
when the reset circuit receives a PLL LOCK signal of an ANA PLL unit in the SOC module, the reset circuit releases the reset signal of the SOC module, and the backup circuit restores backup data to a corresponding power utilization unit.
9. A WiFi device comprising a WiFi chip circuit as claimed in any one of claims 1 to 8.
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