CN110334445A - A kind of control method of low power dissipation design - Google Patents
A kind of control method of low power dissipation design Download PDFInfo
- Publication number
- CN110334445A CN110334445A CN201910605610.7A CN201910605610A CN110334445A CN 110334445 A CN110334445 A CN 110334445A CN 201910605610 A CN201910605610 A CN 201910605610A CN 110334445 A CN110334445 A CN 110334445A
- Authority
- CN
- China
- Prior art keywords
- power
- low
- chip
- wake
- hardware
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/39—Circuit design at the physical level
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Evolutionary Computation (AREA)
- Geometry (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Power Sources (AREA)
Abstract
The present invention relates to chip Low-power Technology fields, disclose a kind of control method of low power dissipation design.Chip is controlled by the way of software and hardware combining enters and exit low-power consumption mode.Firstly, the modules of chip are divided different electrical power domain, each power domain uses respective power voltage supply；Secondly, software configuration wake source and low-power consumption mode register；Then, hardware gradually closes the power supply of modules, and chip is made to enter low-power consumption mode；In addition, hardware generates the isolation signals between wake-up signal and different electrical power domain according to the wake source configured, the disconnection of different electrical power domain power supply is generated by software control, and the wakeup unit of hardware generates the closure of power supply；Finally, chip is exited from low-power consumption mode, each module of hardware is gradually powered on, and starts to work.Wake-up signal is generated by combinational logic, delay unit and latch, so that chip does not need clock and samples to wake-up signal, to significantly reduce power consumption of the chip under low-power consumption mode.
Description
Technical field
It is the present invention relates to the low power dissipation design field of chip, in particular to a kind of to reduce the low of chip suspend mode or stand-by power consumption
Power dissipation design control method.
Background technique
As people are to portable and wearable electronic product demand raising, and the limit developed by battery capacity
System, the low power dissipation design of chip are increasingly valued by people.The method of low power dissipation design includes the domain based on physical level
Placement-and-routing's optimization；Multi-Vt design, optimised power consumption of eda tool based on gate level circuit etc.；Gate based on RTL level
Clock, operand isolation, resource-sharing, state encoding optimization, Parallel Design etc.；Designed based on the multivoltage of system and framework,
Power gating, Hardware/Software Collaborative Design, dynamic voltage frequency adjusting etc..In some applications, chip only needs discontinuity
Work, the most of the time is suspend mode or standby mode, and such as low-power consumption bluetooth chip, it is long that one piece of button cell can provide chip
Up to the power supply of several years, reduce chip suspend mode or it is standby when power consumption be this kind of chip low power dissipation design one of main means.
The present invention is based on the Low-power Technology of system and architecture level, introduce a kind of reduction chip suspend mode or it is standby when power consumption controlling party
Method.
Summary of the invention
The technical problem to be solved in the present invention is to provide a kind of control methods of low power dissipation design, do not need work in chip
When, it is even standby for a long time that control chip enters short time suspend mode (Sleep), deep-sleep (DeepSleep)
(PowerDown) low-power consumption mode, and chip start-up operation can be waken up in time when chip needs work, thus significantly
Reduction chip power-consumption, improve the service life of supplying cell.
The present invention includes the following contents: controlling chip by the way of software and hardware combining and enters and exit low-power consumption mode.
Firstly, the modules of chip are divided different electrical power domain, each power domain uses respective power voltage supply；Software configuration wake source
And low-power consumption mode；Hardware gradually closes the power supply of modules, and chip is made to enter low-power consumption mode；In addition, according to being configured
Wake source, hardware generates the isolation signals between wake-up signal and different electrical power domain, the disconnection of different electrical power domain power supply by
Software control generates, and the wakeup unit of hardware generates the closure of power supply；Finally, chip is exited from low-power consumption mode, each mould of hardware
Block is gradually powered on and is started to work.
Detailed description of the invention
Fig. 1 is the division in chip different electrical power domain；
Fig. 2 is the circuit diagram that isolated from power signal generates；
Fig. 3 is the circuit diagram that wake-up signal generates；
Fig. 4 is the circuit diagram that power switch signal generates.
Specific embodiment
Present invention will now be described in further detail with reference to the accompanying drawings and specific embodiments:
The control method of low power dissipation design of the invention is the low power dissipation design based on system and architecture level, using software and hardware
In conjunction with mode control chip enter and exit low-power consumption mode, be mainly achieved by the steps of:
Step 1, hardware divide different electrical power domain to chip, each power domain is supplied using respective voltage according to application demand
Electricity: the division of power domain is as shown in Fig. 1, and digital logic portion, analog logic part, high frequency clock partial circuit are divided in
Main power source area (MAIN)；The number and simulation part that IO, RTC, low-frequency clock, top-level logic and small part are used to store and wake up
Low-power dissipation power supply area (ULP) is assigned in graduation；Normally opened power supply area (Always on) is only comprising necessary wakeup logic and minimal amount of
Register；FLASH is divided into individual power supply area since supply voltage is different；SRAM power supply and voltage can be separately configured and
Division is independent power supply area.
When not needing work in the chip short time, the power supply in the area MAIN, the area FLASH and part SRAM power supply area can be closed
(Sleep or DeepSleep mode)；When prolonged periods do not need work, MAIN, ULP and FLASH, portion can be simultaneously closed off
Divide the power supply of these power supply areas of SRAM, only retains the power supply (PowerDown mode) in this partial power area Always on, this
When chip make it that can also maintain the several years in battery powered situation with extremely low power consumption.The power supply state of each power domain, by
The switch control of electric power network, shown in S1, S2, Ram_pd as shown in figure 1 etc..
To each respective supply voltage of power supply configuration of territory, to further decrease the power consumption of chip.Due to high threshold voltage
Unit leakage current it is smaller, the frequency of the circuit in the region Always on overturning is again very low, and dynamic power consumption can be ignored not
It counts, therefore the power supply in the region Always on is set as the voltage of 3.3V.The electric leakage proportion of SRAM in the chips compares
Height if you do not need to using too many SRAM, can close extra SRAM power supply in practical applications；Into low-power consumption
When mode, the content of SRAM if the need to keep, and low-power consumption mode does not need the content of access SRAM, and the voltage of SRAM is matched
Setting relatively low value (as the voltage of 0.5V or so can restore the content inside SRAM after chip wake-up) can be into
One step reduces its electricity leakage power dissipation；The voltage of SRAM is adjusted back to normal operating voltage 1.0V again after chip wake-up.
Between different electrical power domain, due to the difference of supply voltage, it is also necessary to level conversion unit be added, high (low) electricity
The signal of intermediate pressure section is transformed into low (height) voltage regime.
Step 2, software can configure wake source, and configures low-power consumption mode register；It, can under different low-power consumption modes
Different wake sources is set: when needing timing working, in settable RTC timing or the generation of other timing modules positioned at the area ULP
Break to wake up chip；When not needing timing working, chip can also be waken up by other modes such as I/O port or chip resets.
Chip provides three kinds of low-power consumption modes for software selection, i.e. suspend mode (Sleep) mode, deep-sleep
(DeepSleep) mode and standby (PowerDown) mode.Sleep and DeepSleep mode can all close the area FLASH and
The power supply of the power supply in the area MAIN, SRAM can be chosen whether to close by software, their main distinction is that Sleep mode remains
The clock module of 32kHz is powered.
Step 3, hardware gradually close the power supply of modules, and chip is made to enter low-power consumption mode: adoption status machine is controlled
The switching sequence of modules power supply processed, while power switch network is switched one by one using concatenated mode in the domain stage,
To reduce dash current of the chip when entering and exiting low-power consumption mode.The switch of electric power network and the area Always on one
Sample is all realized using high threshold voltage unit.
Step 4, the isolation letter according to the wake source configured, between hardware generation wake-up signal and different electrical power domain
Number, and clock is waken up by wakeup unit, the disconnection of different electrical power domain power supply is generated by software control, and the wakeup unit of hardware generates
The closure of power supply: when chip is in low-power consumption mode, when the signal on hardware awake source change and meet wake-up condition with
Afterwards, the delay unit on hardware circuit, latch and a series of combinational logic can generate wake-up signal, and chip will be called out
It wakes up；Which kind of operating mode is tube chip be not in, and after carrying out hardware reset by chip reset pin, entire chip will be reset
And it automatically wakes up.
The switch control of power supply needs that the isolation list controlled by isolation signals is added between charging zone and lower electric region
Member makes the output signal of lower electric module be fixed on 1 or 0 value, to avoid power consumption loss.The tool of isolation signals ulp_aon_iso_en
Body is realized as shown in Fig. 2.When software configuration chip enters PowerDown mode, hardware can generate a pulse signal s1_
Swoff_cs (clock end that this signal is connected to latch), clock pulses has been locked into latch 1, ulp_aon_iso_
En is immediately raised, and the area ULP is realized with the area Always on to be isolated.Isolation signals ulp_aon_iso_en is only in chip
It is waken up, re-powers and the end CLR that can be just latched device after stablizing is reset.Isolation signals interrelated logic all must be placed at
The power supply area of electrification just can guarantee being effectively isolated for circuit.In Fig. 2, S1_swoff_cs is software configuration low-power consumption register
When the pulse signal that generates.The isolation signals in the area ULP and the area MAIN, the area FLASH and the area ULP, the area SRAM and other power supply areas
Realization it is similar with ulp_aon_iso_en signal.
The generation of wake-up signal (pd_wakeup) does not need the participation of clock, realizes that circuit is as shown in Fig. 3: when soft
When part configuration chip enters PowerDown mode, it is locked by the clock pulse signal s1_swoff_cs that software control generates 1
Latch, latch can be reset after pd_wakup signal is delayed a period of time by the end CLR.And the input terminal variation of hardware
The signal stored before output and entrance PowerDown mode with latch passes through after some combinational logics, can
Generate the pulse signal pd_wakeup waken up.This example only lists level wake-up mode, for pulse wake up (rising edge or
Failing edge) it is applied equally to the present invention, the wake-up signal of Sleep and DeepSleep mode generates logical AND pd_wakeup mono-
It causes.In addition, the generation logic of wake-up signal all must assure that the region for being placed on electrification.
The physical circuit of the switch control signal (such as S1_EN) of power supply is realized as shown in Fig. 4: in the rising of isolation signals
After delay a period of time, a pulse is generated by logic as shown in the figure, as the clock of latch, thus 0 lock
Into latch, S1_EN becomes the disconnection of the area 0, ULP power supply；Wake-up signal has been ultimately connected to the set end of latch, works as wake-up
After the pulse of signal generates, S1_EN will be set to 1, ULP power supply area immediately will obtain the power supply of power supply.S1_EN be every
From what is just disconnected after signal delay a period of time, to ensure that ULP's jagged will not be input to the area Always on；This
Outside, the generative circuit of S1_EN all must be placed at the area Always on, just can guarantee that the power switch of ULP will not be in part in this way
Modular power source close when false triggering and cause S1_EN burr occur.The control circuit of S2_EN and other power switches is realized
Mode is similar with S1_EN.
Step 5, chip are exited from low-power consumption mode, and each module of hardware gradually powers on, and starts to work.
For exiting for PowerDown mode, after hardware generates pd_wakeup, the area ULP is first powered on, first low frequency when
Clock (32kHz) powers on start-up operation, and after it is stablized, release resets, and the area MAIN and the area FLASH start power up, high frequency clock
(32MHz) then starts to work, and after high frequency clock is stablized, discharges the reset of CPU, CPU starts to work.For Sleep or
DeepSleep mode exits, and the area ULP will not power off, after hardware generates lp_wakeup, the area MAIN, the area FLASH and low frequency
Clock module (if the case where having powered off) starts power up, and high frequency clock (32MHz) is then started to work, and stablizes to high frequency clock
After, discharge the reset of CPU, the operation such as CPU starts to execute instruction.
By above-mentioned specific embodiment and embodiment, show under SMIC 55nm technique through chip actual measurement, chip
Totally 215.6 ten thousand gate equivalent circuit, the control method of low power dissipation design of the invention make chip power consumption in PowerDown mode
Power consumption is respectively down to 0.8 μ A and 1.0 μ A when down to 0.095 μ A, Sleep and DeepSleep mode.The present invention has carried out detailed
Illustrate, but these should not be construed as limiting the present invention.Without departing from the principles of the present invention, those skilled in the art
Many modification and improvement can be also made, these also should be regarded as protection scope of the present invention.
Claims (8)
1. a kind of control method of low power dissipation design, which is characterized in that controlled by the way of software and hardware combining chip enter and
Low-power consumption mode is exited, is mainly achieved by the steps of:
The modules of chip are divided different electrical power domain, each power domain is using respective according to application demand by step 1, hardware
Power voltage supply；
Step 2, software can configure wake source, and configures low-power consumption mode register；
Step 3, hardware gradually close the power supply of modules, and chip is made to enter low-power consumption mode；
Step 4, according to the wake source configured, hardware generates the isolation signals between wake-up signal and different electrical power domain, together
When, the disconnection of different electrical power domain power supply is generated by software control, and the wakeup unit of hardware generates the closure of power supply；
Step 5, chip are exited from low-power consumption mode, and each module of hardware gradually powers on, and starts to work.
2. control method according to claim 1, which is characterized in that the step 1: hardware is according to application demand, core
The modules of piece divide different electrical power domain, and each power domain uses respective power voltage supply: digital logic portion, analog logic
Partially, high frequency clock partial circuit is divided in main power source area (MAIN)；IO, RTC, low-frequency clock, top-level logic and small part
Number and analog portion for storing and waking up are divided into low-power dissipation power supply area (ULP)；Normally opened power supply area (Always on) is only
Include necessary wakeup logic and minimal amount of register；FLASH is divided into individual power supply area since supply voltage is different；
SRAM can be separately configured power supply and voltage and divide and be independent power supply area.
3. control method according to claim 1, which is characterized in that the step 2: software can configure wake source, and match
Set low power consumption mode register: software needs first to configure wake source before setting chip enters low-power consumption mode；Different
Under low-power consumption mode, settable different wake source；Chip provides three kinds of low-power consumption modes for configuration, i.e. suspend mode (Sleep)
Mode, deep-sleep (DeepSleep) mode and standby (PowerDown) mode.
4. control method according to claim 1, which is characterized in that the step 3: hardware gradually closes modules
Power supply makes chip enter low-power consumption mode: adoption status machine controls the switching sequence of modules power supply, while in domain rank
Section uses concatenated mode to the switch of modular power source line, opening or closing one by one, thus reduce chip entering and
Exit dash current when low-power consumption mode.
5. control method according to claim 1, which is characterized in that the step 4: according to the wake source configured, firmly
Part generates the isolation signals between wake-up signal and different electrical power domain, meanwhile, the disconnection of different electrical power domain power supply is by software control
System generates, and the wakeup unit of hardware generates the closure of power supply: entering after low-power consumption mode, has when on the circuit in hardware awake source
After signal changes and meets wake-up condition, patrolled by delay unit, latch and a series of combination on hardware circuit
It collects and generates wake-up signal；Which kind of operating mode is tube chip be not in, and after pressing reset pin, hardware will be automatically waken up.
6. control method according to claim 1, which is characterized in that the isolation signals in the step 4 are required in power supply
It is first generated before disconnecting；It is re-powering, and is being discharged again after stablizing；In addition, isolation signals interrelated logic all must be placed at
The power supply area of electrification.
7. control method according to claim 1, which is characterized in that the generation of the wake-up signal in the step 4 is not required to
The participation of clock is wanted, hardware first latches the desired value of wake-up signal before entering low-power consumption mode；Meanwhile which kind of chip enters
Low-power consumption mode can be also latched after postponing a period of time；When wake-up signal is consistent with desired value, will generate
Wake-up signal pulse.
8. control method according to claim 1, which is characterized in that the disconnection of the power supply in the step 4 require every
It is generated after for a period of time from signal delay；The closure of power supply in the step 4 requires after receiving wake-up signal immediately
It generates.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910605610.7A CN110334445A (en) | 2019-07-05 | 2019-07-05 | A kind of control method of low power dissipation design |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910605610.7A CN110334445A (en) | 2019-07-05 | 2019-07-05 | A kind of control method of low power dissipation design |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN110334445A true CN110334445A (en) | 2019-10-15 |
Family
ID=68144731
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201910605610.7A Pending CN110334445A (en) | 2019-07-05 | 2019-07-05 | A kind of control method of low power dissipation design |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN110334445A (en) |
Cited By (23)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110908430A (en) * | 2019-10-22 | 2020-03-24 | 珠海市杰理科技股份有限公司 | Controller, data processing method, computer device, and storage medium |
| CN111159962A (en) * | 2019-12-23 | 2020-05-15 | 北京华大信安科技有限公司 | Low-power-consumption design method and system of embedded NVM chip |
| CN111309385A (en) * | 2020-01-17 | 2020-06-19 | 高新兴物联科技有限公司 | Interrupt awakening method and device, electronic equipment and readable storage medium |
| CN111427441A (en) * | 2020-04-02 | 2020-07-17 | 大唐微电子技术有限公司 | Power supply awakening method and device |
| CN111741518A (en) * | 2020-06-22 | 2020-10-02 | 湖南国科微电子股份有限公司 | WiFi chip circuit and WiFi device |
| CN112083791A (en) * | 2020-09-15 | 2020-12-15 | 南方电网数字电网研究院有限公司 | Chip power consumption optimization method and device, computer equipment and storage medium |
| CN112131831A (en) * | 2020-11-25 | 2020-12-25 | 北京智芯微电子科技有限公司 | Multi-power domain layout method and storage medium |
| CN112148662A (en) * | 2020-08-17 | 2020-12-29 | 上海赛昉科技有限公司 | Low-power-consumption chip architecture awakened by I2C address matching and awakening method |
| CN112202432A (en) * | 2020-09-30 | 2021-01-08 | 合肥寰芯微电子科技有限公司 | Low-power-consumption key and external interrupt compatible wake-up circuit and control method thereof |
| CN112235850A (en) * | 2020-09-23 | 2021-01-15 | 上海赛昉科技有限公司 | Low-power-consumption system and method of Internet of things chip |
| CN112484863A (en) * | 2020-11-18 | 2021-03-12 | 上海迈外迪网络科技有限公司 | Passenger flow analysis equipment |
| CN112650384A (en) * | 2021-01-05 | 2021-04-13 | 大唐微电子技术有限公司 | Low-power-consumption dormancy awakening control circuit and control circuit of multiple power domains |
| CN112947738A (en) * | 2019-12-10 | 2021-06-11 | 珠海全志科技股份有限公司 | Intelligent terminal power supply system and intelligent terminal standby and wake-up method |
| CN113595053A (en) * | 2021-08-23 | 2021-11-02 | 莱弗利科技(苏州)有限公司 | Low-power consumption sensing chip of no clock standby |
| CN113672075A (en) * | 2021-07-13 | 2021-11-19 | 平头哥(上海)半导体技术有限公司 | Peripheral management component, related device and method |
| CN113935273A (en) * | 2021-09-17 | 2022-01-14 | 东科半导体(安徽)股份有限公司 | Control signal connection method of low-power-consumption module |
| CN114326931A (en) * | 2021-12-29 | 2022-04-12 | 厦门码灵半导体技术有限公司 | Industrial-grade clock controller, industrial-grade control system, industrial-grade control method and electronic device |
| CN114637386A (en) * | 2022-03-24 | 2022-06-17 | 南京英锐创电子科技有限公司 | Processing method of low-power-consumption debugging path, debugging system and electronic equipment |
| CN114924634A (en) * | 2022-06-17 | 2022-08-19 | 广州万协通信息技术有限公司 | CPU dormancy awakening system and method |
| CN115774484A (en) * | 2023-02-13 | 2023-03-10 | 苏州聚元微电子股份有限公司 | Low-power consumption management system of TOUCH MCU |
| CN115857654A (en) * | 2023-02-27 | 2023-03-28 | 南京芯驰半导体科技有限公司 | System-on-chip low-power-consumption control method and device, system-on-chip and electronic equipment |
| CN116126117A (en) * | 2023-04-04 | 2023-05-16 | 上海维安半导体有限公司 | Automatic management system and method for on-chip power consumption |
| CN116860100A (en) * | 2023-04-19 | 2023-10-10 | 广州市粤港澳大湾区前沿创新技术研究院 | Design method for reducing power consumption of chip |
Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20030131268A1 (en) * | 2001-12-20 | 2003-07-10 | Nokia Corporation | Dynamic power control in integrated circuits |
| CN101859172A (en) * | 2009-04-07 | 2010-10-13 | 上海摩波彼克半导体有限公司 | Integrated circuit SoC chip circuit structure capable of realizing power reduction and method thereof |
| CN102545574A (en) * | 2010-12-27 | 2012-07-04 | 北京中电华大电子设计有限责任公司 | Low-power consumption power network designing method for system on chip (SOC) chip |
| CN102573114A (en) * | 2010-12-27 | 2012-07-11 | 北京中电华大电子设计有限责任公司 | Method for designing System on a Chip (SOC) chips with low power consumption for wireless local area network |
| CN106293005A (en) * | 2016-08-09 | 2017-01-04 | 成都蓉芯微科技有限公司 | Reduce the system and method for MCU chip stand-by power consumption |
| CN107967049A (en) * | 2017-10-18 | 2018-04-27 | 珠海全志科技股份有限公司 | A kind of implementation method that chip power-consumption is reduced based on usb protocol |
| CN109933846A (en) * | 2019-01-29 | 2019-06-25 | 厦门码灵半导体技术有限公司 | The control system and its power control method of super low-power consumption, electronic device |
-
2019
- 2019-07-05 CN CN201910605610.7A patent/CN110334445A/en active Pending
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20030131268A1 (en) * | 2001-12-20 | 2003-07-10 | Nokia Corporation | Dynamic power control in integrated circuits |
| CN101859172A (en) * | 2009-04-07 | 2010-10-13 | 上海摩波彼克半导体有限公司 | Integrated circuit SoC chip circuit structure capable of realizing power reduction and method thereof |
| CN102545574A (en) * | 2010-12-27 | 2012-07-04 | 北京中电华大电子设计有限责任公司 | Low-power consumption power network designing method for system on chip (SOC) chip |
| CN102573114A (en) * | 2010-12-27 | 2012-07-11 | 北京中电华大电子设计有限责任公司 | Method for designing System on a Chip (SOC) chips with low power consumption for wireless local area network |
| CN106293005A (en) * | 2016-08-09 | 2017-01-04 | 成都蓉芯微科技有限公司 | Reduce the system and method for MCU chip stand-by power consumption |
| CN107967049A (en) * | 2017-10-18 | 2018-04-27 | 珠海全志科技股份有限公司 | A kind of implementation method that chip power-consumption is reduced based on usb protocol |
| CN109933846A (en) * | 2019-01-29 | 2019-06-25 | 厦门码灵半导体技术有限公司 | The control system and its power control method of super low-power consumption, electronic device |
Cited By (31)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110908430B (en) * | 2019-10-22 | 2021-01-08 | 珠海市杰理科技股份有限公司 | Controller, data processing method, computer device, and storage medium |
| CN110908430A (en) * | 2019-10-22 | 2020-03-24 | 珠海市杰理科技股份有限公司 | Controller, data processing method, computer device, and storage medium |
| CN112947738A (en) * | 2019-12-10 | 2021-06-11 | 珠海全志科技股份有限公司 | Intelligent terminal power supply system and intelligent terminal standby and wake-up method |
| CN111159962A (en) * | 2019-12-23 | 2020-05-15 | 北京华大信安科技有限公司 | Low-power-consumption design method and system of embedded NVM chip |
| CN111159962B (en) * | 2019-12-23 | 2023-11-03 | 北京华大信安科技有限公司 | Low-power-consumption design method and system for embedded NVM chip |
| CN111309385A (en) * | 2020-01-17 | 2020-06-19 | 高新兴物联科技有限公司 | Interrupt awakening method and device, electronic equipment and readable storage medium |
| CN111427441A (en) * | 2020-04-02 | 2020-07-17 | 大唐微电子技术有限公司 | Power supply awakening method and device |
| CN111427441B (en) * | 2020-04-02 | 2022-07-12 | 大唐微电子技术有限公司 | Power supply awakening method and device |
| CN111741518A (en) * | 2020-06-22 | 2020-10-02 | 湖南国科微电子股份有限公司 | WiFi chip circuit and WiFi device |
| CN112148662A (en) * | 2020-08-17 | 2020-12-29 | 上海赛昉科技有限公司 | Low-power-consumption chip architecture awakened by I2C address matching and awakening method |
| CN112148662B (en) * | 2020-08-17 | 2024-02-09 | 上海赛昉科技有限公司 | Low-power-consumption chip architecture and wake-up method by using I2C address matching wake-up |
| CN112083791A (en) * | 2020-09-15 | 2020-12-15 | 南方电网数字电网研究院有限公司 | Chip power consumption optimization method and device, computer equipment and storage medium |
| CN112235850A (en) * | 2020-09-23 | 2021-01-15 | 上海赛昉科技有限公司 | Low-power-consumption system and method of Internet of things chip |
| CN112202432A (en) * | 2020-09-30 | 2021-01-08 | 合肥寰芯微电子科技有限公司 | Low-power-consumption key and external interrupt compatible wake-up circuit and control method thereof |
| CN112202432B (en) * | 2020-09-30 | 2022-11-22 | 合肥寰芯微电子科技有限公司 | Low-power-consumption key and external interrupt compatible wake-up circuit and control method thereof |
| CN112484863A (en) * | 2020-11-18 | 2021-03-12 | 上海迈外迪网络科技有限公司 | Passenger flow analysis equipment |
| CN112484863B (en) * | 2020-11-18 | 2022-02-08 | 上海迈外迪网络科技有限公司 | Passenger flow analysis equipment |
| CN112131831A (en) * | 2020-11-25 | 2020-12-25 | 北京智芯微电子科技有限公司 | Multi-power domain layout method and storage medium |
| CN112650384A (en) * | 2021-01-05 | 2021-04-13 | 大唐微电子技术有限公司 | Low-power-consumption dormancy awakening control circuit and control circuit of multiple power domains |
| CN113672075A (en) * | 2021-07-13 | 2021-11-19 | 平头哥(上海)半导体技术有限公司 | Peripheral management component, related device and method |
| CN113595053A (en) * | 2021-08-23 | 2021-11-02 | 莱弗利科技(苏州)有限公司 | Low-power consumption sensing chip of no clock standby |
| CN113935273A (en) * | 2021-09-17 | 2022-01-14 | 东科半导体(安徽)股份有限公司 | Control signal connection method of low-power-consumption module |
| CN114326931B (en) * | 2021-12-29 | 2023-08-15 | 厦门码灵半导体技术有限公司 | Industrial-grade clock controller, industrial-grade control system, method and electronic device |
| CN114326931A (en) * | 2021-12-29 | 2022-04-12 | 厦门码灵半导体技术有限公司 | Industrial-grade clock controller, industrial-grade control system, industrial-grade control method and electronic device |
| CN114637386A (en) * | 2022-03-24 | 2022-06-17 | 南京英锐创电子科技有限公司 | Processing method of low-power-consumption debugging path, debugging system and electronic equipment |
| CN114924634A (en) * | 2022-06-17 | 2022-08-19 | 广州万协通信息技术有限公司 | CPU dormancy awakening system and method |
| CN114924634B (en) * | 2022-06-17 | 2024-02-27 | 广州万协通信息技术有限公司 | CPU dormancy awakening system and method |
| CN115774484A (en) * | 2023-02-13 | 2023-03-10 | 苏州聚元微电子股份有限公司 | Low-power consumption management system of TOUCH MCU |
| CN115857654A (en) * | 2023-02-27 | 2023-03-28 | 南京芯驰半导体科技有限公司 | System-on-chip low-power-consumption control method and device, system-on-chip and electronic equipment |
| CN116126117A (en) * | 2023-04-04 | 2023-05-16 | 上海维安半导体有限公司 | Automatic management system and method for on-chip power consumption |
| CN116860100A (en) * | 2023-04-19 | 2023-10-10 | 广州市粤港澳大湾区前沿创新技术研究院 | Design method for reducing power consumption of chip |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN110334445A (en) | A kind of control method of low power dissipation design | |
| US7622955B2 (en) | Power savings with a level-shifting boundary isolation flip-flop (LSIFF) and a clock controlled data retention scheme | |
| TWI417710B (en) | Computer system for saving power consumption of a stand-by/power-off state and method thereof | |
| CN112083791B (en) | Chip power consumption optimization method and device, computer equipment and storage medium | |
| KR101962606B1 (en) | Integrated circuit with power gating | |
| KR100965198B1 (en) | wake-up reset circuit | |
| CN107003707B (en) | Integrated system with independent power domains and split power rails for logic and memory | |
| KR20070026441A (en) | State retention within a data processing system | |
| US8816741B2 (en) | State retention power gated cell | |
| CN102545574A (en) | Low-power consumption power network designing method for system on chip (SOC) chip | |
| CN106293005A (en) | Reduce the system and method for MCU chip stand-by power consumption | |
| CN116700412A (en) | Low-power consumption system, microcontroller, chip and control method | |
| CN115598406B (en) | Low-power-consumption voltage monitoring method and system based on state machine | |
| CN109799898A (en) | A kind of power control of chip, chip and its power control method | |
| US9780644B1 (en) | Methods and apparatus for always on domain finite state machine shutdown using a clock source from a power managed domain | |
| CN219574672U (en) | Low-power consumption system, microcontroller and chip | |
| CN109669524A (en) | The electrification reset circuit of chip | |
| CN206363301U (en) | The TYPE_C interface protocol chips of super low-power consumption | |
| CN101872997A (en) | Switch control method capable of continuously providing power and device thereof as well as power supply system | |
| Chen et al. | Self-super-cutoff power gating with state retention on a 0.3 V 0.29 fJ/cycle/gate 32b RISC core in 0.13 µm CMOS | |
| CN206133459U (en) | System for reduce MCU chip stand -by power consumption | |
| CN209625154U (en) | A kind of SOC electric power management circuit | |
| CN220671926U (en) | PMU, wake-up circuit and MCU | |
| US7313713B2 (en) | Sequential/combinational logic transistor segregation for standby power and performance optimization | |
| CN116126117B (en) | Automatic management system and method for on-chip power consumption |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| WD01 | Invention patent application deemed withdrawn after publication | ||
| WD01 | Invention patent application deemed withdrawn after publication |
Application publication date: 20191015 |