CN113595053A - Low-power consumption sensing chip of no clock standby - Google Patents
Low-power consumption sensing chip of no clock standby Download PDFInfo
- Publication number
- CN113595053A CN113595053A CN202110966699.7A CN202110966699A CN113595053A CN 113595053 A CN113595053 A CN 113595053A CN 202110966699 A CN202110966699 A CN 202110966699A CN 113595053 A CN113595053 A CN 113595053A
- Authority
- CN
- China
- Prior art keywords
- circuit
- power
- power supply
- fuse
- low
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004891 communication Methods 0.000 claims abstract description 59
- 238000012544 monitoring process Methods 0.000 claims 1
- 239000003381 stabilizer Substances 0.000 abstract description 11
- 230000007306 turnover Effects 0.000 abstract description 3
- 230000000694 effects Effects 0.000 description 3
- 238000000034 method Methods 0.000 description 3
- 238000012937 correction Methods 0.000 description 2
- 230000003068 static effect Effects 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000012938 design process Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000020169 heat generation Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000005259 measurement Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02J—CIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
- H02J1/00—Circuit arrangements for dc mains or dc distribution networks
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01J—MEASUREMENT OF INTENSITY, VELOCITY, SPECTRAL CONTENT, POLARISATION, PHASE OR PULSE CHARACTERISTICS OF INFRARED, VISIBLE OR ULTRAVIOLET LIGHT; COLORIMETRY; RADIATION PYROMETRY
- G01J1/00—Photometry, e.g. photographic exposure meter
- G01J1/42—Photometry, e.g. photographic exposure meter using electric radiation detectors
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01J—MEASUREMENT OF INTENSITY, VELOCITY, SPECTRAL CONTENT, POLARISATION, PHASE OR PULSE CHARACTERISTICS OF INFRARED, VISIBLE OR ULTRAVIOLET LIGHT; COLORIMETRY; RADIATION PYROMETRY
- G01J1/00—Photometry, e.g. photographic exposure meter
- G01J1/42—Photometry, e.g. photographic exposure meter using electric radiation detectors
- G01J1/4204—Photometry, e.g. photographic exposure meter using electric radiation detectors with determination of ambient light
Abstract
The invention discloses a low-power consumption sensing chip without clock standby, which relates to the field of chips.A power domain division is made in the low-power consumption sensing chip, a power management circuit and a communication register circuit are arranged in a normally open power domain, and other circuits including a clock circuit are arranged in a controllable power domain controlled by the power management circuit, so that the low-power consumption sensing chip can realize external communication and register configuration without requiring any on-chip clock in a standby mode. Because the turnover rate of the part of logic is very low, the dynamic power consumption only accounts for a very small part of the total power consumption, the promotion of the dynamic power consumption is smaller than the saved leakage power consumption of the voltage stabilizer, and finally the total power consumption is reduced.
Description
Technical Field
The invention relates to the field of chips, in particular to a low-power-consumption sensing chip without clock standby.
Background
Sensing chips such as infrared proximity and ambient light brightness sensing chips have been increasingly and widely installed in mobile phones, televisions or portable devices, and as the functions of the chips are continuously expanded, the power consumption of high-performance chips is large, which causes the problems of weak cruising ability and serious heat generation of the whole device, so that how to reduce the overall power consumption of the sensing chips and prolong the service life of the system is a key point in the design process of the sensing chips.
Disclosure of Invention
The present invention provides a low power consumption sensing chip without clock standby for solving the above problems and technical requirements, and the technical solution of the present invention is as follows:
a low power consumption sensing chip without clock standby, the low power consumption sensing chip comprising: the power supply management circuit, the communication register circuit, the sensing analog circuit, the digital control circuit, the clock circuit and the fuse circuit are connected, the communication register circuit is connected with the communication pin, the communication register circuit is connected with the power supply management circuit, the digital control circuit and the fuse circuit, the digital control circuit is connected with the sensing analog circuit, and the clock circuit is used for providing an on-chip clock;
the power management circuit and the communication register circuit are normally powered by a normally open power supply of a normally open power supply domain, the sensing analog circuit, the digital control circuit, the clock circuit and the fuse circuit are powered by a power supply of a controllable power supply domain, and the on-off of the power supply of the controllable power supply domain is controlled by the power management circuit;
when the low-power-consumption sensing chip is in a standby mode, the power supply management circuit controls the power supply of the controllable power supply domain to be switched off, and the low-power-consumption sensing chip performs external communication and/or register configuration by utilizing the communication pin through the communication register circuit on the basis of no on-chip clock.
The controllable power domain comprises a fuse wire power domain and a main power domain, the fuse wire circuit is powered by a fuse wire power supply of the fuse wire power domain, the sensing analog circuit, the digital control circuit and the clock circuit are powered by the main power supply of the main power domain, the power management circuit respectively controls the on-off of the fuse wire power supply and the main power supply, and when the low-power-consumption sensing chip is in a standby mode, the power management circuit controls the fuse wire power supply and the main power supply to be off.
When the low-power-consumption sensing chip is in a fuse mode, the power management circuit controls the fuse power supply and a main power supply to be conducted, the clock circuit provides an on-chip clock for the fuse circuit, and the fuse circuit burns or reads fuse data;
when the low-power sensing chip is in the sensing mode, the power management circuit controls the fuse wire power supply to be disconnected and the main power supply to be connected, and the low-power sensing chip executes sensing operation.
The low-power-consumption sensing chip enters a fuse mode to read fuse data after being electrified, and the low-power-consumption sensing chip is switched between a standby mode and a sensing mode according to an external switching instruction received by a communication register circuit after the fuse data is read.
The fuse circuit comprises a fuse controller and a fuse device, wherein the fuse controller is respectively connected with the communication register circuit and the fuse device.
The low-power consumption sensing chip further comprises a linear voltage stabilizer working in the main power domain, wherein the linear voltage stabilizer is used for converting the first power supply into the second power supply;
the sensing analog circuit comprises a high-voltage analog circuit and a low-voltage analog circuit which are connected, the high-voltage analog circuit is powered by a first power supply of the main power supply domain, and the low-voltage analog circuit, the digital control circuit and the clock circuit are powered by a second power supply of the main power supply domain.
The low-power consumption sensing chip further comprises an interrupt control circuit powered by a second power supply of the main power supply domain, wherein the interrupt control circuit is connected with the communication register circuit and the digital control circuit, and is also connected with an interrupt pin.
The further technical scheme is that the communication register circuit is constructed based on high-threshold transistors.
The communication registering circuit comprises an I2C interface and a register which are connected, the I2C interface is connected with a communication pin, the communication pin comprises an SCL pin and an SDA pin of an I2C bus, and when the low-power sensing chip is in a standby mode, the power management circuit and the communication registering circuit work by depending on an SCL clock of the I2C bus.
The beneficial technical effects of the invention are as follows:
the application discloses low-power consumption sensing chip of no clock standby, this low-power consumption sensing chip is inside to be done the power domain and is divided, puts power management circuit and communication register circuit in normally open power domain, and other circuits including clock circuit are put in the controllable power domain who is controlled by power management circuit to make this low-power consumption sensing chip can need not to ask any on-chip clock just can realize external communication and register configuration under standby mode, effectively reduce the consumption.
Meanwhile, the method is different from the method that all digital logics are placed in a low-voltage domain by a traditional chip, and a part of digital logics including a power management circuit and a communication register circuit are placed in a high-voltage domain, so that the part of digital logics do not need to be used in a voltage stabilizer, and the leakage power consumption of the voltage stabilizer can not be generated. Because the turnover rate of the part of logic is very low, the dynamic power consumption only accounts for a very small part of the total power consumption, the promotion of the dynamic power consumption is smaller than the saved leakage power consumption of the voltage stabilizer, and finally the total power consumption is reduced.
Furthermore, the HVT transistor is adopted to realize the digital logic of the high-voltage domain, so that the leakage power consumption can be reduced on the basis of not influencing the operation of the chip, and finally, the power consumption of the digital logic of the high-voltage domain is further reduced.
The controllable power domain can be further divided into a fuse power domain and a main power domain, and the fuse power domain can be completely powered off after the access of the fuse circuit is finished so as to achieve the effect of 0 power consumption. When the main power domain is powered on and enters the sensing mode, the fuse circuit is powered off, and can be switched back to the standby mode from the sensing mode in time, so that the power consumption can be effectively reduced compared with the traditional chip.
Drawings
Fig. 1 is a schematic diagram of an internal structure of a low power consumption sensing chip according to the present application.
Detailed Description
The following further describes the embodiments of the present invention with reference to the drawings.
The application discloses a low power consumption sensing chip of no clock standby, please refer to fig. 1, the low power consumption sensing chip includes: the circuit comprises a power management circuit, a communication register circuit, a sensing analog circuit, a digital control circuit, a clock circuit and a fuse circuit. The communication registering circuit is connected with the communication pin, the communication registering circuit is connected with the power management circuit, the digital control circuit and the fuse circuit, and the digital control circuit is connected with the sensing analog circuit. The low-power consumption sensing chip further comprises an interrupt control circuit, the interrupt control circuit is connected with the communication register circuit and the digital control circuit, and the interrupt control circuit is further connected with an interrupt pin INT. Wherein:
(1) the communication register circuit comprises an I2C interface and a register which are connected, the I2C interface is connected with communication pins, and the communication pins comprise an SCL pin and an SDA pin of an I2C bus. The I2C interface is used for external communication, and the register is used for storing configuration and status information.
(2) The sensing analog circuit mainly comprises a photodiode, an analog-to-digital converter and an LED driver, so that the sensing chip is realized as an infrared proximity and ambient light brightness sensing chip. The sensing analog circuit comprises a high-voltage analog circuit and a low-voltage analog circuit which are connected, wherein the high-voltage analog circuit mainly comprises an LED driver, and actually possibly comprises an IO pin, a band-gap reference power supply and the like, and the low-voltage analog circuit mainly comprises a photodiode and an analog-to-digital converter.
(3) The digital control circuit comprises a state machine and corresponding control logic, and is used for managing the sensing analog circuit, controlling data return and the like.
(4) The clock circuit is used for providing an on-chip clock, and mainly comprises an oscillator and a clock controller, wherein the oscillator is used for generating the on-chip clock, and the clock controller is used for branching, opening/closing, frequency dividing and generating reset signals of the on-chip clock.
(5) The fuse circuit comprises a fuse controller and a fuse device, and the fuse controller is respectively connected with the communication register circuit and the fuse device. The fuse device can be written once for storing the correction data, and the fuse controller generates the interface read-write signal timing sequence of the fuse.
(6) The interrupt control circuit is used for generating an interrupt signal in time and informing an external microcontroller to perform corresponding processing through an interrupt pin INT.
The power management circuit and the communication register circuit are powered by a normally open power supply of a normally open power domain PD0, the sensing analog circuit, the digital control circuit, the clock circuit and the fuse circuit are powered by a power supply of a controllable power domain, and the on-off of the power supply of the controllable power domain is controlled by the power management circuit.
When the low-power consumption sensing chip is completely powered off, the normally-open power supply of the normally-open power supply domain PD0 and the power supply of the controllable power supply domain are both powered off, and the normally-open power supply domain PD0 is a high-voltage power domain, and is a 3.3V power supply domain in a relatively typical mode. When the low-power-consumption sensing chip normally supplies power, the normally open power of the normally open power domain PD0 is always turned on, the power management circuit controls the power supply disconnection of the controllable power domain to enable the low-power-consumption sensing chip to be in a standby mode, at the moment, other circuit structures are powered off except the communication registering circuit and the power management circuit, all logics are static without turning, the clock is static, and the power consumption is reduced. But the low power consumption sensing chip is externally communicated with a communication register circuit by using a communication pin and/or performs register configuration on the basis of no on-chip clock. That is, the low power consumption sensing chip can normally receive external commands and register configuration process in the standby mode without requesting any on-chip clock, and the power management circuit and the communication register circuit operate by means of the SCL clock of the I2C bus.
Further, the communication register circuit is constructed based on high threshold (HVT) transistors, and since the communication register circuit is operated at a very low frequency (<10MHz), the HVT transistors are relatively slow and cannot affect the chip, and the HVT transistors can reduce leakage power consumption. In addition, the communication registering circuit and the power management circuit do not need to use voltage stabilizers, so that the leakage power consumption of the voltage stabilizers cannot be generated, the dynamic power consumption only accounts for a very small part of the total power consumption due to the low turnover rate of the communication registering circuit and the power management circuit, the promotion of the dynamic power consumption is smaller than the saved leakage power consumption of the voltage stabilizers, and finally the total power consumption is reduced. Therefore, in the standby mode, if no external access exists, the low-power-consumption sensing chip can basically realize 0 dynamic power consumption and minimum leakage power consumption, compared with the traditional operation mode, the power consumption is greatly reduced, and the power consumption can be reduced by more than 90% through actual measurement.
Further, the controllable power domains include a fuse power domain PD1 and a main power domain PD2, the fuse circuit is powered by the fuse power of the fuse power domain PD1, and the sensing analog circuit, the digital control circuit, the clock circuit, and the interrupt control circuit are powered by the main power of the main power domain PD 2. The voltage of the fuse power supply is equal to that of the normally-open power supply, and is also a high-voltage domain, namely the 3.3V power domain. The low-power-consumption sensing chip further comprises a linear voltage stabilizer working in the main power supply domain, wherein the linear voltage stabilizer is used for converting the first power supply into the second power supply, for example, the normally open power supply, the fuse wire power supply and the first power supply are all 3.3V, and the second power supply is 1.6V. The high voltage analog circuit is powered by a first power supply of the main power domain, and the low voltage analog circuit, the digital control circuit, the clock circuit and the interrupt control circuit are powered by a second power supply of the main power domain.
The power supply management circuit respectively controls the on-off of the fuse power supply and the main power supply, so that the working states of the fuse circuit and other circuits can be independently controlled. When the low-power consumption sensing chip is in a standby mode, the power management circuit controls the fuse power supply and the main power supply to be disconnected, so that the controllable power domain is disconnected. Since the fuse power domain PD1 and the main power domain PD2 can be controlled to operate independently, further, the low power consumption sensing chip further includes a fuse mode and a sensing mode:
when the low-power-consumption sensing chip is in the fuse mode, the power management circuit controls the fuse power supply and the main power supply to be conducted, the clock circuit working on the main power supply provides an on-chip clock for the fuse circuit, and the fuse circuit burns or reads fuse data. The fuse data can be written only once in the production process, and is used for storing the fuse data and writing correction data. Reading fuse data typically reads calibration data when the chip is powered on. After the access to the fuse circuit is finished, the fuse power supply can be completely powered off to achieve the effect of 0 power consumption.
When the low power consumption sensing chip is in the sensing mode, the power management circuit controls the fuse power supply to be disconnected and the main power supply to be connected, each part of the circuit working in the main power supply domain PD2 normally works, and the low power consumption sensing chip performs the sensing operation, that is, enters the normal working state.
Therefore, the low-power sensing chip comprises four working modes: off mode, fuse mode, standby mode, and sense mode: in the off mode, the external power supply is disconnected, and the normally-on power domain PD0, the fuse power domain PD1, and the main power domain PD2 are all turned off. In the fuse mode, the external power supply is turned on, and the normally-on power domain PD0, the fuse power domain PD1, and the main power domain PD2 are all turned on. In the standby mode, the external power supply is turned on, the normally-on power domain PD0 is turned on, and both the fuse power domain PD1 and the main power domain PD2 are turned off. In the sensing mode, the external power supply is turned on, the normally-on power domain PD0 and the main power domain PD2 are turned on, and the fuse power domain PD1 remains turned off. Please refer to the following table.
When the low-power sensing chip actually works, the low-power sensing chip is in a shutdown mode when the low-power sensing chip is completely powered off, and after the low-power sensing chip is normally powered on, the low-power sensing chip generally enters a fuse mode to read fuse data. And after the fuse data is read, switching between a standby mode and a sensing mode according to an external switching instruction received by the communication register circuit. In general, the fuse data is read and then enters the standby mode. The sensing mode is entered when an external switching instruction received through the communication register circuit indicates to start sensing. When the external switching instruction received by the communication register circuit indicates the end of sensing, the standby mode is entered again in time to reduce power consumption, so as to circulate. And returning to the off mode until the low-power sensing chip is powered down.
What has been described above is only a preferred embodiment of the present application, and the present invention is not limited to the above embodiment. It is to be understood that other modifications and variations directly derivable or suggested by those skilled in the art without departing from the spirit and concept of the present invention are to be considered as included within the scope of the present invention.
Claims (9)
1. A low power consumption sensing chip without clock standby, the low power consumption sensing chip comprising: the power supply monitoring circuit comprises a power supply management circuit, a communication registering circuit, a sensing analog circuit, a digital control circuit, a clock circuit and a fuse circuit, wherein the communication registering circuit is connected with a communication pin, the communication registering circuit is connected with the power supply management circuit, the digital control circuit and the fuse circuit, the digital control circuit is connected with the sensing analog circuit, and the clock circuit is used for providing an on-chip clock;
the power management circuit and the communication register circuit are normally powered by a normally open power supply of a normally open power supply domain, the sensing analog circuit, the digital control circuit, the clock circuit and the fuse circuit are powered by a power supply of a controllable power supply domain, and the on-off state of the power supply of the controllable power supply domain is controlled by the power management circuit;
when the low-power-consumption sensing chip is in a standby mode, the power supply management circuit controls the power supply of the controllable power supply domain to be switched off, and the low-power-consumption sensing chip performs external communication and/or register configuration by utilizing the communication pin through the communication register circuit on the basis of no on-chip clock.
2. The low power consumption sensing chip of claim 1, wherein the controllable power domains comprise a fuse power domain and a main power domain, the fuse circuit is powered by a fuse power source of the fuse power domain, the sensing analog circuit, the digital control circuit and the clock circuit are powered by a main power source of the main power domain, the power management circuit controls on and off of the fuse power source and the main power source respectively, and when the low power consumption sensing chip is in a standby mode, the power management circuit controls both the fuse power source and the main power source to be off.
3. The low power consumption sensing chip of claim 2,
when the low-power sensing chip is in a fuse mode, the power management circuit controls the fuse power supply and a main power supply to be conducted, the clock circuit provides an on-chip clock for the fuse circuit, and the fuse circuit burns or reads fuse data;
when the low-power sensing chip is in a sensing mode, the power management circuit controls the fuse power supply to be disconnected and the main power supply to be connected, and the low-power sensing chip executes sensing operation.
4. The low power consumption sensing chip of claim 3, wherein the low power consumption sensing chip enters a fuse mode after being powered on to read fuse data, and switches between the standby mode and the sensing mode according to an external switching instruction received through the communication register circuit after the fuse data is completely read.
5. The low power consumption sensing chip according to claim 2, wherein the fuse power supply has a voltage equal to that of the normally-on power supply, the fuse circuit includes a fuse controller and a fuse device, and the fuse controller is connected to the communication register circuit and the fuse device, respectively.
6. The low power consumption sensing chip according to claim 2, wherein a main power supply of the main power domain comprises a first power supply and a second power supply with the same on-off state, a voltage of the first power supply is equal to that of the normally-open power supply, and a voltage of the second power supply is lower than that of the normally-open power supply, and the low power consumption sensing chip further comprises a linear regulator operating in the main power domain, wherein the linear regulator is configured to convert the first power supply into the second power supply;
the sensing analog circuit comprises a high-voltage analog circuit and a low-voltage analog circuit which are connected, the high-voltage analog circuit is powered by a first power supply of the main power supply domain, and the low-voltage analog circuit, the digital control circuit and the clock circuit are powered by a second power supply of the main power supply domain.
7. The low power consumption sensing chip of claim 6, further comprising an interrupt control circuit powered by a second power supply of the primary power domain, the interrupt control circuit connected to the communication register circuit and the digital control circuit, the interrupt control circuit further connected to an interrupt pin.
8. The low power consumption sensing chip according to any one of claims 1 to 7, wherein the communication register circuit is constructed based on high threshold transistors.
9. The low power consumption sensing chip according to any one of claims 1-7, wherein the communication register circuit comprises an I2C interface and a register connected together, the I2C interface connects the communication pins, the communication pins comprise an SCL pin and an SDA pin of an I2C bus, and the power management circuit and the communication register circuit operate according to an SCL clock of an I2C bus when the low power consumption sensing chip is in a standby mode.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110966699.7A CN113595053A (en) | 2021-08-23 | 2021-08-23 | Low-power consumption sensing chip of no clock standby |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110966699.7A CN113595053A (en) | 2021-08-23 | 2021-08-23 | Low-power consumption sensing chip of no clock standby |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN113595053A true CN113595053A (en) | 2021-11-02 |
Family
ID=78239315
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202110966699.7A Pending CN113595053A (en) | 2021-08-23 | 2021-08-23 | Low-power consumption sensing chip of no clock standby |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN113595053A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114236230A (en) * | 2021-12-13 | 2022-03-25 | 广西电网有限责任公司电力科学研究院 | Design method for optimizing power consumption and stably supplying power for multiple voltage domains of power quality chip |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102902350A (en) * | 2012-11-13 | 2013-01-30 | 江苏东大集成电路系统工程技术有限公司 | Chip extra-low in standby power consumption |
| DE102014114681A1 (en) * | 2013-11-08 | 2015-05-13 | Intel Corporation | Power Management for a Physical Layer Interface Connect a display to a display transmission system |
| CN110334445A (en) * | 2019-07-05 | 2019-10-15 | 上海华虹集成电路有限责任公司 | A kind of control method of low power dissipation design |
| CN111474876A (en) * | 2019-01-23 | 2020-07-31 | 瑞萨电子株式会社 | Semiconductor device and semiconductor system |
| CN112214450A (en) * | 2020-10-12 | 2021-01-12 | 湃方科技(天津)有限责任公司 | Edge intelligent SOC processor and electronic equipment |
-
2021
- 2021-08-23 CN CN202110966699.7A patent/CN113595053A/en active Pending
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102902350A (en) * | 2012-11-13 | 2013-01-30 | 江苏东大集成电路系统工程技术有限公司 | Chip extra-low in standby power consumption |
| DE102014114681A1 (en) * | 2013-11-08 | 2015-05-13 | Intel Corporation | Power Management for a Physical Layer Interface Connect a display to a display transmission system |
| CN104635909A (en) * | 2013-11-08 | 2015-05-20 | 英特尔公司 | Power management for a physical layer interface connecting a display panel to a display transmit engine |
| CN111474876A (en) * | 2019-01-23 | 2020-07-31 | 瑞萨电子株式会社 | Semiconductor device and semiconductor system |
| JP2020119187A (en) * | 2019-01-23 | 2020-08-06 | ルネサスエレクトロニクス株式会社 | Semiconductor device and semiconductor system |
| CN110334445A (en) * | 2019-07-05 | 2019-10-15 | 上海华虹集成电路有限责任公司 | A kind of control method of low power dissipation design |
| CN112214450A (en) * | 2020-10-12 | 2021-01-12 | 湃方科技(天津)有限责任公司 | Edge intelligent SOC processor and electronic equipment |
Non-Patent Citations (1)
| Title |
|---|
| 李勋等: "《AVR单片机应用技术》", 北京航空航天大学出版社, pages: 63 - 71 * |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114236230A (en) * | 2021-12-13 | 2022-03-25 | 广西电网有限责任公司电力科学研究院 | Design method for optimizing power consumption and stably supplying power for multiple voltage domains of power quality chip |
| CN114236230B (en) * | 2021-12-13 | 2023-10-24 | 广西电网有限责任公司电力科学研究院 | Multi-voltage-domain power consumption optimization and stable power supply design method for power quality chip |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US10365704B2 (en) | Discrete power control of components within a computer system | |
| US7279927B2 (en) | Integrated circuit with multiple power domains | |
| US7979724B2 (en) | System and method for dynamically managing power consumption of integrated circuitry | |
| US7673163B2 (en) | Semiconductor integrated circuit device with power source areas | |
| CN100462898C (en) | CPU powerdown method and apparatus therefor | |
| JP3150567U (en) | Electronic device that reduces power consumption when computer motherboard shuts down | |
| US7882376B2 (en) | Power control for a core circuit area of a semiconductor integrated circuit device | |
| CN103838349A (en) | Power supply control system and method thereof | |
| CN102998982A (en) | Power control circuit, semiconductor device including the same | |
| CN102147652A (en) | Shut-down energy-saving system and shut-down energy-saving method | |
| CN101853067B (en) | Methods for reducing power consumption and a device with an embedded memory module | |
| CN116700412A (en) | Low-power consumption system, microcontroller, chip and control method | |
| US20110099389A1 (en) | Stand-by power system for information handling systems | |
| US20100250983A1 (en) | Power saving control system | |
| US11372470B2 (en) | Control system for controlling intelligent system to reduce power consumption based on bluetooth device | |
| CN113595053A (en) | Low-power consumption sensing chip of no clock standby | |
| CN219574672U (en) | Low-power consumption system, microcontroller and chip | |
| US8762753B2 (en) | Power management circuit using two configuration signals to control the power modes of two circuit modules using two crosslinked multiplexers and a level shifter | |
| CN205540550U (en) | ATX power switching over structure based on digital power supply | |
| WO2006026627A2 (en) | On-chip power regulator for ultrta low leakage current | |
| US9348770B1 (en) | Non-volatile semiconductor memory device with temporary data retention cells and control method thereof | |
| CN214069905U (en) | Multi-power-supply chip control circuit and electronic equipment | |
| CN111880442A (en) | MCU with low standby power consumption and method thereof | |
| CN105451309B (en) | SIM card control system and method | |
| US9477300B2 (en) | Bridging device and power saving method thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination |