CN101853067B - Methods for reducing power consumption and a device with an embedded memory module - Google Patents
Methods for reducing power consumption and a device with an embedded memory module Download PDFInfo
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- CN101853067B CN101853067B CN2010101211980A CN201010121198A CN101853067B CN 101853067 B CN101853067 B CN 101853067B CN 2010101211980 A CN2010101211980 A CN 2010101211980A CN 201010121198 A CN201010121198 A CN 201010121198A CN 101853067 B CN101853067 B CN 101853067B
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/26—Power supply means, e.g. regulation thereof
- G06F1/32—Means for saving power
- G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
- G06F1/3234—Power saving characterised by the action undertaken
- G06F1/325—Power saving in peripheral device
- G06F1/3275—Power saving in memory, e.g. RAM, cache
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/26—Power supply means, e.g. regulation thereof
- G06F1/32—Means for saving power
- G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
- G06F1/3206—Monitoring of events, devices or parameters that trigger a change in power modality
- G06F1/3215—Monitoring of peripheral devices
- G06F1/3225—Monitoring of peripheral devices of memory devices
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Abstract
A method for reducing power consumption and a device with an embedded memory module are provided. The method is used to the device with an embedded memory module. The method comprises the steps of partitioning the embedded memory module into a plurality of memory blocks; segmenting an instruction set and a data set of a software module into a plurality of segments in accordance with the first predetermined rule, wherein the first predetermined rule is determined according the operation requirement; and loading the plurality of segments into the plurality of plurality of memory blocks. The plurality of memory blocks are switched on or off individually in accordance with a condition. The invention can switch off at least one memory block corresponding to the null instruction or data to achieve the object of save power when the processor is at the complete operation mode.
Description
Technical field
The invention relates to method that reduces rating of set consumption and device with embedded memory module; More specifically; Be about a kind of method, be used to adopt system on chip (System On Chip, device SOC); When system on chip was in complete operation mode, this method was used to reduce its power consumption.
Background technology
Modern system on chip (SOC) is to be used for high speed processing, and comprises one or more processor cores (processor cores), and the storer that directly is connected (directly attach) or couples with above-mentioned one or more processor cores.Nowadays, modern SOC utilizes the manufacturing of sophisticated semiconductor technology, to reach width and the length that significantly reduces transistor gate (transistor gates)., because modern SOC has the more manufacturing of deep-sub-micrometer field (deeper sub-micro region), cause the increase of static leakage current (static leakage current).
Therefore, for the device that adopts modern SOC, saving power consumption is an important indicator.For conventional power consumption method, adopt the device of modern SOC can operate in operator scheme (operation mode) or power saving mode (power saving mode).When device was in operator scheme, voltage source must continue power supply to the storer of the one or more processor cores that are connected directly to device to be provided.As a result, the static leakage current of direct-connected storer (static current leakage) is one of voltage source main electric leakage flow point of the device that is in operator scheme.When device is in power dissipation modes, modern SOC no longer operates in maximum clock speed, and wherein the operating frequency of modern SOC will be lower or ends (halt).
Therefore, need a kind of method and system to reduce power consumption, when system remains on operator scheme, can save power.
Summary of the invention
For the problem of the power consumption of resolution system, the present invention provides a kind of device that reduces the method for rating of set consumption and have embedded memory module.
The present invention provides a kind of method that rating of set consumes that reduces, and wherein device comprises embedded memory module, and said method comprises: dividing embedded memory module is a plurality of memory blocks; Instruction group and the data set of dividing software module according to first established rule are a plurality of sections, and wherein first established rule determines according to operational requirements; And section is written in the memory block; Wherein memory block is opened respectively or is closed according to condition.
The present invention provides a kind of method that rating of set consumes that reduces in addition, and wherein device comprises embedded memory module, and said method comprises: instruction group and the data set of dividing software module are a plurality of sections; Dividing embedded memory module according to first established rule is a plurality of memory blocks, and wherein first established rule is according to the size decision of section; And section is written in the memory block; Wherein open or close memory block respectively according to condition.
The present invention provides the device with embedded memory module in addition, comprises: processor; The embedded memory module of processor access, wherein embedded memory module is divided into a plurality of memory blocks according to first established rule; Software module comprises instruction group and data set, and wherein software module is divided into a plurality of sections according to second established rule; Power supply unit is used to provide power supply to a plurality of memory blocks; And the auxiliary logic module, being used to control power supply unit, the power supply that wherein is supplied to memory block is opened or is closed according to condition.
Utilize the present invention can be capable of using to be under the complete operation mode when processor, at least one memory block of closing instruction and the data of corresponding not usefulness is reached the purpose of power-saving.
Description of drawings
Fig. 1 shows the embodiment synoptic diagram of the device that reduces power consumption.
Fig. 2 shows the division synoptic diagram of embedded memory module.
Fig. 3 shows the process flow diagram of the embodiment of the method that reduces rating of set consumption.
Fig. 4 shows the embodiment process flow diagram of the method for the power consumption that reduces device.
Embodiment
In the middle of instructions and claims, used some vocabulary to call specific element.Those skilled in the art should understand, and hardware manufacturer may be called same element with different nouns.This instructions and claims are not used as distinguishing the mode of element with the difference of title, but the criterion that is used as distinguishing with the difference of element on function.Be open term mentioned " comprising " in the middle of instructions and claims in the whole text, so should be construed to " comprise but be not limited to ".In addition, " coupling " speech is to comprise any indirect means that are electrically connected that directly reach at this.Therefore, be coupled to second device, then represent first device can directly be electrically connected in second device, or be connected electrically to second device through other device or the intersegmental ground connection of connection hand if describe first device in the literary composition.
The present invention provides a kind of device that reduces power consumption.Fig. 1 shows the embodiment synoptic diagram of the device that reduces power consumption, and device 1 comprises processor 10, embedded memory module (embedded memory module) 11, power supply unit 12, and auxiliary logic module (auxiliary logic) 13.Embedded memory module 11 couples with processor 10, and can be processed device 10 accesses.In this embodiment; Embedded memory module 11 is a Direct Attached Storage device (directly-attached memory); Itself and processor 10 couple and operate in monocycle tupe (single cycle execution), the storer that for example closely couples.As shown in Figure 2, Fig. 2 shows the division synoptic diagram of embedded memory module, and embedded memory module 11 is divided into a plurality of memory block MB# 0～MB#n.The data set (data set) of the software module that instruction group (instruction set) the and instruction group of the software module that processor 10 is carried out is used is divided into a plurality of sections (segment).Section is written into memory block.
According to this embodiment, supply with the power supply of memory block MB# 0～MB#n and can control respectively.Therefore, when processor 10 is under the complete operation mode, can reach power-saving through closing the corresponding not instruction of usefulness and at least one memory block of data.
As shown in Figure 1, device 1 more comprises second memory 14, is coupled to embedded memory module 11.Second memory 14 stores the section of pent at least one memory block of power supply.For instance, the power supply of supposing to supply with memory block MB# 1 is decided to be according to memory access mode closes.Before power provided unit 12 to close to supply with the power supply of memory block MB# 1, the section of memory block MB# 1 was transferred to second memory 14 and stores.Supplying with the power supply of memory block MB# 1 can open according to another memory access mode.Simultaneously, be transferred to the section relevant with memory block MB# 1 of second memory 14, after power supply unit 12 unlatchings were supplied to the power supply of memory block MB# 1, above-mentioned section was got back to memory block MB# 1 from second memory 14 transmission again before.
In this embodiment, auxiliary logic module 13 control power supply units 12 are to open or to close the power supply that all supply with memory block MB# 1～MB#n respectively.In some embodiments; When keeping remaining memory block is when always opening (always-on state) state; Auxiliary logic module 13 control power supply units 12; To switch the power supply of supplying with some blocks among memory block MB# 1～MB#n respectively according to different event or condition, incident or condition memory access mode for example wherein.
In the embodiment of Fig. 1, processor 10 all is in the system on chip with storer 12.And in the embodiment of Fig. 1, auxiliary logic module 13 is coupled to processor 10.In some embodiments, auxiliary logic module 13 can be included in the processor 10.
Fig. 3 shows the process flow diagram of the embodiment of the method that reduces rating of set consumption.Said method can describe with reference to figure 1-3.At first, embedded memory module 11 is divided into a plurality of memory block MB# 0～MB#n (step S30).In this embodiment, the size of each memory block is all by predetermined.In simple terms, the size of each memory block mean allocation all in the embedded memory module 11 in this embodiment, but this and should not be construed as a limitation of the present invention.The data set of the employed software module of instruction group (instruction set) and instruction group of the software module that processor 10 is performed is divided into a plurality of sections (step S31) according to first established rule.For instance, when the embedded memory module 11 of 128MB was divided into the memory block of four 32MB, instruction group and data set also were divided into the section of four 32MB.And instruction group and data set can further be divided section according to operational requirements, and operational requirements can be: for example immediately/and non-real time operation; The instruction process possibility, instruction process frequency, storage access frequency; Type of memory, the perhaps power distribution of circuit design in the system.For instance; The instruction group of real time operation (real time operation) and data set can be divided at least one in four 32MB sections, (non-real time operation) the instruction group of non-real time operation and data set can by division advance in four 32MB sections remaining at least one.Section is written into memory block (step S32) respectively.In some other embodiments, according to set mode, section is written into memory block, and wherein set mode is written into a memory block for for example two sections.
Then; Based on second established rule; The condition of memory access mode or the sequential demand that is used to operate in the incident for example, for example low electric weight incident, it obtains through software administration message; Auxiliary logic module 13 can be controlled power supply unit 12, supplies to the wherein power supply of at least one memory block (step S33) of memory block MB# 1～MB#n to open respectively or to close.
In step S33; If the power supply that offers memory block is closed in the sequential demand decision according to storage access scheme or operation; The section of memory block can be closed at power supply unit 12 and provided to the power supply of above-mentioned memory block, is transferred to second memory 14 so that store.In addition; If sequential demand according to storage access scheme or operation; Decision is opened provides the power supply to memory block; Be transferred to the section relevant of second memory 14 before, can after power supply unit 12 is opened the above-mentioned memory block of supply, be stored to above-mentioned memory block again from second memory 14 with above-mentioned memory block.
Fig. 4 shows the embodiment process flow diagram of the method for the power consumption that reduces device.Said method can be explained according to Fig. 1-2 and Fig. 4.At first; The instruction group of the software module of being carried out by processor 10 and the data set of the software module that the instruction group is used are divided into a plurality of sections (step S40) according to operational requirements; Wherein operational requirements can be immediately/non-real time operation, handles possibility, or handles frequency.For instance, the instruction group of the instruction group of real time operation and data set and non-real time operation and data set are divided into section respectively.Embedded memory module 11 is divided into a plurality of memory cells (step S41).The quantity of the memory cell of each section decides according to the division of instruction group and data set, and the size of each section for example, and the memory cell of decision quantity is grouped (grouped) is with as corresponding stored device block (step S42).Therefore, the size of memory block can be different sizes.Section is written into (step S43) in the memory block respectively.In some other embodiments; Packet mode (grouping pattern) can change to some extent; For example the first memory unit is grouped into first memory block; Second memory unit and the 3rd memory cell are grouped into the 3rd memory block, and the second memory block is left a blank because of other specific reasons.It is a plurality of memory blocks that group mode can be the first memory unit packet, or a plurality of memory cell is grouped into single memory block.
Based on the memory access mode of set incident (for example low electric weight) or the sequential demand of operation, auxiliary logic module 13 can be controlled power supply unit 12 and open or close the power supply that is supplied at least one memory block among memory block MB# 1～MB#n.
In step S44; If the power supply that is supplied to memory block is closed in the sequential demand decision according to memory access mode or operation, the section of memory block can be transferred to second memory 14 and store before power supply unit 12 is closed the power supply that offers memory block.In addition; If the sequential demand power supply according to memory access mode or operation decides the power supply of opening the supply memory block; After power supply unit 12 was opened the power supply of supplying with memory block, the section relevant with above-mentioned memory block that before had been transferred to second memory 14 can be stored into the memory block from second memory 14 again.
According to above-mentioned embodiment, the power supply that is supplied to memory block can be opened respectively or close.When processor 10 is in complete operation mode, be supplied to unused instruction and the memory of data block can be closed, so reduce the power consumption under the complete operation mode.
Though the present invention with the preferred embodiments explanation as above; Yet it is not to be used for limiting scope of the present invention; Any those skilled in the art are not breaking away from the spirit and scope of the present invention, any change and the change made; All in protection scope of the present invention, the scope that specifically defines with claim is as the criterion.
Claims (12)
1. one kind is reduced the method that rating of set consumes, and wherein said apparatus comprises embedded memory module, and the method for above-mentioned minimizing rating of set consumption comprises:
Dividing above-mentioned embedded memory module is a plurality of memory blocks;
Instruction group and the data set of dividing software module according to first established rule are a plurality of sections, and wherein above-mentioned first established rule determines according to operational requirements; And
Above-mentioned a plurality of section is written in above-mentioned a plurality of memory block;
Wherein above-mentioned a plurality of memory blocks are opened respectively or are closed according to condition.
2. the method that minimizing rating of set as claimed in claim 1 consumes is characterized in that above-mentioned condition determines according to control and management message.
3. the method that minimizing rating of set as claimed in claim 1 consumes is characterized in that above-mentioned condition determines according to memory access mode.
4. the method that minimizing rating of set as claimed in claim 1 consumes is characterized in that, the aforesaid operations demand is according to the size decision of above-mentioned a plurality of memory blocks.
5. one kind is reduced the method that rating of set consumes, and wherein said apparatus comprises embedded memory module, and the method for above-mentioned minimizing rating of set consumption comprises:
Instruction group and the data set of dividing software module are a plurality of sections;
Dividing above-mentioned embedded memory module according to first established rule is a plurality of memory blocks, and wherein above-mentioned first established rule is according to the size decision of above-mentioned a plurality of sections; And
Above-mentioned a plurality of section is written in above-mentioned a plurality of memory block;
Wherein open or close above-mentioned a plurality of memory block respectively according to condition.
6. the method for the power consumption of minimizing device as claimed in claim 5 is characterized in that, the above-mentioned steps of dividing above-mentioned embedded memory module comprises:
Dividing above-mentioned embedded memory module is a plurality of memory cells; And
According to the quantity of the memory cell of each above-mentioned a plurality of section of the size of each above-mentioned a plurality of section decision, wherein the memory cell of the above-mentioned quantity of decision is grouped with as corresponding stored device block.
7. device with embedded memory module comprises:
Processor;
The embedded memory module of above-mentioned processor access, wherein above-mentioned embedded memory module is divided into a plurality of memory blocks according to first established rule;
Software module comprises instruction group and data set, and wherein above-mentioned software module is divided into a plurality of sections according to second established rule;
Power supply unit is used to provide power supply to above-mentioned a plurality of memory blocks; And
The auxiliary logic module is used to control above-mentioned power supply unit, and the power supply that wherein is supplied to memory block is opened or closed according to condition.
8. the device with embedded memory module as claimed in claim 7 is characterized in that, above-mentioned first established rule determines that according to first operational requirements above-mentioned first operational requirements is according to the size decision of above-mentioned a plurality of memory blocks.
9. the device with embedded memory module as claimed in claim 7; It is characterized in that; Above-mentioned second established rule determines according to second operational requirements; And above-mentioned embedded memory module is divided into above-mentioned a plurality of memory block according to the division of above-mentioned instruction group and above-mentioned data set, and above-mentioned a plurality of section is written in above-mentioned a plurality of memory block.
10. the device with embedded memory module as claimed in claim 9 is characterized in that, above-mentioned second operational requirements is according to the size decision of above-mentioned a plurality of sections.
11. the device with embedded memory module as claimed in claim 7; It is characterized in that, more comprise be used for the above-mentioned power supply unit of above-mentioned auxiliary logic module controls with close be supplied to one of them power supply of above-mentioned a plurality of memory block before storage be transmitted the second memory of the section in the above-mentioned memory block that comes.
12. the device with embedded memory module as claimed in claim 11; It is characterized in that; The above-mentioned power supply unit of above-mentioned auxiliary logic module controls is opened after the power supply of supplying with above-mentioned memory block, and the section relevant with above-mentioned memory block is stored in the above-mentioned memory block from above-mentioned second memory again.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US12/413,713 US8127167B2 (en) | 2009-03-30 | 2009-03-30 | Methods for reducing power consumption and devices using the same |
| US12/413,713 | 2009-03-30 |
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| Publication Number | Publication Date |
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| CN101853067A CN101853067A (en) | 2010-10-06 |
| CN101853067B true CN101853067B (en) | 2012-12-26 |
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| CN2010101211980A Expired - Fee Related CN101853067B (en) | 2009-03-30 | 2010-03-10 | Methods for reducing power consumption and a device with an embedded memory module |
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| Country | Link |
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| US (1) | US8127167B2 (en) |
| CN (1) | CN101853067B (en) |
| TW (1) | TWI407303B (en) |
Families Citing this family (8)
| Publication number | Priority date | Publication date | Assignee | Title |
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| TWI493563B (en) * | 2012-01-06 | 2015-07-21 | Acer Inc | Memory managing method and electronic apparatus using the same |
| US20140189603A1 (en) * | 2012-12-28 | 2014-07-03 | Darryl L. Adams | Gesture Based Partition Switching |
| US8766707B1 (en) | 2013-03-15 | 2014-07-01 | Seagate Technology Llc | Integrated always on power island for low power mode operation |
| US9411394B2 (en) | 2013-03-15 | 2016-08-09 | Seagate Technology Llc | PHY based wake up from low power mode operation |
| US9335809B2 (en) | 2013-03-15 | 2016-05-10 | Seagate Technology Llc | Volatile memory storing system data during low power mode operation and monitoring the voltage supplied to the memory during low power mode |
| KR102275497B1 (en) * | 2014-10-20 | 2021-07-09 | 삼성전자주식회사 | System-on-chip including a power path controller and electronic device |
| US10539997B2 (en) | 2016-09-02 | 2020-01-21 | Qualcomm Incorporated | Ultra-low-power design memory power reduction scheme |
| US20210065758A1 (en) | 2019-08-29 | 2021-03-04 | Advanced Micro Devices, Inc. | Adaptable allocation of sram based on power |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6457108B1 (en) * | 1999-10-07 | 2002-09-24 | Monolithic System Technology, Inc. | Method of operating a system-on-a-chip including entering a standby state in a non-volatile memory while operating the system-on-a-chip from a volatile memory |
| JP2004133969A (en) * | 2002-10-08 | 2004-04-30 | Renesas Technology Corp | Semiconductor device |
| EP1623349B1 (en) * | 2003-05-07 | 2018-01-24 | Conversant Intellectual Property Management Inc. | Managing power on integrated circuits using power islands |
| US9384818B2 (en) | 2005-04-21 | 2016-07-05 | Violin Memory | Memory power management |
| CN100442203C (en) * | 2006-05-26 | 2008-12-10 | 中国科学院计算技术研究所 | Power consumption reduction method for intellectual core and functional module for chip system |
| US7930565B2 (en) * | 2006-09-11 | 2011-04-19 | Texas Instruments Incorporated | Power-optimizing memory analyzer, method of operating the analyzer and system employing the same |
| US8266464B2 (en) * | 2006-10-24 | 2012-09-11 | Texas Instruments Incorporated | Power controller, a method of operating the power controller and a semiconductor memory system employing the same |
| CN101174176A (en) * | 2006-11-03 | 2008-05-07 | 北京中电华大电子设计有限责任公司 | Low-power dissipation SOC circuit and method based on orderly-control |
| US7900069B2 (en) * | 2007-03-29 | 2011-03-01 | Intel Corporation | Dynamic power reduction |
| US7941682B2 (en) * | 2007-05-09 | 2011-05-10 | Gainspan, Inc. | Optimum power management of system on chip based on tiered states of operation |
| US8190931B2 (en) * | 2009-04-30 | 2012-05-29 | Texas Instruments Incorporated | Power management events profiling |
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2009
- 2009-03-30 US US12/413,713 patent/US8127167B2/en not_active Expired - Fee Related
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2010
- 2010-03-10 TW TW099106867A patent/TWI407303B/en not_active IP Right Cessation
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| Publication number | Publication date |
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| US20100250980A1 (en) | 2010-09-30 |
| CN101853067A (en) | 2010-10-06 |
| US8127167B2 (en) | 2012-02-28 |
| TW201035747A (en) | 2010-10-01 |
| TWI407303B (en) | 2013-09-01 |
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