TWI493563B - Memory managing method and electronic apparatus using the same - Google Patents

Description

Memory management method and electronic device using the same

The present invention relates to a memory management method, and more particularly to a memory management method capable of turning off an unused portion of a memory module to achieve a power saving effect.

In order to achieve power saving effect, many electronic devices in the present invention are in an idle state or a sleep mode, and some components of the device are turned off or stopped to reduce unnecessary power consumption, such as displaying a screen, a hard disk, a processor, and the like. However, as far as the memory is concerned, once the power is stopped, the dynamic data temporarily stored in the memory will be lost, which will cause an error in the device system. Therefore, if the memory needs to be turned off, the data originally stored in the memory must be stored first. Write to the hard disk, and then restore the data from the hard disk to the memory after the memory is restored.

Conventional technology, such as the Republic of China Patent No. I343519, which compresses the stored data in the memory to reduce the space used by the memory and power off some of the unused memory modules. The effect of the device's power consumption. However, this design must compress and decompress the data in the memory, which will increase the additional system processing and power consumption, but may increase the system load and fail to achieve the expected energy saving effect.

The main object of the present invention is to provide a memory management method capable of turning off an unused portion of a memory module to achieve a power saving effect.

To achieve the above objective, the memory management method of the present invention is applied to an electronic device, and the electronic device includes at least one memory module, a control module, and a power module for forming a plurality of memory blocks. The method includes the following steps: receiving, by the control module, an execution instruction; rearranging at least one data stored in the memory module according to the execution instruction, to store the at least one data in a single memory block or a plurality of consecutive In the memory block; and informing the power module to stop supplying power to other memory blocks not used in the plurality of memory blocks.

Furthermore, the present invention also provides an electronic device to which the aforementioned memory management method is applied. The electronic device includes at least one memory module, a control module, a processing module, and a power module. At least one memory module includes a plurality of memory blocks for storing at least one data, each data is stored in a plurality of data blocks in a plurality of data blocks; and the control module is configured to receive an execution instruction to rearrange Storing the at least one data in the at least one memory module to store the at least one data in a single memory block or a plurality of consecutive memory blocks; a plurality of memory blocks; the processing module is configured to issue an execution instruction, and after the control module completes at least one data rearrangement, notifying the power module to stop supplying power to other memory blocks not used in the plurality of memory blocks .

With the design of the present invention, when the electronic device is in an idle or dormant state, the data stored in the memory module can be rearranged and concentrated in a part of the memory block to use other memories not used in the memory module. The body block is powered off to achieve energy saving and power saving to reduce excess power consumption.

In order to enable the reviewing committee to better understand the technical contents of the present invention, the preferred embodiments are described below.

Please refer to FIG. 1 , which is a schematic diagram of a first embodiment of an electronic device 1 of the present invention. In various embodiments of the present invention, the electronic device is a portable computer or a desktop computer, but the electronic device may be another electronic device that can be configured with a memory module, depending on the type of application. This embodiment is limited.

As shown in FIG. 1 , the electronic device 1 of the present invention includes at least one memory module 10 , a control module 20 , a processing module 30 , and a power module 40 . The processing module 30 is electrically connected to each module. And the power supply required by each module is supplied by the power module 40. In this embodiment, at least one memory module 10 is a single memory module, which includes a plurality of memory blocks 11 to 18 for storing at least one data, and any data is formed by a plurality of data blocks. . Here, the memory module 10 can be regarded as a memory device, and each of the memory blocks 11 to 18 is a memory chip on the memory device, but the number and division of the memory blocks set on the memory device The method is not limited to this embodiment. For example, a plurality of adjacent memory chips may be regarded as the same memory block, or a memory chip having a smaller capacity and a smaller volume may be disposed on the memory device to increase the number of memory blocks, etc. Design needs vary from design to application.

The control module 20 is configured to receive an execution command to perform data transfer on at least one of the data stored in the at least one memory module 10. In each embodiment of the present invention, the control module 20 can be executed under the operating system. An application, or a hardware component that stores the application, such as a basic input/output system chip (BIOS) or a read-only memory (ROM), but is not limited to this embodiment.

The processing module 30 is configured to issue an execution command to the control module 20, and notify the power module 40 whether the memory blocks 11 to 18 of the at least one memory module 10 are normally powered. In this embodiment, the processing module 30 may include a central processing unit and/or an operating system stored in a storage device such as a hard disk; the central processing unit may first load the operating system, and when the operating system detects that it is idle, After the time is switched to the sleep state, the execution instruction notification control module 20 can be issued to enable the control module 20 to perform the action of rearranging the data of at least one memory module 10.

The power supply module 40 is configured to supply power required by each module, and controls the power supply of each of the memory blocks 11 to 18 corresponding to the at least one memory module 10 by the switches 51 to 58. After all the data stored in the at least one memory module 10 is rearranged, the control module 20 can notify the processing module 30 to instruct the power supply module 40 to stop powering the unused memory blocks. .

In order to ensure that the data stored in the memory module 10 can be correctly read, the system generates a mapping table in the memory module 10, and the corresponding data is used to record each data block of any data. The corresponding virtual memory address and the physical memory address actually stored in the corresponding memory blocks 11 to 18. Therefore, by using the corresponding data, the control module 20 can identify the memory block currently in use, and after the data block is moved, the system will modify to update the corresponding data to avoid data reading. The wrong situation.

Please refer to Figure 2 (a), (b) together. 2(a) is a schematic view of the memory module 10 of the first embodiment of the electronic device 1 of the present invention before data rearrangement; FIG. 2(b) is a memory of the first embodiment of the electronic device 1 of the present invention. The body module 10 performs a schematic diagram of rearranging the data.

As shown in FIG. 2(a), in general, when a plurality of data blocks of any data are stored in the plurality of memory blocks 11 to 18, in order to increase the data access speed, the device system will The plurality of data blocks are dispersedly stored in the respective memory blocks 11 to 18. In this embodiment, it is assumed that the data is a binary bit group, which is composed of 8 bits such as "01100111", and each bit can be regarded as a data block. Therefore, when the byte is stored in the memory module 10, each bit of the byte is stored in each of the memory blocks 11 to 18.

As shown in FIG. 1 and FIG. 2(b), when the control module 20 receives the execution command, the byte data stored in the memory module 10 is rearranged according to the execution command to perform the data for the data. The data block is moved between different memory blocks 11 to 18. In this embodiment, the control module 20 stores the original bits in the memory blocks 11 to 18, and rearranges the data to store the bits originally stored in the memory blocks 15 to 18. Stored in a plurality of consecutive memory blocks 11 to 14, as shown in FIG. 2(b); the control module 20 also updates the corresponding data to reflect the actual storage corresponding to each data block. position. Thereby, the data stored in the memory blocks 15 to 18 is emptied, and is in an unused state, that is, the unused memory blocks 15 are formed in the plurality of memory blocks 11 to 18 to 18.

The foregoing control module 20 can determine the contiguous memory block by reading a memory link information, and the memory link information can define the physical connection relationship between the memory blocks 11 to 18. For determining which memory blocks are adjacent to each other, contiguous memory blocks. The memory connection information can be stored in a hardware device that does not cause the data to disappear due to power failure, such as a BIOS, a ROM, or a hard disk device, but is not limited to this embodiment.

After the control module 20 completes the foregoing data rearrangement and vacates the unused memory blocks 15 to 18, the processing module 30 can be notified, and the processing module 30 will command the power module 40 to The memory blocks 15 to 18 used perform the action of stopping the power supply, so the power module 40 correspondingly turns off the switches 55 to 58 to interrupt the supply of the memory blocks 15 to 18. The design can achieve the effect of powering off part of the power supply part of the memory module 10 to save unnecessary power consumption.

Please refer to FIG. 3, which is a schematic diagram of a second embodiment of the electronic device 1a of the present invention. As shown in FIG. 3, in the embodiment, the electronic device 10 of the present invention includes two memory modules 10a, 10b, each of the memory modules 10a, 10b can be a memory device, and each memory device The whole can be regarded as a single memory block 11a or 11b, so that the two memory modules 10a, 10b form two different memory blocks 11a, 11b, but the number of the memory modules 10a, 10b is set to be included The number of memory blocks 11a, 11b is not limited to this embodiment. For example, the electronic device 1a may add more memory devices, or divide each memory device into two or more memory blocks, etc., depending on the design requirements.

As shown in FIG. 3, in the embodiment, when the electronic device 1a is provided with a plurality of memory modules 10a, 10b, when the plurality of data blocks of any data are to be stored in the memory modules 10a, 10b In order to improve the data access speed, the device system will divide the plurality of data blocks of the data into two parts and store them in the respective memory blocks 11a and 11b.

When the control module 20 receives the execution command, the data stored in the memory module 10a, 10b is rearranged according to the execution command, and the data blocks originally stored in the memory block 11b are collectively stored in a single unit. In the memory block 11a, the control module 20 also updates the corresponding data to reflect the actual storage location corresponding to each data block. Thereby, the data stored in the memory block 11b has been emptied, that is, the memory module 10b itself is in an unused state.

After the unused memory block 11b is vacated, the control module 20 can notify the processing module 30 to instruct the power module 40 to close the switch 50b to interrupt the power supply to the memory block 11b. The design can achieve the effect of powering off part of the power supply part for different memory modules 10 to save unnecessary power consumption.

Please refer to FIG. 4, which is a flowchart of an embodiment of a memory management method of the present invention. It should be noted that the memory management method of the present invention is described below by taking the electronic device 1 shown in FIG. 1 as an example, but the present invention is not limited to the electronic device 1, such as the foregoing electronic device 1a or any other device. Electronic devices of similar architecture may also be adapted to the method of the present invention. As shown in FIG. 2, the memory management method of the present invention includes steps S401 to S404. The various steps of the method are described in detail below.

Step S401: Receive an execution instruction.

After the processing module 30 of the electronic device 1 is loaded into the operating system, after the system is idle for a certain period of time or switched to the sleep state, the processing module 30 issues an execution command notification control module 20, and the control module 20 receives After the execution of the command, the energy-saving operation for the memory module 10 is prepared.

Step S402: Rearrange at least one data stored in the at least one memory module 10 according to the execution instruction to store the at least one data in a single memory block or a plurality of contiguous memory blocks.

After the control module 20 receives the execution instruction, the at least one stored data may be rearranged among the memory blocks of the at least one memory module according to the execution instruction, so that the data is moved and concentrated. In the memory block, for example, in the foregoing first embodiment, the data is concentrated in the contiguous memory block of the same memory module 10 (such as continuous memory blocks 11 to 14), or as in the foregoing second embodiment. The middleware data is concentrated on at least one of the plurality of memory modules 10a, 10b (such as the memory block 11a), so that the memory modules can free other unused memory blocks. It should be noted that, while the data is rearranged, the control module 20 also synchronously updates the corresponding data stored in the at least one memory module to ensure the physical memory address and virtual memory stored after the data is moved. Correspondence of body addresses to avoid errors when accessing data.

Step S403: Stop supplying power to other memory blocks that are not used in the plurality of memory blocks.

After the data of at least one memory module is rearranged and the unused memory blocks are vacated, the control module 20 can notify the processing module 30 to command the power module 40 to stop supplying power to the unpowered modules. The memory block is used; therefore, the power module 40 turns off the power switch corresponding to the memory blocks to achieve different power supply effects for different memory blocks or memory modules.

In addition, before step S402, step S404 may be further included: clearing all cache data in at least one memory module.

Before the control module 20 performs data rearrangement on the at least one memory module 10, the processing module 30 may be notified to perform the clearing operation of all the cached data in the at least one memory module to reduce the subsequent need to move the array. The amount of data. Since the electronic device 1 temporarily stores a large amount of cache data by using the memory module during the execution of the system, the cache data can be deleted and deleted. Therefore, the processing module 30 first targets at least one memory. The module 10 performs the clearing operation of the cache data, which helps to improve the processing speed of subsequent data rearrangement and reduce resource consumption.

When the system returns to the normal state from the idle state or the dormant state, the processing module 30 notifies the power module 40 to turn on the corresponding switch to restore the power supply to the memory block not used by the memory module 10, so that each memory is restored. The body module 10 returns to the initial state for use by the system.

Please refer to FIG. 5, which is a flowchart of another embodiment of the memory management method of the present invention. As shown in FIG. 5, in the embodiment, the memory management method of the present invention includes steps S501 to S506, wherein steps S501 to S502 are the same as the foregoing steps S401 to S402, and are not described here. Steps S503 to S506 in the method will be described in detail below.

Step S503: Receive an interrupt instruction.

During the execution of step S502, if the system has jumped away from the idle or hibernation state, indicating that the user may need to use the electronic device 1 immediately, the processing module 30 will issue an interrupt command to the control module 20.

Step S504: It is determined whether the target data block of the currently moved data has been moved into the target memory block and the corresponding data has been updated.

During the data transfer process, the multiple data blocks of the data will be moved one by one according to the different moving rules set. After the control module 20 receives the interrupt instruction, it immediately determines whether the target data block of the data currently being moved in the at least one memory module has been moved into a target memory block according to the original rearrangement plan. And check whether the stored corresponding data has been updated in response to the removal of the target data block. If both of the foregoing conditions have been met, then step S506 is continued; if any of the above two conditions is not satisfied, then step S505 is continued.

Step S505: Waiting for the target data block to move in and the corresponding data update is completed.

When it is determined by the foregoing step S504 that any of the foregoing conditions is not satisfied, the control module 20 continues to perform the current target data block moving operation and the related corresponding data update operation. After the target data block is moved in and the corresponding data update is completed, the process proceeds to step S506.

Step S506: interrupting the rearrangement of at least one data.

After the target data block moves in and the corresponding data update is completed, the control module 20 determines that the current data rearrangement operation can be temporarily terminated, so that at least one data rearrangement can be interrupted according to the foregoing interrupt instruction, and at least The control authority of a memory module is returned to the processing module 30. Thereby, when the user continues to operate the electronic device and accesses the related data, the data does not have an access error or the like.

According to the design of the present invention, the data stored in the memory module can be concentrated in a part of the memory block in a state where the system is idle or in a sleep state, and power is cut off for other memory blocks that are not used. In order to save unnecessary power consumption of the memory blocks, it is not necessary to additionally perform data compression and decompression procedures, which can speed up execution efficiency and achieve effective energy saving.

In summary, the present invention is a breakthrough in terms of its purpose, means and efficacy, and it is different from the characteristics of the prior art. It is a great breakthrough for the reviewer to ask for an early patent, and to benefit the society. Debian. It is to be noted that the above-described embodiments are merely illustrative of the principles of the invention and its advantages, and are not intended to limit the scope of the invention. Modifications and variations of the embodiments can be made by those skilled in the art without departing from the spirit and scope of the invention. The scope of protection of the present invention should be as described in the scope of the patent application to be described later.

1, 1a. . . Electronic device

10, 10a, 10b. . . Memory module

11, 11a, 11b, 12, 13, 14, 15, 16, 17, 18. . . Memory block

20. . . Control module

30. . . Processing module

40. . . Power module

50a, 50b, 51, 52, 53, 54, 55, 56, 57, 58. . . switch

1 is a system block diagram of a first embodiment of an electronic device of the present invention.

2(a) is a schematic view showing the memory module of the first embodiment of the electronic device of the present invention before data rearrangement.

FIG. 2(b) is a schematic diagram showing the rearrangement of data by the memory module of the first embodiment of the electronic device of the present invention.

3 is a system block diagram of a second embodiment of the electronic device of the present invention.

4 is a flow chart of an embodiment of a memory management method of the present invention.

Figure 5 is a flow chart showing another embodiment of the memory management method of the present invention.

Claims (8)

A memory management method is applied to an electronic device, the electronic device comprising at least one memory module forming a plurality of memory blocks, the method comprising the steps of: receiving an execution instruction; rearranging and storing according to the execution instruction Storing at least one of the at least one memory module in a single memory block or a plurality of consecutive memory blocks, and simultaneously updating the memory in the at least one memory module One of the group corresponding data, the corresponding data is a virtual memory address corresponding to each data block of the at least one data record and one physical memory address stored in the plurality of memory blocks; and the power supply is stopped. The other memory block that is not used in the plurality of memory blocks. The memory management method of claim 1, further comprising the steps of: clearing the at least one memory module before rearranging the at least one data stored in the at least one memory module All cached data (cache). The memory management method of claim 1, further comprising the steps of: receiving an interrupt instruction; determining whether a target data block of the currently moved data has been moved into a target memory block and has been updated. Corresponding information; When any of the target data blocks of the currently moved data has been moved into the target memory block and the corresponding data has been updated correspondingly, the rearrangement of the at least one data is interrupted. The memory management method of claim 1, wherein the at least one memory module is a single memory module, and the single memory module comprises the plurality of memory blocks. An electronic device comprising: at least one memory module, comprising a plurality of memory blocks for storing at least one data, each of the data being stored in the plurality of memory blocks in a plurality of data blocks; a control module a group, configured to receive an execution command to rearrange the at least one data stored in the at least one memory module to store the at least one data in a single memory block or a plurality of consecutive memory blocks a block, and the control module synchronously updates one of the corresponding data stored in the at least one memory module, wherein the corresponding data is a virtual memory address corresponding to each data block of the at least one data record and is stored in the block a physical memory address in the plurality of memory blocks; a power module for supplying power to the plurality of memory blocks; and a processing module for issuing the execution command and completing the control module After the at least one data is rearranged, the power module is notified to stop supplying power to the other memory blocks that are not used in the plurality of memory blocks. The electronic device of claim 5, wherein the processing module clears the at least one memory module before the control module rearranges the at least one data stored in the at least one memory module All cached data in the middle. The electronic device of claim 5, wherein when the control module receives an interrupt instruction during the rearrangement of the at least one data, if the control module determines any target of the current data being moved After the data block has been moved into a target memory block and the corresponding data has been updated, the rearrangement of the at least one data is interrupted. The electronic device of claim 5, wherein the at least one memory module is a single memory module, and the single memory module comprises the plurality of memory blocks.