JP4155545B2 - Computer system and data transfer control method - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a computer system and a data transfer control method used in the system, and more particularly to a computer system and a data transfer control method improved so as to efficiently execute data transfer with a disk device.
[0002]
[Prior art]
2. Description of the Related Art In recent years, various portable notebook computers or sub-notebook portable personal computers and pocket computers such as portable information terminals have been developed.
[0003]
This type of portable computer is provided with various power saving modes for saving the power of the computer system in order to extend the battery-operable time. The suspend mode is one of the power save modes with the least power consumption. That is, when the computer system is in the suspend mode, most other devices in the system are powered off except for the main memory storing system data necessary for restarting the operating system and user programs.
[0004]
The system data saved in the main memory is the status of the CPU and the status of various peripheral LSIs immediately before the computer system is set to the suspend mode. The main memory also stores the operating state of the operating system and application program and user data created by the application program. Information saved in the main memory is used to restore the work state immediately before the suspend mode.
[0005]
The system data is saved by a suspend routine incorporated in the system BIOS (basic input / output program). The system BIOS is for controlling hardware in the system according to a request from the operating system, and includes a device driver group for controlling various hardware devices in the system. The system BIOS suspend routine is activated when the system is powered off, etc., saves the CPU registers and various peripheral LSI statuses in the memory, and then powers off the system.
[0006]
Power to the main memory is maintained by the battery throughout the system power off. For this reason, the system status and user data are not lost, and the system can be returned to the working state before the suspension at high speed.
[0007]
However, if the capacity of the battery is reduced to the low battery state when the system is in the suspend mode, the data in the main memory is lost. In this case, the system cannot be returned to the state before suspending, and user data expanded in the main memory is also lost.
[0008]
Therefore, recently, hibernation has begun to be used as a new power save mode that replaces the suspend mode. Hibernation is a mode that powers down almost all devices in the system including the main memory after saving the status of the CPU and various peripheral LSIs and the contents of the main memory to the hard disk when the system power is turned off. Power consumption can be reduced. Further, even if the battery capacity is reduced, the information saved in the hard disk is not lost, so that the system state can be normally restored to the state immediately before the hibernation process. Therefore, many portable computers that are frequently used on the go where the AC adapter cannot be used implement hibernation as a power save mode.
[0009]
By the way, with the recent improvements in functions of operating systems and application programs, the memory capacity mounted as the main memory of portable computers is increasing. As the storage capacity of the main memory increases, the time required to save the contents of the main memory to the hard disk and the time required to restore the contents of the hard disk to the main memory also increase accordingly. For this reason, in a system using the hibernation mode, the time required for the hibernation process, that is, the time required from when the user turns off the power switch until the system is actually powered off, and after the user turns on the power switch. The time required to restore the system state is becoming very large.
[0010]
Conventionally, the data input / output operation with the hard disk device via the BIOS is always performed in the PIO (Programmed Input / Output) mode.
[0011]
That is, in a portable computer, ATA (Enhanced IDE) is used as an interface used to connect a hard disk drive. A typical transfer mode used in this Enhanced IDE is the aforementioned PIO mode. In ATA, PIO modes 0 to 4 are defined, and the maximum transfer rates are different from each other. The PIO mode is a transfer mode using a handshake between the CPU and the hard disk drive, and the CPU performs data transfer by repeatedly accessing the I / O port of the hard disk drive directly. Therefore, although the transfer speed is not high at all, this transfer method is sufficient in consideration of the data transfer capability of the hard disk drive itself that requires mechanical operations such as seek operation and spindle rotation.
[0012]
Recently, however, the density of hard disks has rapidly increased, and the data transfer capability of the hard disk itself has been greatly improved. In addition to PIO mode 4, it now supports DMA mode and Ultra DMA mode. Those with a disk interface are the mainstream. For this reason, the conventional BIOS data transfer method in which only the PIO mode is used to input / output data to / from the disk device causes a problem that the performance of the disk device cannot be fully exploited.
[0013]
[Problems to be solved by the invention]
However, when a BIOS disk access routine (INT13h) is called from a higher-level program such as an operating system, if data transfer is always performed using DMA transfer, a serious error may occur depending on the operation mode of the CPU at that time. There is a risk that
[0014]
That is, when executing DMA transfer (DMA mode or UltraDMA), the BIOS itself calculates the physical memory address that is the transfer destination / transfer source instead of using the CPU address conversion mechanism, and uses it as the transfer source. / It is necessary to set in a DMA control logic such as a bus master IDE controller as a transfer destination memory address. This is because in DMA transfer, memory access is executed not by the CPU but by a DMA control logic such as a bus master IDE controller. However, in practice, the method of calculating the physical memory address differs depending on the CPU operation mode (real mode, virtual address mode).
[0015]
That is, in the real mode, the conversion from the segment and the offset to the physical address is performed by the calculation of segment × 16 + offset = physical memory address, but in the virtual address mode such as the V86 mode and the protect mode, it is referred to as a descriptor table. It is necessary to refer to the virtual address translation table. Referring to the descriptor table requires a privilege level, and normally other programs (including BIOS) other than the operating system cannot access it.
[0016]
Therefore, if the BIOS always calculates the physical memory address by the calculation of segment × 16 + offset = physical memory address regardless of the operation mode of the CPU, and starts processing for DMA transfer using it, the CPU In the case of the mode (for example, V86 mode), an incorrect physical memory address is calculated, resulting in a malfunction.
[0017]
The present invention has been made in view of the above-described circumstances. The execution condition of the DMA transfer mode can be determined in consideration of the operation mode of the CPU, the operation is highly reliable, and the disk device is sufficiently connected. An object of the present invention is to provide a computer system and a data transfer control method capable of improving the data transfer efficiency.
[0018]
[Means for Solving the Problems]
In order to solve the above problems, the present invention provides: Without using virtual address translation table A computer having a CPU having a first operation mode for calculating a physical address from a segment and an offset, and a second operation mode for calculating a physical memory address by using a virtual address including the segment and the offset and a virtual address conversion table In the system, A DMA controller for executing DMA transfer between a disk device provided in the computer system and a memory of the computer system; Access to the disk unit was requested by a higher-level program In response to It is determined whether the operation mode of the CPU is the first operation mode or the second operation mode When executing the process and determining that the operation mode of the CPU is the first operation mode, A physical memory address is calculated from the segment and offset set in the CPU register, and the calculated physical memory address and a disk address set in another register of the CPU are calculated. By setting in the DMA controller, data transfer to and from the disk device requested by the host program is executed by DMA transfer by the DMA controller, and the operation mode of the CPU is the second operation mode. Is determined, the data transfer to and from the disk device requested by the higher-level program is executed in the PIO transfer mode in which the CPU repeatedly executes the access to the disk device. And a disk access control means.
[0019]
In this computer system, when access to a disk device is requested from a higher-level program, the CPU operation mode at that time is determined, and this is the first operation mode in which the physical memory address can be directly calculated from the segment and offset. On the condition, the processing for DMA transfer is executed. Therefore, it is possible to efficiently execute data transfer between the disk device and the memory without causing problems such as incorrect calculation of the physical memory address, and not only the normal disk input / output operation but also the operating system The bootstrap process and the return process from hibernation can be speeded up.
[0020]
The disk access control means causes the CPU to repeatedly execute access to the disk device when the current operation mode of the CPU is determined to be the second operation mode by the operation mode determination means. It is preferable that data transfer to and from the disk device requested by the higher-level program is executed depending on the mode. As a result, the DMA transfer mode and the PIO transfer mode can be selectively executed according to the current operation mode of the CPU, and the optimum transfer mode can always be used.
[0021]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the drawings.
FIG. 1 shows the configuration of a computer system according to an embodiment of the present invention. This computer system is a notebook-type or sub-notebook-type portable personal computer, and is composed of a computer main body and an LCD panel unit attached to the computer main body so as to be freely opened and closed. This computer has a built-in battery, and is configured to be operable by electric power from the built-in battery. In addition, power can be supplied from an external power source such as an AC commercial power source via an AC adapter. When power is supplied from an external power source, the power from the external power source is used as an operating power source for the computer system. At this time, the built-in battery is automatically charged by the power from the external power source. When the AC adapter is removed or the AC commercial power supply breaker is turned off, the power from the built-in battery is used as the operating power supply for the computer system.
[0022]
A hard disk drive (HDD) 17 having an IDE interface is detachably mounted on the computer body. The HDD 17 is used as a secondary storage for the computer.
[0023]
On the system board of this computer, as shown, a CPU 11, a host-PCI bridge 12, a main memory 13, a VGA controller 14, a PCI-ISA bridge 15, a bus master IDE controller 16, a BIOS-ROM 18, an embedded controller ( EC) 20, a power supply controller (PSC) 21, and the like are provided.
[0024]
The CPU 11 executes operation control and data processing of the entire system. As the CPU 11, a CPU that supports a memory segmentation mechanism and a virtual addressing mechanism, for example, a microprocessor “Pentium” manufactured and sold by Intel Corporation is used. In this case, the CPU 11 has the following operation.
[0025]
That is, the CPU 11 has a real mode, a protect mode, and a virtual 8086 mode (V86 mode) as operation modes for executing a program such as an application program or an operating system (OS). The real mode is a real address mode using memory segmentation, and the protect mode and the virtual 86 mode are virtual address modes.
[0026]
In other words, the real mode is a mode in which a memory space of 1 Mbyte at the maximum can be accessed, and the conversion from a logical address to a physical address is an address calculation in which a physical address is determined by an offset value from a base address represented by a segment register. Done by the format. That is, as shown in FIG. 2, the segment is a 16-bit value (sometimes referred to as a selector) that virtually represents the memory segment, and the physical memory address is shifted by 4 bits to the left of the segment value ( 16 times) as a base address, and an offset value represented by 16 bits is added to the base address.
[0027]
On the other hand, the protect mode is a mode in which a memory space of up to 4 Gbytes per task can be accessed, and a linear address is determined using a virtual address conversion table called a descriptor table. This linear address is finally converted into a physical address by paging. That is, as shown in FIG. 3, the segment value is used as a pointer for referring to the descriptor table, the value obtained from the descriptor table is used as a base address, and an offset value represented by 16 bits is used as the base address. In addition, a linear address is calculated. The V86 mode is an operation mode for emulating the real mode in the protect mode environment, and uses the same virtual address calculation method as the protect mode.
[0028]
The operation mode at the time of initialization of the CPU 11 is a real mode, and is switched to the protect mode and the V86 mode under the control of software such as an operating system.
[0029]
The host-PCI bridge 12 is a bridge that connects the CPU bus 1 and the PCI bus 2 bidirectionally, and a memory controller for controlling the main memory 13 is also incorporated therein. The main memory 13 is used as a main memory of this system, that is, a system memory, and stores an operating system, an application program to be processed, user data created by the application program, and the like. The main memory 13 is realized by a semiconductor memory such as a DRAM.
[0030]
The BIOS-ROM 18 is for storing a system BIOS (Basic I / O System), and is configured by a flash memory so that the program can be rewritten. The system BIOS is a systematic function execution routine for accessing various hardware in the system, and is configured to operate in a real mode. The system BIOS includes a processing routine for bootstrapping the operating system when the system is powered on, a BIOS driver group for various hardware control, and the like. Each BIOS driver includes a plurality of function execution routine groups corresponding to these functions in order to provide a plurality of functions for hardware control to the operating system and application programs. When INT13h is called from the upper program, the BIOS hard disk driver is executed. This driver (INT13h) includes a function for performing data transfer with the HDD 17 by DMA transfer and a function for performing PIO transfer.
[0031]
The EC 20 is a controller for controlling additional functions of the system. A thermal control function for controlling the rotation of the cooling fan in accordance with the temperature around the CPU and the like, and various states of the system are controlled by lighting of LEDs and beeps. It has an LED / beep sound control function for notifying the user, a power sequence control function for controlling on / off of the system power in cooperation with the power controller 21, a power status notification function, and the like. Even in the hibernation state, the operation power is supplied to the EC 20 and the power controller 21, and the on / off of the power switch 22 and the panel switch 23 is monitored.
[0032]
Hibernation saves the status of the CPU 11 and various peripheral LSIs and the contents of the main memory 13 to the hard disk 17 at the occurrence of an event for transition to the power save mode such as system power off, and then almost all the systems including the main memory 17 in the system. In this mode, the device is powered down. When a wake-up event such as system power off occurs in the hibernation state, the memory image saved in the hard disk 17 is restored to the main memory 13 and restored to the work state before hibernation. The control of hibernation execution and return processing is ACPI (Advanced Configuration and Power).
Interface) is executed under the management of the corresponding OS.
[0033]
The VGA controller 14 is for controlling an LCD and an external CRT used as a display monitor of this system, and displays screen data drawn in the VRAM on one or both of the LCD and the external CRT.
[0034]
The bus master IDE controller 16 is for controlling an IDE device (here, the HDD 17) mounted on the computer main body, and is a bus master function (DMA controller) capable of executing DMA transfer between the IDE device and the main memory 13. )have. This bus master function executes a bus cycle (DMA transfer) for data transfer by itself in response to a command from the CPU 11, and with the IDE device and the main memory 13 in a state where the CPU load is reduced as compared with the PIO mode. Can be transferred at high speed.
[0035]
Next, the BIOS disk access operation will be described with reference to FIG.
[0036]
Here, it is assumed that a BIOS disk driver (INT13h) is called from a higher-level program such as an operating system. The BIOS call of INT13h is realized by using the software interrupt function of the CPU 11. In this case, the following I / O parameters are notified from the host program to the BIOS disk driver (INT13h) through the register of the CPU 11.
[0037]
R / W function: Indicates disk read or disk write
Number of transfer sectors: Number of sectors to transfer data to / from the disk unit
Segment: 16-bit segment value as described above
Offset: The above 16-bit offset value
HDD address: Start address for disk access
Drive number: Drive number of the disk device to be accessed
The upper program sets the R / W function, transfer sector number, segment, offset, HDD address, and drive number in the AH register, AL register, ES register, BX register, CX / DH register, DL register, etc. of the CPU 11, respectively. Later, INT13h is called. As a result, the control is transferred to the BIOS disk driver (INT13h).
[0038]
The BIOS disk driver (INT13h) first checks the operation mode of the CPU 11 in which the host program was operating, that is, the current operation mode of the CPU 11, and determines whether it is the virtual address mode or the real mode ( Steps S101 and S102). As described above, since the BIOS is configured to operate in the real mode, the BIOS call from the host program is performed in the real mode or the V86 mode. Therefore, by checking whether or not the V86 flag of the status register in the CPU 11 is on, it is possible to determine whether it is the virtual address mode or the real mode.
[0039]
In the virtual address mode, that is, the V86 mode, the BIOS disk driver (INT13h) executes data transfer with the HDD 17 in the PIO transfer mode in which the CPU 11 repeatedly executes access to the HDD 17 (step S103).
[0040]
On the other hand, in the real mode, the BIOS disk driver (INT13h) executes data transfer with the HDD 17 in the DMA transfer mode (step S104). In this case, the BIOS disk driver (INT13h) first calculates the physical memory address from the segment of the ES register and the offset value of the BX register (segment × 16 + offset = physical memory address), and then calculates the physical memory address. To do. Then, the BIOS disk driver (INT13h) sets the physical memory address and the HDD address set in CX / DH in the bus master IDE controller 16 as initial values of the transfer source / destination addresses and the AL register. Are set in the bus master IDE controller 16 as the data transfer width. As a result, the bus master IDE controller 16 starts DMA transfer. For example, in the case of disk read from the main memory 13 from the disk, the bus master IDE controller 16 reads data sequentially from the sector data at the position specified by the HDD address, and the read data is specified by the physical memory address. A bus cycle for writing in order from the memory address of the main memory 13 is executed.
[0041]
FIG. 5 shows a processing example when determining the data transfer mode in consideration of not only the virtual address mode but also the transfer mode supported by the HDD 17.
[0042]
That is, the BIOS disk driver (INT13h) first checks the operation mode of the CPU 11 in which the host program was operating, that is, the current operation mode of the CPU 11, and determines whether it is the virtual address mode or the real mode. (Steps S101 and S102). Up to this point, the process is the same as in FIG.
[0043]
In the virtual address mode, that is, the V86 mode, the BIOS disk driver (INT13h) determines whether the HDD 17 supports the Read / Write Multiple command based on the drive parameter information read from the HDD 17 (step S201). ), Based on the result, data transfer using a Read / Write Multiple command or a Read / Write Sector command is executed (step S202). Read / Write Multiple is a command that can specify read / write for a plurality of sectors at a time. If this Read / Write Multiple command is not supported, read / write in units of a single sector for HDD access. A data transfer mode using a Read / Write Sector command that designates “” is used. Both Read / Write Multiple and Read / Write Sector are PIO transfer modes.
[0044]
In the real mode, the BIOS disk driver (INT13h) determines whether the HDD 17 supports DMA based on the drive parameter information read from the HDD 17 (step S204). If not supported, the aforementioned Read / Write Multiple command is used for HDD access. If the DMA is supported, it is next determined whether or not the Ultra DMA is supported (step S205). If not supported, a DMA Read / Write command is used for HDD access (step S207). If it is supported, an Ultra DMA Read / Write command is used (step S208). Both the DMA Read / Write command and the Ultra DMA Read / Write command are commands for the aforementioned DMA transfer.
[0045]
Many HDDs support Read / Write Multiple and Ultra DMA Read / Write, so even if the number of transfer sectors is 2 or more, PIO transfer is actually executed in the virtual address mode using the Read / Write Multiple command. In the real mode, DMA transfer using the UltraDMA Read / Write command is executed.
[0046]
The data transfer rate is highest for Ultra DMA Read / Write, followed by DMA Read / Write, Read / Write Multiple, and Read / Write Sector.
[0047]
Next, with reference to FIG. 6, the operation when the system is started, that is, when the operating system (OS) is bootstrapped will be described.
[0048]
When the system is powered on by turning on the power switch 22, the BIOS uses the disk driver (INT 13 h) to access the disk for reading the contents of the MBR (Master Boot Record) of the HDD 17 into the main memory 13. Do. The MBR includes a master boot code for reading the boot code (OS loader) from the active partition, and control is transferred to the master boot code. The master boot code sets a parameter necessary for reading the OS loader in the register of the CPU 11 and then calls the BIOS disk driver (INT13h). The disk driver (INT 13h) executes a disk read designated by the master boot code, and reads the OS loader into the main memory 13. Thereafter, control is transferred to the OS loader. The OS loader sets parameters necessary for reading the kernel in the register of the CPU 11, and then calls the BIOS disk driver (INT13h).
[0049]
The disk driver (INT13h) reads the kernel into the main memory 13 by executing the disk read designated by the OS loader. Thereafter, control is transferred from the OS loader to the kernel. The kernel reads various drivers by using a BIOS disk driver (INT13h), and the mode is switched from the real mode to the protected mode. When calling the BIOS disk driver (INT13h), the V86 mode is used. Until the environment in which the disk driver (INT13h) is called is switched from the real mode to the V86 mode, all data transfer between the disk device and the memory by the disk driver (INT13h) is performed by DMA transfer. Then, after switching to the V86 mode, disk access in the PIO mode is performed. As a result, it is possible to increase the speed of the bootstrap sequence of the OS as compared with the case where the disk driver (INT 13h) always accesses the disk in the PIO mode.
[0050]
Next, with reference to FIG. 7, the operation at the time of returning from the hibernation state will be described.
[0051]
When a wake-up event such as turning on the power switch 22 occurs, the BIOS uses the disk driver (INT13h) to perform disk access for reading the contents of the MBR (Master Boot Record) of the HDD 17 into the main memory 13. The MBR includes a master boot code for reading the boot code (OS loader) from the active partition, and control is transferred to the master boot code. The master boot code sets a parameter necessary for reading the OS loader in the register of the CPU 11 and then calls the BIOS disk driver (INT13h). The disk driver (INT 13h) executes a disk read designated by the master boot code, and reads the OS loader into the main memory 13. Thereafter, control is passed to the OS loader. The OS loader determines whether it is a return from hibernation or a normal bootstrap. This determination can be performed, for example, by storing a flag indicating the status in the hibernation state in the OS or in a register of the EC 20 and referring to the flag when executing the OS loader.
[0052]
In the case of returning from hibernation, the OS loader sets a parameter necessary for reading the memory image saved in the HDD 17 in the register of the CPU 11, and then calls the BIOS disk driver (INT13h). The disk driver (INT13h) reads the memory image into the main memory 13 by executing the disk read designated by the OS loader. At this time, since the CPU 11 is still in the real mode, the transfer of the memory image from the HDD 17 to the main memory 13 is executed at a high speed by the DMA transfer. Thereafter, processing necessary for restoring the state of each main device is executed by the OS, so that the work environment before the transition to hibernation is restored.
[0053]
As described above, according to the present embodiment, an error is caused by selectively switching between DMA transfer and PIO transfer according to the operation mode of the CPU 11 when a disk input / output operation is requested from a higher-level program. Data transfer between the disk device and the memory can be performed efficiently without causing problems such as calculation of the physical memory address. In particular, when returning from hibernation, using the Ultra DMA Read / Write command that can transfer a large amount of memory image data at a high speed can significantly reduce the time required for reading the memory image data compared to the case of using PIO. it can.
[0054]
【The invention's effect】
As described above, according to the present invention, it is possible to sufficiently improve the data transfer efficiency with the disk device without impairing the reliability of the operation.
[Brief description of the drawings]
FIG. 1 is a block diagram showing a configuration of a computer system according to an embodiment of the present invention.
FIG. 2 is a view for explaining a physical address calculation method when the CPU is in a real mode in the embodiment;
FIG. 3 is a view for explaining a physical address calculation method when the CPU is in a protect mode in the embodiment;
FIG. 4 is a flowchart for explaining a disk access operation executed in the embodiment;
FIG. 5 is a flowchart for explaining a second example of the disk access operation executed in the embodiment;
FIG. 6 is a flowchart for explaining a bootstrap operation of the operating system in the embodiment;
FIG. 7 is a flowchart for explaining a return operation from hibernation in the embodiment;
[Explanation of symbols]
11 ... CPU
12 ... Host-PCI bridge
13 ... Main memory
16 ... Bus master IDE controller
17 ... HDD
18 ... BIOS-ROM

Claims (3)

A first operation mode for calculating a physical address from a segment and an offset without using a virtual address conversion table, and a second operation for calculating a physical memory address using the virtual address and the virtual address conversion table including the segment and the offset In a computer system comprising a CPU having a mode,
A DMA controller for executing a DMA transfer between a disk device provided in the computer system and a memory of the computer system;
In response to a request from the host program to access the disk device, the CPU executes a process for determining whether the operation mode of the CPU is the first operation mode or the second operation mode, and the CPU When it is determined that the operation mode is the first operation mode, a physical memory address is calculated from the segment and offset set in the register of the CPU, and the calculated physical memory address and the CPU By setting a disk address set in another register in the DMA controller to the DMA controller, data transfer to and from the disk device requested by the host program is executed by DMA transfer by the DMA controller, and the CPU Is the second operation mode. Disk access that executes data transfer to and from the disk device requested by the higher-level program in a PIO transfer mode that causes the CPU to repeatedly execute access to the disk device. And a control means. The upper program is an operating system, and it is determined that the operating mode of the CPU when the operating system calls a disk driver that accesses the disk device during the bootstrap sequence is the first operating mode. If the operation mode of the CPU to switch from the first operation mode to the second operation mode, the disk access control means, in response to a request from the operating system in the bootstrap sequence, the operating 2. The computer system according to claim 1, wherein data transfer for reading a file group constituting the system from the disk device is executed by DMA transfer by the DMA controller. A first operation mode for calculating a physical address from a segment and an offset without using a virtual address conversion table, and a second operation for calculating a physical memory address using the virtual address and the virtual address conversion table including the segment and the offset A data transfer control method applied to a computer system including a CPU having a mode,
Determining whether the operation mode of the CPU is the first operation mode or the second operation mode in response to a request from a higher-level program to access a disk device provided in the computer system; ,
When it is determined that the operation mode of the CPU is the first operation mode, a physical memory address is calculated from the segment and offset set in the register of the CPU, and the calculated physical memory address and the CPU By setting a disk address set in another register in the DMA controller provided in the computer system, data transfer to and from the disk device requested by the higher-level program is performed by the DMA by the DMA controller. Steps to be performed by transfer,
When it is determined that the operation mode of the CPU is the second operation mode, the PIO transfer mode in which the CPU repeatedly executes access to the disk device, and the disk device requested by the higher-level program. A data transfer control method comprising the steps of:

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