JPH0944418A - Information-processing system and its control method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an information processing system capable of executing a power management operation and a recovery operation from power management at a higher speed and the control method. SOLUTION: In the information processing system of a type provided white a processor 11, a volatile memory 13 and nonvolatile auxiliary storage devices 22 and 24 for stopping power supply to a prescribed electrical circuit after the contents of the memory 13 are stored in the auxiliary storage devices 22 and 24, further, a memory use information management means for managing whether the respective areas the inside the memory are valid areas or invalid areas is provided. At the time of stopping the power supply, only the contents of the valid areas in the memory 13 are stored in the auxiliary storage devices 22 and 24 corresponding to the memory use information management means.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an information processing system including a personal computer and a control method therefor, and in particular, appropriately supplies electric power to each internal electric circuit when the usage of the system deteriorates. Power saving operation to reduce or stop (“Power Management”
(Also referred to as a) information processing system having a function and a control method thereof. More specifically, the present invention relates to an information processing system and a control method therefor capable of executing a power management operation and a return operation from a power management mode at a higher speed.

[0002]

2. Description of the Related Art With the recent technological innovation, various types of personal computers such as desktop type and notebook type (hereinafter, also referred to as "PC" or "system") have been developed and put on the market. Of these, notebook PCs
Is designed and manufactured to be small and light in weight for outdoor and portable use. Japan Ib
Most notebooks P, including those sold by M Corporation
C includes a main body that houses a system board and peripheral devices therein and has a keyboard arranged on the upper surface thereof, and a lid body in which an LCD panel is embedded in approximately the center of the inside. It is a structure in which the body is hinged so that it can be opened and closed substantially at the rear edge. The user opens the lid when using
The lid is designed to be closed when not in use or carrying.

One of the characteristics of the notebook PC is that it is a "battery driven type" that can be driven by a built-in battery. This is because it can be used even in places where commercial power cannot reach. The battery built into the notebook PC is generally Ni-Cd, NiMH, Li.
-It takes the form of a "battery pack" in which a plurality of rechargeable battery cells such as Ion are connected and packaged. Such a battery pack can be reused by charging, but the charging capacity per charge is only about 2 to 3 hours in operating time of the system. It can be said that one of the characteristics of the notebook PC is that various measures have been made to save power in order to extend the battery life as much as possible.

Recently, there is an increasing demand for power saving from an ecological point of view even for desktop PCs that can supply power inexhaustibly with a commercial power source. The US Environmental Protection Agency (EPA) announced in June 1993 "Ener
gy Star Computer Program "
Announced a voluntary regulation called power consumption, power consumption in a standby state below a certain standard (driving power 30W or less, or CPU
It is required to be 30% or less of the operating time). For this reason, computer makers are competing to develop products in accordance with the proposed regulations. For example, Japanese IBB
M Corporation has already marketed several types of desktop PCs with a power saving function (for example, PS / 55E (commonly known as "
GreenPC "), PC750, and the Aviva series (" Aptiva "is a trademark of IBM Corp. in the US).

The power saving of the PC can be achieved by not only reducing the power consumption itself during the operation of each electric circuit, but also by appropriately lowering or interrupting the power supply to the electric circuit (or device) whose usage has been lowered. Will be realized. The latter may also be referred to as "power management".

The so-called "Suspend"
d) ”and“ Hibernation ”
n) ”is a prime example of power management.
More specifically, the term “suspend” means that after saving data required for task restart (for example, hardware context information such as I / O setting status and CPU status, VRAM content, etc.) to the main memory. , Refers to the operation of stopping the power supply to almost all electric circuits except the main memory. Also, hibernation means hardware context information, VRAM contents, main
After saving all volatile data, such as memory contents, to a non-volatile storage device such as an HDD (hard disk drive), it refers to the operation of stopping the power supply to almost all electrical circuits including the main memory. . The system uses suspend or hibernation after a predetermined time has passed since the last user input (that is, the operation wait state continues for a predetermined time or more), or when the user inputs a predetermined key (hot key). And power management mode. Also, when returning from power management to the normal operation mode,
The sequence is almost reversed. Incidentally, the return from suspend is called "Resume", and the return from hibernation is called "Wake up".

Suspend and hibernation are similar in that power supply is stopped after saving data for task restart. However, it can be said that hibernation is superior in that power supply to almost all electric circuits in the system can be stopped. (For example, the specification of Japanese Patent Application No. 05-184186 assigned to the present applicant (Japanese Patent Application Laid-Open No. 0-184186)
7-084848, our reference number: JA9-93
020) discloses a technique related to hibernation. Also, IBM Japan, Ltd.
ThinkPad, a notebook PC marketed by
750/755 ("ThinkPad" is a trademark of IBM Corp. in the US) has a hibernation function. )

[Problems to be Solved by the Invention]

As described above, before the system enters the hibernation mode, a "data store sequence" for storing necessary data in the main memory or the like in the HDD must be performed. Also, when waking up, the "data restore sequence" that restores the data saved in the HDD naturally
Have to go through.

According to the conventional hibernation / wake-up technique (for example, Japanese Patent Laid-Open No. 07-084848 mentioned above), in the data store sequence, the entire image of the main memory is saved in the HDD, and
In the data restore sequence, it was necessary to expand the data stored in the HDD to the entire main memory. In short, when entering hibernation and when waking up, a processing time for storing and expanding the memory image of the entire main memory was required. Further, it is necessary to secure at least a storage area (also referred to as "hibernation file") having the same size as the main memory on the HDD.

Store / image of entire main memory
As long as it is targeted for restoration, the processing time and storage area for hibernation and wake up are
Naturally, it will increase in proportion to the capacity of the main memory. Especially in recent PCs, SIMM (Single I
nline Memory Module) card and DIMM (Dual Inline)
By installing a memory module card, the capacity of the main memory can be easily increased. Alternatively, the capacity of the standard memory itself may be enormous in the first place due to an increase in the power of the CPU. 32MB for example
PCs with 64MB standard memory are becoming commonplace. It is considered that the problems of processing time and storage area in hibernation and wake-up are becoming more and more serious with the tendency of increasing the size of the memory.

An object of the present invention is to save power ("power management") by appropriately reducing or stopping the power supply to an electric circuit when the usage of the system is reduced.
It is to provide an excellent information processing system having a function and a control method thereof.

A further object of the present invention is to provide an information processing system and a control method therefor capable of executing a power management operation and a return operation from the power management at a higher speed.

[0013]

The present invention has been made in consideration of the above problems, and a first aspect thereof is a processor, a volatile memory, and a non-volatile auxiliary storage device. In an information processing system of a type that stops the power supply to a predetermined electric circuit after storing the contents of the memory in the auxiliary storage device, further managing whether each area in the memory is a valid area or an invalid area. In the information processing system, the memory use information management means is included, and only the contents of the effective area of the memory are stored in the auxiliary storage device according to the memory use information management means when the power supply is stopped.

A second aspect of the present invention is that a processor, a volatile memory, a non-volatile auxiliary storage device, and the contents of the memory are stored in the auxiliary storage device in response to the occurrence of a predetermined event. In an information processing system including a power management means for stopping power supply to a predetermined electric circuit after storing,
Further, the power management means includes a memory usage information management means for managing whether each area in the memory is a valid area or an invalid area, and the power management means according to the memory usage information management means when the power supply is stopped. In the information processing system, only the contents of the effective area are stored in the auxiliary storage device.

A third aspect of the present invention is an information processing system of a type in which the contents of a volatile memory are stored in a non-volatile storage device in response to the occurrence of a predetermined event and then a transition is made to a power saving operation mode. In the control method, a first step of detecting the occurrence of the predetermined event, a second step of determining whether each area of the volatile memory is a valid area or an invalid area, and a valid area of the volatile memory A method of controlling an information processing system, comprising: a third step of storing only the contents of the above in the nonvolatile memory device; and a fourth step of transiting to a power saving operation mode.

A fourth aspect of the present invention is an information processing system including a processor, a volatile memory, and a non-volatile auxiliary storage device, wherein the power supply to a predetermined electric circuit is stopped. When the contents of the memory are stored in the auxiliary storage device, the contents of the memory are compressed and then stored.

A fifth aspect of the present invention is that a processor, a volatile memory, a non-volatile auxiliary storage device, and the contents of the memory are stored in the auxiliary storage device in response to the occurrence of a predetermined event. In an information processing system including a power management means for stopping power supply to a predetermined electric circuit after storing,
The power management means is an information processing system characterized by storing the contents of the memory in the auxiliary storage device after compressing the data.

The sixth aspect of the present invention is characterized in that when the data saved in the auxiliary storage device in the fourth or fifth aspect is restored to the memory, it is performed after decompressing the data. It is a processing system.

A seventh aspect of the present invention is an information processing system of a type in which the contents of a volatile memory are stored in a non-volatile storage device in response to the occurrence of a predetermined event and then a transition is made to a power saving operation mode. In the control method, a first step of detecting the occurrence of the predetermined event, a second step of data compression of the contents of the volatile memory, and a nonvolatile storage of the data compressed contents of the volatile memory. A method of controlling an information processing system, comprising: a third step of storing in the device; and a fourth step of transiting to a power saving operation mode.

Further, in the eighth aspect of the present invention, when returning from the power saving operation mode in the seventh aspect, the data saved in the nonvolatile storage device is expanded and then stored in the volatile memory. A method of controlling an information processing system characterized by restoring.

The "effective area" in the information processing system or the control method therefor according to the first, second and third aspects.
Here, for example, it is an area containing data which the processor is currently using or may use in the future.
The “invalid area” is, for example, an unused area and an area where a parity error has occurred.

Further, in each of the first, second, fourth, and fifth aspects, the purpose of stopping power supply to a predetermined electric circuit is to improve power saving (that is, power management) of the system. It is none other than. A specific example of power saving is "hibernation" described in [Prior Art]. In this case, the predetermined electric circuit to which power supply is stopped includes almost all devices including a volatile main memory.

As the "data compression" in the fourth, fifth and seventh aspects, an existing data compression tool based on an algorithm such as a slide dictionary method or a dynamic dictionary method may be used.

An example of the "power saving operation mode" referred to in each of the third and seventh aspects is hibernation.

Therefore, according to the present invention, it is possible to provide an information processing system and its control method capable of executing the power management operation and the return operation from the power management at a higher speed.

For example, according to the information processing system and the control method thereof according to the first to third aspects of the present invention, when the system transits to hibernation, the main
Only valid data in memory is saved to HDD. Also, when waking up from hibernation, naturally only valid data is restored in the main memory. As is well known, main memory is not only the area where valid data (that is, currently used or that may be used in the future) is written, but also the invalid area (that is, unused area or parity error). Area, etc.) that contains many. Therefore, by saving only valid data (that is, a size smaller than the total capacity of main memory), the processing time required for hibernation and wakeup (especially data store and restore) is significantly increased. Shortened. Further, the size of the storage area (hibernation file) to be prepared in the HDD can be greatly saved.

Attribute information of each area in the main memory, such as a valid data area or an invalid data area, a memory resident data area or a memory non-resident data area (hereinafter referred to as "memory usage information"). Generally refers to a "memory manager" (a memory manager that supports a virtual memory function is also called a "virtual memory manager (VMM)") that is a part of the kernel of an operating system. It is managed in page units (one page is 4 KB, for example). Therefore, if a program (hereinafter referred to as “power manager”) that executes a power saving operation such as hibernation / wakeup exists in the same software layer as the VMM, that is, the kernel portion of the OS. Since the "memory usage information" can be easily used, the first to third aspects of the present invention can be realized relatively easily and inexpensively.

Further, according to the information processing system and the control method thereof according to the fourth to eighth aspects of the present invention, when the transition to the hibernation mode is made, the desired image in the main memory is data-compressed. To be stored in the HDD. Also, when waking up, it is natural that the main
Restored to memory. Generally, the data on the main memory has regularity, and a compression effect of about 50% can be expected. Therefore, it is possible to significantly reduce the size of the hibernation file in the HDD. Especially, if a recent powerful CPU (for example, PowerPC 603e jointly developed by IBM Corp., Motorola Corp., Apple Corp., USA) is used, data compression / decompression can be executed at extremely high speed.
There is almost no effect on the processing time. Rather, due to the reduction in the number of disk accesses accompanying the reduction in the data size, the processing time required for data store and restore will be greatly reduced, and the extra processing time for data compression / decompression can be absorbed ( Because, mechanical control of HDD takes a very long time!).

Further objects, features and advantages of the present invention are as follows.
It will become apparent from the following more detailed description based on the embodiments of the present invention and the accompanying drawings.

[0030]

Embodiments of the present invention will be described below in detail with reference to the drawings.

A. Personal computer (PC) 1
Hardware Configuration of 00 FIG. 1 shows a hardware configuration of a personal computer (PC) 100 used for implementing the present invention.

In the PC 100, the CPU 11, which is the main controller, executes various programs under the control of the operating system (OS). The CPU 11 communicates with each unit via a common signal transmission path (also referred to as a “bus”) 12 and 12 ′ including a data signal line, an address signal line, a control signal line, and the like. The CPU 11 is, for example, IBM US
PowerPC 603e ("PowerPC" is US I
BM's trademark). Further, the bus 12 is the CPU 11
Local bus, and bus 12 'is an input / output bus. An example of the bus 12 'is PCI (Peripheral Comp
onent interconnect (BUS) or ISA (Industri)
al Standard Architecture) bus.

The main memory 13 is a volatile memory (RAM) for loading each program executed by the CPU 11 (OS, application programs, etc .: see section B) and used by the CPU 11 as a work area.
It is. As the main memory 13, a dynamic RAM (DRAM) having a large capacity and available at a relatively low cost is used. The capacity of the main memory 13 is 32 MB, for example, and can be expanded up to about 96 MB. Further, when the code or data cannot fit in the main memory 13, the auxiliary storage device (described later) is operated by the cooperative operation of the virtual memory manager and the file manager.
Swapping is performed between and (described later). The memory controller 14 is for controlling the access operation to the main memory 13. The memory controller 14 of this embodiment is integrated into one chip together with a bus bridge for connecting the local bus 12 and the input / output bus 12 '. ROM1
Reference numeral 5 is a non-volatile memory in which write data is determined at the time of manufacturing, and is used for semi-permanently storing a coded test program (POST) performed when the system 100 is started.

The video controller 16 has a CPU 11
Is a peripheral controller for actually processing the drawing command from the CPU, and stores the processed drawing information in a screen buffer (VRA).
M) 17 and the drawing information is read from the VRAM 17 while being written in the liquid crystal display device (L) as a display unit.
CD) 18 is output. audio·
The controller 19 is a peripheral controller for processing input / output of audio signals. The audio signal output from the audio controller 19 is amplified by, for example, the amplifier 20 and output as audio from the speaker 21.

Hard disk drive (HDD) 2
2 or floppy disk drive (FDD) 24
Is a so-called auxiliary storage device. The floppy disk controller 23 is a controller for driving the FDD 24. Access to HDD22 and FDD24,
It is under the control of a file manager that is part of the operating system kernel.

The DMA (Direct Memory Access) controller 25 is provided in the main memory 1 without the intervention of the CPU 11.
3 is a peripheral controller for performing data transfer between the peripheral device 3 and a peripheral device (for example, FDD 24). The interrupt controller 26 constantly monitors the buses 12 and 12 ', and when detecting the occurrence of an interrupt (or a system event), notifies the CPU 11 (more specifically, an event handler in the kernel of the OS) of this. It is supposed to do.

The I / O controller 27 is a peripheral controller for controlling data input / output to / from an external device (modem, printer, etc.) via a serial port or a parallel port. The keyboard / mouse controller (KMC) 29 converts the input matrix from the keyboard 30 and the coordinate values designated by the mouse 31 into a format that matches the definition of the operating system and sends it out onto the bus 12.

The oscillator (OSC) 32 is a device for supplying a clock signal to a device such as the CPU 11 which is synchronously driven and each device having a timer function.

Real Time Clock (RTC) 33
Is a device for real-time measurement that generates signals at fixed time intervals. The CMOS RAM 34 is a storage element having a CMOS structure. The RTC 33 and the CMOS RAM 34 of this embodiment are mounted on one chip and are backed up by the coin battery 35.

EEPROM (Electrically Erasable PR
OM) 36 is a rewritable non-volatile semiconductor memory that stores passwords, installed PC card serial numbers, some system configuration information, and other information necessary for system security. It is provided.

The system 100 includes an AC / DC adapter 4
The power is supplied from either an external commercial power source obtained via 1 or a built-in battery pack 42 for driving. The supply voltages of the power supplies 41 and 42 are input in parallel to the DC / DC converter 43. The DC / DC converter 43 reduces the supply voltage to a level suitable for driving the system 100 (for example, 5 V or 3.3 V) and supplies it to each unit as a constant power supply voltage. The supply and cutoff of the power supply voltage is performed by the opening / closing operation of the FET switch 44. The gate terminal of the FET switch 44 is electrically connected to the corresponding bit cell in the power control register 46.

The power management processor 45 is a peripheral controller provided mainly for managing the power supply to each part in the system 100, and is preferably a one-chip controller "300 / H8" manufactured by Hitachi, Ltd. Is. This type of IC has a 16-bit CPU,
RAM, ROM, timer, 8 analog input pins,
It has 16 digital input / output pins and its function is programmable. In particular, the power management processor 4 of this embodiment
5 communicates with each part via the input / output bus 12 ',
By detecting the open / closed state of the lid (LCD), it is possible to detect the decrease in the remaining capacity of the battery 42 (low battery), and to rewrite the content of the bit cell of the power control register 46. Has become.

Most of the PCs currently on the market are
Equivalent to the hardware blocks shown at 11-36 and 41-44. Further, the technology itself related to the power management processor 45 and the power control register 46 is already known. For example, the specification of Japanese Patent Application No. 04-54955 assigned to the present applicant (Japanese Patent Application Laid-Open No. 0-54955)
No. 5-289784: Company reference number JA9-92-
004) and Japanese Patent Application No. 05-184186 (JP-A-07-84848: our company reference number JA9-93).
-020) describes hardware blocks equivalent to reference numerals 45 and 46. A notebook computer ThinkPad 700/750/755, which is commercially available from IBM Japan, Ltd., includes hardware components equivalent to reference numerals 45 and 46. Further, in order to configure the PC, a surprisingly large number of hardware components described in FIG. 1 are necessary, but these are well known to those skilled in the art and are not related to the gist of the present invention. Therefore, the description is omitted in this specification.

B. Software Configuration of PC 100 FIG. 2 schematically shows a hierarchical configuration of software executable on the PC 100 for implementing the present invention.

Device driver (D / D): The lowest software layer is the device driver (D / D). The device driver is for converting a general format command issued by higher-level software (such as an operating system) into a format suitable for driving hardware unique to each device. device·
The driver is usually each device (for example, the video controller 16, the keyboard 30, the HDD 22, the FDD 2).
It is provided for each 4). In some cases, a single device is provided with a plurality of layers of device drivers (for example, a device driver for a PC card or a device driver for a network card).

Each device driver is appropriately loaded from the auxiliary storage device such as the HDD 22 into the main memory 13. The device driver includes a portion for physically and time-critically driving the corresponding device (for example, a portion for processing an IRQ or a DMA request). Such time critical processing part is HD
If you swap in from D22 etc. at any time, the processing time will not be in time, so with the work data
It is designed to reside on the memory 13 (that is, physical memory). The rest of the device driver is
It does not have to reside in the physical memory, and is appropriately swapped out to the HDD 22.

Operating System (OS): The operating system (OS) is the system 100.
Is a basic software for comprehensively managing hardware and software of the OS, such as OS / 2 ("OS
"/ 2" is a trademark of IBM Corp. in the US) or UNIX. The operating system is generally composed of a kernel (Kernel) area and a user area.

The kernel area is a group of basic functions for monitoring the operation of the entire system 100 and supporting the execution of various programs such as applications. The core portion of the kernel area includes a “file manager” for managing recording of files in an auxiliary storage device such as the HDD 22, a “scheduler” for managing the order and priority of task execution, and a memory area It includes a "memory manager" for allocation. A memory manager that supports virtual memory (described later) is specifically referred to as a "virtual memory manager (VM
M) ”. The program (hereinafter referred to as "power manager (PM)") defining the power management operation (hibernation routine and wake-up routine: described later) according to the present embodiment is a kernel. It exists in the core part of. This power manager may include a module for data compression / expansion for use when storing and restoring data in the HDD 22 (described later).

Since the core part of the kernel performs time-critical processing, it is made to reside on the physical memory together with its work data. These always exist in the physical memory even under the virtual memory system. On the contrary, the kernel area other than the core portion does not need to reside in the physical memory.

On the other hand, the user area mainly includes a function routine portion for supporting the application selected by the user. A "user interface"('s for interpreting commands from the user and transmitting them to the core part of the kernel and transmitting the response from the core part to the user.
(also referred to as "hell '") is included in this user area.
Also, a "window system" (for example, UNIX's) that executes window display on the LCD display 18 is used.
X Window 'and OS / 2'Presentati'
on Manager ') and a library (also called "shared library" or "dynamic link library (DLL)") that is a collection of functions and data for performing common processing by multiple software in the user area. included.

The user area is a portion interposed between the kernel and the user, and is not a time-critical program. Therefore, it is not necessary to make it resident in the physical memory. These may be appropriately swapped out to the HDD 22 or the like.

Application Program (AP):
The uppermost layer application program is a program that uses the system 100 for practical purposes, and corresponds to, for example, word processing software, database software, spreadsheet software, communication software, or the like.
In addition, a utility program (also referred to as a “tool”) for improving the usability of the user is a type of application. These applications do not need to be resident in the physical memory, and may be appropriately swapped out to the HDD 22 or the like.

Virtual addresses are allocated to these programs and their work data described above under the virtual storage system. The software configuration itself as shown in FIG. 2 is already well known in the art. Further, depending on the system 100, there may be a more complicated hierarchical structure, but the minute difference does not affect the implementation of the present invention. However, in considering the present invention, (1) not all of the program (and its work data) always exists in the main memory 13, and it is appropriately replaced with an auxiliary storage device such as the HDD 22. (swapping)
(2) In the program (and its work data), there is a "memory resident program" that must always exist in the physical memory and a "memory resident program" that can be appropriately swapped out. Please note that there is a "memory non-resident program".

Note that "memory non-resident" is called "pageable" in the sense that swapping can be performed in page units (described later), and conversely "memory resident" is referred to as "non-pageable (Non-pageable)". Pag
Sometimes referred to as "able)". The non-pageable area usually has a size of about 4 MB.

C. Memory space virtual storage system on PC 100 : PC 100 used for implementing the present invention
Employs a technology called "virtual memory," like many other PCs currently on the market. What is virtual memory?
By assigning a logical address (virtual address) to the auxiliary storage device such as D, it is handled as if it were a part of the main memory. The virtual memory space has a wide area of about 4 GB, for example. System 1
The virtual memory 00 allows the capacity of the main memory to be apparently larger than the actual physical size (for example, 32 MB), and enables large-scale programs and data to be handled. One of the effects of virtual memory is a powerful CPU with a high processing speed (for example, "PowerP" mentioned above).
The C 603e ") handles a vast memory area, thereby fully exerting its arithmetic function.

FIG. 3 is a schematic diagram showing a virtual storage system (well known). The physical capacity of the main memory 13 is, for example, about 32 MB (96 MB when added), whereas the virtual memory provided by the virtual storage system is 4 G.
It is a vast space of about B level. Naturally, only a small area of the virtual address can exist in the main memory 13. That is, the virtual address may be present in the main memory 13 or may be apparently already swapped out to the auxiliary storage device such as the HDD 22.

Access to the virtual memory is performed by referring to a virtual address. Further, the virtual memory space is generally divided and handled in units of pages (one page is 4 KB). Therefore, under the virtual storage system, in order to grasp the position of the virtual page in the physical memory, a page table (well known) having a structure as shown in FIG. 4 is generated. In the figure, one virtual address is formed of 32 bits, but the upper 10 bits are the directory offset, the next 10 bits are the page table offset, and the remaining 12 bits are the page offset. This is a field for storing. The directory offset is an offset value for the start address of the page directory, and the start address of the corresponding page table is recorded in the corresponding record in the page directory. The page table offset is an offset value for the start address of the page table, and the start address of the corresponding page frame and the attribute information of the page frame are recorded in the corresponding record in the page table. ing. Here, the attribute information is the access frequency (LRU) to the page frame.
And whether the page frame is pageable or non-pageable. The page offset is an offset value for the start address of the page frame, and is the lower bit itself of the physical address. In other words, (start address of page frame) +
The (page offset) represents the actual physical address. The page frame is the page itself on the physical address, and its contents are actual codes and data.

Since 10 bits are allocated to the directory offset, 1024 (= 10 ¹⁰ ) page tables can be addressed, and since 10 bits are allocated to the page table,
1024 (= 10 ¹⁰ ) page frames can be addressed. Also, one page frame is 4 KB
Have the size of. Therefore, the virtual memory space has a size of 4 GB (= 10 ¹⁰ × 10 ¹⁰ × 4 KB) as a whole.

The page table can be implemented by either hardware or software. However, in the latter case, the page table is stored in the memory resident area on the main memory 13.

Functions of Virtual Memory Manager: Virtual Memory Manager (VMM) which is a part of OS kernel
Is a program for managing the virtual memory space, and can appropriately use the above-mentioned page table.

One function of the virtual memory manager is mapping. Mapping is the translation of a virtual address into a physical address that actually contains data to allow access to the virtual memory space. For example, if the referenced virtual address exists in the physical memory as a result of mapping, the virtual memory manager passes the data at the corresponding address in the physical memory as it is to the access request source (for example, the application being executed by the CPU 11). . Also, the referenced virtual address is
If it does not exist in the memory 13, the file manager is requested to swap the data at the corresponding address in the HDD 22 into the main memory 13. At this time, if the main memory 13 is already full of other valid pages, the virtual memory manager swaps some other pages into the HDD 22 in order to reserve a page for swap-in. -Request the file manager to go out (pages to be swapped out are determined according to freshness. A method for prioritizing is, for example, LRU (Le
ast Recently Used)). However, the virtual memory manager cannot target the pages defined as non-pageable by the attribute information of the page table for swap-out.

Another function of the virtual memory manager is to manage the memory usage information of each page frame in the virtual memory space. Here, the memory usage information refers to whether the page frame is valid (that is, used in the process) or invalid (that is, unused or has a parity error). The virtual memory manager of this embodiment is
A "page frame database" that stores the frame memory usage information and the pointer to the page table in association with each other is constructed. In other words, the virtual memory manager can manage the memory usage information of each page frame in the form as shown in FIG. 5 by referring to the page table and the page frame database. It is possible to easily distinguish whether the frame is valid or invalid, whether it is in the physical memory 13 or the HDD 22, and if valid, whether it is memory-resident (non-pageable) or non-resident (pageable). The page frame database is placed in the memory resident area on the main memory 13.

The physical address corresponding to the virtual address,
The contents of the page frame database may change during page swapping. The virtual memory manager is also adapted to update these contents as changes occur.

The virtual memory system itself described in this section is already well known in the art. However, when considering the following item D, it should be noted that not all the pages in the main memory 13 are in use.

D. Power management by PC100
The operation of the PC 100 embodying the present invention has been described above. In this section, P
The operation of the present invention will be described together with the operation of C100.

D-1. Hibernation / wake
Up Routine FIG. 6 shows a routine for entering hibernation,
Also, a routine for returning from hibernation and restarting a task is shown in the form of a flowchart.
Here, the hibernation routine will be described first.

Events that should enter hibernation (hereinafter referred to as "hibernation event") include
2 of hardware event and software event
It is roughly divided into two. Hardware events include closing of the lid (LCD), reduction of the remaining capacity of the battery 42 (low battery), pressing of a main power switch (not shown), and the like. A software event is a double-click on the PM (Power Manager) icon.
Clicks, disappearance of system idle timers, etc.

The power management processor 45 constantly monitors the open / closed state of the lid, the capacity of the battery, and the pressing of the main power switch. When a predetermined event is detected, a hardware event is sent to the CPU 11. ing.
With this as a trigger, the control right of the system 100 is once transferred from the running OS or application to the PM event handler (the PM event handler is a part of the power manager) (step S10).
0). When the PM event handler determines that the cause of the hardware event is a hibernation event, the PM event handler proceeds to step S110 to enter the hibernation mode. On the other hand, if it is due to a software event, step S100 is skipped and the process directly jumps to step S110.

In step S110, the PM server in the user area of the OS displays the application (hereinafter referred to as "PM") which is interested in the power management operation.
(aware application)) and sends a notification of the hibernation request and its authentication response.
The PM ware application is physically connected to another independent device (another PC) via a network cable or a printer cable and is in communication, such as a network application or a print spooler. It is an application.
Such applications are PM aware because they can lose data in process due to inadvertent power management operations. Step S1
At 10, the positive or negative response from each PM aware application and the hibernation request are arbitrated. Then, if it is determined that the hibernation is to be performed, the process proceeds to the next step S120. If not, the hibernation request is ignored and the original state is returned.

In step S120, the PM server calls the PM system call in the kernel area of the OS. This transfers control of the system 100 to the PM core.

In step S130, the PM core causes each device driver (in particular, a device driver that physically operates hardware, “PM awa
re device driver ”), and sends a notification of the hibernation request and an authentication response. Each notified device driver saves necessary hardware context information in its own work area.
Typical examples of hardware context information are interrupt controller 26, DMA controller 25, video
It is the register value of each chip such as the controller 16 and the count value of the timer, and is also the data necessary to restart the task at the same time later. The PMAware device driver and its working area may be considered memory resident. In addition, the register value (that is, the context) of the CPU 11 is the PM value at the final stage of step S130.
The core itself saves in its own work area. However, if the acquisition of the authentication response from the PM aware device driver fails in step S130, the next step S1
Return PM system call without going to 40. As a result, the hibernation request is ignored,
Return to normal operation mode.

Next, a hibernation enter job for saving desired data in the main memory 13 to the HDD 22 is executed (step S14).
0). When the job ends, the power manager (P
M) indicates to the power management processor 45 that the system 10
Requests to stop power supply to all 0 electric circuits. In response to this request, the power management processor 45 rewrites the bit cell of the power control register 46 to stop the power supply (enter the hibernation mode). Along with this, the contents of the main memory 13 are naturally lost.

The hibernation enter job in step S140 is one of the important operations of the PC 100 according to the present invention, but a detailed description will be given in the following section D-2.

D-2. Hibernation enter
Job FIG. 7 shows a hibernation enter job for entering hibernation (step S140).
Is shown in more detail as a flowchart.

First, in step S141, a specific area on the main memory 13 is left, and swapping is performed as much as possible.
Do out. Swap out here is power
The manager makes a request to the virtual memory manager. In addition, "Main memory 1
"Specific area on 3" refers to all memory-resident or non-pageable areas and some pageable areas that have been used relatively recently, and the virtual memory manager uses the page table (described above). It can be detected by referring to the attribute information in the page frame database and the page frame database (described above). Also, "swap out as much as possible" means swapping out old data that is no longer accessed as much as possible, for example, according to the LRU logic. The size of the non-memory area, that is, the area that should not be swapped out in the pageable area is usually about 12 MB from the viewpoint of performance at wake-up. Therefore, the size of the area left without being swapped out after step S141 is 16 (= 4 + 12) MB.
It is a degree. This size is considered to be approximately constant as memory size is expanded. The screen information displayed on the LCD display 18 will be swapped out together with the window system as work data of the window system (for example, X Window) in the pageable area (the contents of the VRAM 17 are directly stored in the HDD 22). Note that it does not save to).

Next, the power manager
The memory usage information of the entire memory 13 is acquired (step S142). Here, "memory usage information of the entire main memory 13" refers to records of all page frames existing in the main memory 13 in the page frame database (described above). The power manager can distinguish the valid page (that is, the page storing the data / code being used by the process) in the main memory 13 by referring to the memory usage information.

Next, the power manager saves only the valid page in the HDD 22 in the area left on the main memory 13 without being swapped out (step S143). The valid pages saved in this step include memory-resident or non-pageable areas, as well as some pageable areas. In addition, the memory usage information acquired in the previous step S142, power
The manager itself is also included in the valid page. The valid page saved in the HDD 22 in this step is hereinafter referred to as "hibernation volume".

In step S143, the HDD 2
Before saving to 2, the hibernation volume may be data compressed. The main method of data compression may be the "slide dictionary method" or the "dynamic dictionary method" already known to those skilled in the art. With such a data compression method, the size of the hibernation volume can be reduced to about 5
It can be reduced to 0%. In this case, the power manager may include a tool for data compression and a tool for decompressing it. However, power
The code part for the wake-up process (described later) of the manager is saved without being compressed because it is executed before the data decompression process.

Then, in step S144, the configuration data (hardware configuration information) of the system 100 is transferred to a predetermined address (provisionally'A
Save as AA '). The configuration data is the data examined by POST when the system 100 is started up, and is written on the main memory 13, for example.

Next, in step S145, the location information of the hibernation volume, that is, the storage location in the HDD 22 is saved in a predetermined address (probably'BBB ') in the HDD 22.

Next, in step S146, a symbol indicating that the system 100 has been powered off through such a hibernation enter job (hereinafter,
"Hibernation signature") HDD
The data is written in a predetermined address in 22 (provisionally referred to as'CCC '). The hibernation signature is composed of, for example, data of about 8 bytes. In this way, the hibernation enter job ends successfully.

The main features of the hibernation enter job routine according to the present embodiment are (1) that the memory non-resident data is already swapped out in step S144, and (2) the main memory 13 There are two points, that is, only valid pages in the area remaining in the above are set to the hibernation volume. Since the size of the memory resident area (or effective page) does not depend much on the size of the physical memory, according to the former (1), the size of the hibernation volume can be made almost constant regardless of the addition of memory. . The latter (2)
It is possible to downsize the hibernation volume in advance (about several MB). Further, if the hibernation volume is subjected to data compression processing and saved, the disk access time to the HDD 22 can be largely omitted, and the processing time can be further shortened. Also, of course,
It also saves the hibernation file area of the HDD 22.

D-3. Wake-Up Routine In this section, returning to FIG. 6 again, the wake-up routine will be described.

When the main power switch is turned on while the system 100 is powered off (step S
160), similarly to the normal power-on reset (POR), first, the POST program stored in the ROM 15 is executed (step S170).

In the process of executing POST, the system 10
Check the 0 configuration again. Also, HD
The predetermined address CCC of D22 is accessed to check the hibernation signature. If the signature does not exist, it is determined that the power-on this time is POR, and the OS is normally booted (that is, the wake-up job is not executed). If the signature is written, the signature is erased for reuse, and the process proceeds to the subsequent step S180.

In step S180, step S143
The hibernation volume saved in the HDD 22 is written in the main memory 13. The storage location of the hibernation volume is HDD22.
It can be found by accessing a predetermined address BBB in the above. Further, if the hibernation volume is data-compressed, the number of times of disk access is reduced accordingly, and the processing time is shortened. Step S18
0 is executed by the code in the ROM 15, and the final code jumps to the entry point (step S190) of the wake-up code on the main memory 13.

The process in step S180 is as follows.
It does not mean that the hibernation volume is completely restored to its original location, it just transfers the data in chunks for the moment. Also, if step S
If the data is compressed in 143, it remains in the compressed state and is not expanded. However, only the wake-up code is not compressed (described above).

In S190, the configuration data checked in step S170 is compared and collated with that before power-off. The configuration data before power off is HD in step S144.
It is stored in the predetermined address AAA of D22 (described above).
If they match, the process proceeds to the subsequent wake-up job routine (step S200). Conversely, if the two do not match, the system 10 is turned off during power off.
0 peripheral devices are attached and detached, and system 1
00 cannot return to the state immediately before entering hibernation. Therefore, in this case, the OS is normally booted without performing the subsequent wake-up routine.

In the wake-up job routine of step S200, the restore operation of the hibernation volume on the main memory 13 is mainly performed.
The wake-up job is the PC 100 according to the present invention.
This is one of the important operations of the above, but a detailed description is given in the following section D-4.

Then, returning to step S130, the CPU
After restoring the 11 contexts, the PM core
Wake-up notification and authentication response are performed with the Maware device driver. Upon receiving the notification, the device driver restores the hardware context information such as the register value of the chip to a predetermined location or initializes it. Then, step S
Returning to 120, the PM system call that was being called is returned.

Next, returning to step S110, the PM server sends a wake-up notification and an authentication response to each PM aware application. In addition,
The application is the HDD 22 in step S141.
Since it is still swapped out to the main memory 13, it is appropriately swapped in to the main memory 13 at the time of notification / authentication response.

In this way, the system 100 can complete the wake-up operation and resume the task from the same point in time that the hibernation event occurred.

D-4. Wake Up Job Figure 8 shows the wake up job from hibernation mode.
The wake-up job (step S200) for uploading is shown in more detail as a flowchart.

First, in step S201, memory usage information is acquired from the hibernation volume.

Then, in step S202, only valid pages are stored in the main memory 1 based on the memory usage information.
3 is restored to a predetermined physical address. In this way, the wake-up job ends successfully. However, the data swapped out in step S141 remains unrestored in the main memory 13.

When the hibernation volume is compressed in the hibernation enter job, the above steps S201 and S2 are performed.
In 02, of course, the data is expanded and then restored.

The main feature of the wake-up job routine according to the present embodiment is that only the hibernation volume, that is, the valid page portion on the main memory 13 is restored. As described above, the hibernation volume is sufficiently downsized and has a substantially constant size regardless of the size of the physical memory. Therefore, the processing time required for the wake-up job becomes extremely short.

E. The present invention has been described in detail with reference to specific embodiments. However, it is obvious that those skilled in the art can modify or substitute the embodiments without departing from the scope of the present invention. That is, the present invention has been disclosed in the form of exemplification, and should not be limitedly interpreted.
In order to determine the gist of the present invention, the section of the claims described at the beginning should be taken into consideration.

[0099]

As described above in detail, according to the present invention,
It is possible to provide an information processing system capable of executing a power management operation and a return operation from the power management at a higher speed, and a control method thereof.

For example, according to the information processing system and the control method thereof according to the first to third aspects of the present invention, when the system transits to hibernation, the main
Only valid data in memory is saved to HDD. Also, when waking up from hibernation, naturally only valid data is restored in the main memory. Therefore, the processing time required for execution of hibernation and wakeup (in particular, data store and restore) is significantly reduced. Further, since the image of the entire main memory is not stored, the size of the storage area (hibernation file) to be prepared in the HDD can be greatly saved. Main memory is not only the area where valid data (that is, currently used or that may be used in the future) is written, but invalid area (that is, unused area or area where parity error has occurred) It also contains a lot. Therefore, those skilled in the art will be able to fully understand the effects realized by excluding such invalid areas from the targets of data store and restore, that is, the effects on processing time and storage area problems.

Further, according to the information processing system and the control method thereof according to the fourth to eighth aspects of the present invention, when the transition to the hibernation mode is performed, the desired image in the main memory is data-compressed. To be stored in the HDD. Also, when waking up, it is natural that the main
Restored to memory. Generally, the data on the main memory has regularity, and a compression effect of about 50% can be expected. Therefore, it is possible to significantly reduce the size of the hibernation file in the HDD. In particular, if a CPU with a recent powerful power (for example, PowerPC 603e jointly developed by IBM Corp., Motorola Corp., Apple Corp., USA) is used, data compression / decompression can be executed at extremely high speed.
There is almost no effect on the processing time. Rather, the processing time required for data store and data restoration can be significantly reduced due to the reduction in the number of disk accesses accompanying the reduction in data size, and the extra processing time for data compression / decompression can be absorbed. Let's do it.

[Brief description of drawings]

FIG. 1 is a personal computer used for carrying out the present invention.
FIG. 1 is a diagram schematically showing a hardware configuration of a computer (PC) 100.

FIG. 2 is a personal computer used for carrying out the present invention.
FIG. 3 is a diagram schematically showing a hierarchical structure of software executed on a computer (PC) 100.

FIG. 3 is a schematic diagram showing a virtual storage system.

FIG. 4 is a diagram showing a structure (known) of a page table.

FIG. 5 is a diagram schematically showing memory usage information of each page frame that can be managed by a virtual memory manager.

FIG. 6 is a flowchart showing a routine for entering hibernation and a routine for returning from hibernation and restarting a task.

FIG. 7 is a detailed flowchart showing a hibernation enter job for entering hibernation.

FIG. 8 is a wake-up job for waking up from hibernation mode,
It is the figure which made it into a flowchart in more detail.

[Explanation of symbols]

11 ... CPU, 12 ... Bus, 13 ... Main memory, 1
4 ... Memory controller, 15 ... ROM, 16 ... Video controller, 17 ... VRAM, 18 ... LCD, 1
9 ... Audio controller, 20 ... Amplifier, 22 ...
HDD, 23 ... FDC, 24 ... FDD, 25 DMA controller, 26 ... Interrupt controller, 27 ... I / O
Controller, 29 ... KMC, 30 ... Keyboard, 31
... Mouse, 32 ... OSC, 33 ... RTC, 34 ... CMO
SRAM, 35 ... Coin battery, 36 ... EEPR
OM, 41 ... AC adapter, 42 ... Battery, 43 ... D
C / DC converter, 44 ... FET switch, 45 ... Power management processor, 46 ... Power management processor, 100
…Personal computer.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Tomohiro Miyahira 1623 Shimotsuruma, Yamato-shi, Kanagawa 14 Japan AIBM Co., Ltd. Yamato Works (72) Inventor Akihiro Nakao Yamato, Kanagawa 1623 Shimotsuruma 14 Japan AIBM Co., Ltd. Yamato Works

Claims (22)

[Claims] 1. Information of a type including a processor, a volatile memory, and a non-volatile auxiliary storage device, which stops power supply to a predetermined electric circuit after storing the contents of the memory in the auxiliary storage device. The processing system further includes a memory usage information management unit that manages whether each area in the memory is a valid area or an invalid area. Information processing system characterized by storing only contents in the auxiliary storage device 2. A processor, a volatile memory, a non-volatile auxiliary storage device, and, after storing the contents of the memory in the auxiliary storage device in response to the occurrence of a predetermined event, transferring the data to a predetermined electric circuit. In an information processing system including a power management means for stopping power supply, further, a memory use information management means for managing whether each area in the memory is an effective area or an invalid area, wherein the power management means is provided when power supply is stopped. In the information processing system, according to the memory use information management means, only the contents of the effective area of the memory are stored in the auxiliary storage device. 3. The valid area is an area containing data which is currently used or may be used in the future by the processor, and the invalid area is an unused area and a parity area.
The information processing system according to claim 1 or 2, which is an area in which an error occurs. 4. The information processing system according to claim 1, wherein the predetermined electric circuit includes the memory. 5. The information processing system according to claim 1, wherein the storage of the contents of the memory in the auxiliary storage device when power supply is stopped is performed after data compression. 6. The information processing system according to claim 2, wherein the power management means stores the data in the auxiliary storage device after compressing the data. 7. A method for controlling an information processing system of a type in which the contents of a volatile memory are stored in a non-volatile storage device in response to the occurrence of a predetermined event and then transition to a power saving operation mode is performed. The first stage of detecting the occurrence,
A second step of determining whether each area of the volatile memory is a valid area or an invalid area; a third step of storing only the contents of the valid area of the volatile memory in the nonvolatile storage device; And a fourth step of transiting to an operation mode. 8. The valid area is an area containing data which is currently used or may be used in the future, and the invalid area is an unused area and an area in which a parity error has occurred. The method for controlling the information processing system according to claim 7. 9. The control method for an information processing system according to claim 7, wherein the power saving operation mode is an operation mode in which power supply to an electric circuit including the volatile memory is stopped. 10. The control of the information processing system according to claim 7, wherein in the third step, the contents of the effective area of the volatile memory are data-compressed and then stored in the auxiliary storage device. Method 11. The information processing system according to claim 5, wherein the memory resident data is restored from the auxiliary storage device to the memory after decompressing the data. 12. The power management means restores the memory resident data saved in the auxiliary storage device to the memory after decompressing the data.
Information processing system described in 13. An information processing system including a processor, a volatile memory, and a non-volatile auxiliary storage device, wherein the content of the memory is stored in the auxiliary storage device to stop power supply to a predetermined electric circuit. When storing, the information processing system is characterized in that the contents of the memory are compressed and then stored. 14. A processor, a volatile memory, a non-volatile auxiliary storage device, and after storing the contents of the memory in the auxiliary storage device in response to the occurrence of a predetermined event, a predetermined electric circuit is stored. In an information processing system including a power management means for stopping power supply, the power management means stores the contents of the memory in the auxiliary storage device after compressing the data. 15. The information processing system according to claim 13, wherein the data saved in the auxiliary storage device is restored to the memory after decompressing the data. 16. The information processing system according to claim 13, wherein the predetermined electric circuit includes the memory. 17. A method for controlling an information processing system of a type in which the contents of a volatile memory are stored in a non-volatile storage device in response to the occurrence of a predetermined event and then transition to a power saving operation mode is performed. A first step of detecting the occurrence, a second step of data-compressing the contents of the volatile memory, and a third step of storing the data-compressed contents of the volatile memory in the non-volatile storage device. And a fourth step of transitioning to a power saving operation mode. 18. The information according to claim 17, wherein when returning from the power saving operation mode, the data saved in the nonvolatile storage device is expanded and then restored in the volatile memory. Processing system control method 19. The control method of an information processing system according to claim 17, wherein the power saving operation mode is an operation mode in which power supply to an electric circuit including the volatile memory is stopped. 20. The method according to claim 1, wherein the program including a sequence for executing stop and resumption of power supply is a part of an operating system loaded in the memory. The information processing system according to claim 13 or 14. 21. The information according to claim 7, wherein the program for executing the first to fourth steps is a part of an operating system loaded in the volatile memory. Processing system control method 22. The information of claim 17, wherein the program for performing the first to fourth steps is part of an operating system loaded in the volatile memory. Processing system control method