JP3702233B2 - Information processing system and program execution mode control method - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to an information processing system such as a personal computer and a program execution mode control method.
[0002]
[Prior art]
In recent years, so-called “high-speed ROM” functions are used in information processing systems such as personal computers in order to improve system performance. The “high-speed ROM” function is a function for reading the contents of a low-speed ROM device from a RAM device that can be accessed at high speed.
[0003]
Specifically, when the system is powered on, the system BIOS (Basic Input Output System) is copied from the ROM in which it is stored onto the RAM constituting the main memory, and then the system BIOS on the RAM is executed. That's it. This function is based on the assumption that reading from RAM is faster than reading from ROM, and that there is no difference in system reliability and stability using either ROM or RAM. It is.
[0004]
[Problems to be solved by the invention]
However, there are cases where the system area on the RAM where the system BIOS is copied cannot be completely protected due to the function restriction of the chip set to be used. In this case, there is no problem when all other software is terminated and only the dedicated system utility program is executed, for example, when the system environment is changed. During operation, there is a possibility that malicious software or software with improper behavior may operate, and there is a risk that the system area on the RAM is destroyed by the software.
[0005]
On the other hand, the method of always reading the system BIOS from the ROM causes a problem that the system performance is deteriorated and the ROM rewriting operation for updating the BIOS cannot be executed during the operation of the operating system.
[0006]
The present invention has been made in view of the above circumstances, and provides an information processing system and a program execution mode control method capable of ensuring a good balance between system performance and system reliability and stability. Objective.
[0007]
[Means for Solving the Problems]
In order to solve the above-described problems, an information processing system according to the present invention includes a CPU, a non-volatile memory in which a system BIOS including a BIOS driver group and a system management program is stored, and an operating system temporarily stored during operation of the operating system. a main memory that is, at power up means for copying from the nonvolatile memory the BIOS drivers in the main memory, to perform a rewrite operation of the non-volatile memory during operation of the operating system, the BIOS the system management program from the first mode to be executed is read from the nonvolatile memory when the system management interrupt signal is inputted to the CPU and executes the drivers on the main memory, the system management to the main memory Copy the program And a switching means for switching to a second mode for reading and executing the system management program from the main memory when a system management interrupt signal is input to the CPU .
[0008]
In this information processing system, first and second modes are prepared as execution modes for executing the system BIOS . In the first mode BIOS drivers runs in the main memory, the system management program the runs while reading from the nonvolatile memory, also in the second mode is copied system management program on the main memory, the system management program Is executed while reading from the copy area on the main memory. Switching from the first mode to the second mode is performed when the nonvolatile memory is rewritten during the operation of the operating system. By preparing a mechanism for switching the execution mode of the system BIOS during the operation of the operating system in this way, the execution mode of the system BIOS can be dynamically switched according to the system operating environment. It is possible to ensure a good balance between stability and stability.
[0009]
Further, in particular, as the CPU, a memory having a cache memory that performs a cache operation on a code or data within a memory address range set to cache enable in a memory address space accessible by the CPU is used. A memory to which the non-volatile memory is allocated within the memory address space of the CPU when the first execution mode is used so that the contents of the non-volatile memory are cached in the cache memory in the first mode It is preferable to set the address range to cache enable. Thus, by setting the contents of the nonvolatile memory as a cache target, it is possible to ensure sufficient system performance even in the first mode.
[0010]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the drawings.
FIG. 1 shows the configuration of an information processing system according to an embodiment of the present invention. This information processing system is, for example, a notebook-type personal computer that can be driven by a battery. The computer main body includes a processor bus 1, a PCI bus 2, an ISA bus 3, a CPU 11, a host bridge 12, and a main memory as shown in the figure. 13, a display controller 14, a PCI-ISA bridge 15, an I / O controller 16, a hard disk drive (HDD) 17, a flash BIOS-ROM 18, and the like are provided.
[0011]
The CPU 11 is for controlling the operation of the entire PC, and executes an operating system (OS), various application programs, a BIOS update utility, and the like loaded into the main memory 13. The main memory 13 is composed of DRAM. The BIOS update utility is software for rewriting the flash BIOS-ROM 18. This BIOS update utility is a kind of application program configured to operate under the operating environment of the OS, and the BIOS update can be executed under the operating environment of the OS.
[0012]
As the CPU 11, one that supports a system management interrupt SMI (SMI) is used. That is, the CPU 11 has an operation mode for realizing a system management function called a system management mode (SMM) in addition to a normal operation mode for executing an operating system, applications, and the like.
[0013]
When a system management interrupt (SMI) is issued to the CPU 11, the operation mode of the CPU 11 is switched from the normal operation mode (real mode, protect mode, or virtual 86 mode) to SMM. In SMM, a system management program is executed. The system management program is stored in advance in the flash BIOS-ROM 18 as one of the system BIOS (SM-BIOS).
[0014]
In the present embodiment, as a program execution mode of the flash BIOS-ROM 18, a “ROM operation” mode in which a system BIOS stored in advance in the flash BIOS-ROM 18 is executed while being read from the flash BIOS-ROM 18 as necessary, A “RAM operation” mode is prepared in which the system BIOS is copied to a specific area on the main memory 13 and executed while reading from the specific area on the main memory 13. “ROM operation” and “RAM operation” can be dynamically switched during the OS operation according to the system operating environment at that time.
[0015]
The host bridge 12 is a bridge device that bi-directionally connects the CPU bus 1 and the PCI bus 2, and has a built-in memory control function for controlling access to the main memory 13. The display controller 14 controls an LCD and an external CRT used as a display monitor of this PC.
[0016]
The PCI-ISA bridge 15 is a bridge that connects the PCI bus 2 and the ISA bus 3, and can operate as a bus master of the PCI bus 2. The PCI-ISA bridge 15 includes an SMI generation circuit 151 for generating the above-mentioned SMI in addition to a circuit for executing an operation necessary for rewriting the flash BIOS-ROM 18. The SMI generation circuit 151 generates an SMI signal when a specific register in the PCI-ISA bridge 15 is accessed by software. When BIOS update is started by the BIOS update utility, the BIOS update utility notifies the system BIOS of that fact by an SMI signal.
[0017]
The I / O controller 16 incorporates a bus master IDE controller for controlling IDE devices such as the HDD 17 used as secondary storage. The bus master IDE controller can operate as a bus master for data transfer between the HDD 17 and the main memory 13. The I / O controller 16 can also control a DVD drive or a CD-ROM drive.
[0018]
The flash BIOS-ROM 18 is for storing the system BIOS as described above, and is realized by a flash memory (flash EEPROM) that is an electrically rewritable non-volatile memory so that the BIOS can be updated by software. Has been. The system BIOS includes a POST (PowerON Self Test) routine executed when the PC is powered on or restarted, a BIOS driver group for controlling various I / O devices, a BIOS setup routine for setting the system environment, and the like. It is structured and used to directly control the hardware in the computer.
[0019]
The flash BIOS-ROM 18 also includes an SM-BIOS and an SMI handler. The SMI handler is an interrupt handler that is executed by the CPU 11 when an SMI occurs, and is used to activate the SM-BIOS corresponding to the SMI occurrence factor.
[0020]
Next, the “ROM operation” and “RAM operation” in the present embodiment will be described with reference to FIG.
There are several options for the method of executing the system BIOS (especially SM-BIOS) depending on the specifications and restrictions of the CPU and chipset to be used. The following are some of them.
[0021]
I: Operates with the cache on on the flash BIOS-ROM 18.
II: The area that opens and closes in synchronization with the SMI on the main memory 13 is used with the cache off.
III: The area that is always open on the main memory 13 is used with the cache on.
[0022]
The performance is higher in the order of III, I, and II (III and I have no sense of incongruity as the user's experience speed, but II can be a problem). Reliability is high in the order of I or II (both are equivalent) and III (III is not hidden from general OS and software, and can be easily destroyed by carelessness or malicious). II and III can realize specific functions (functions that cannot be realized if there is an operation in ROM, such as rewriting BIOS-ROM 18 during OS operation). It is I that cannot be realized.
[0023]
Therefore, in this embodiment, I is used for both performance and reliability during normal operation (when the user can execute arbitrary software on the OS). When the trigger for operating the specific function is received, the program on the BIOS-ROM 18 is copied to the area III, and the program operates on the III until the specific function is completed. Hereinafter, I is referred to as “ROM operation” mode and III is referred to as “RAM operation” mode.
[0024]
In the “ROM operation” mode, as shown in FIG. 2, the BIOS-ROM 18 is assigned to a part of the memory address range in the memory address space of the CPU 11, and the system BIOS is executed while being read from the BIOS-ROM 18. Is done. In this case, the memory address range to which the BIOS-ROM 18 is assigned is set to cache enable. That is, the CPU 11 has a cache memory that performs a cache operation on a code or data within a memory address range set to cache enable in a memory address space accessible by the CPU 11. In the mode, the memory address range to which the BIOS-ROM 18 is allocated is set to cache enable.
[0025]
As described above, the present embodiment is configured to execute the “ROM operation” mode with the cache ON, and in this way, a certain system performance can be obtained in the “ROM operation” mode. Which memory address range of the CPU 11 is set to cache enable can be controlled using a register in the CPU 11.
[0026]
In the “RAM operation” mode, the contents of the BIOS-ROM 18 are copied to a specific area on the main memory 13, and the system BIOS is executed while being read from the specific area. The memory address range corresponding to the specific area is set to cache enable.
[0027]
Next, switching between “ROM operation” and “RAM operation” will be described with reference to FIG.
[0028]
As described above, the system BIOS is executed in the “ROM operation” mode during the normal operation. When an event indicating switching from “ROM operation” to “RAM operation” occurs, the content of the BIOS-ROM 18 is copied to a specific area on the main memory 13 in response to the event, and from “ROM operation” to “RAM operation”. Is switched to “operation”. The occurrence of a switching event from “ROM operation” to “RAM operation” is notified to the system BIOS by the SMI.
[0029]
Even during normal operation, it is not necessary to execute all the system BIOS in the BIOS-ROM 18 from the ROM, and some system BIOS can be executed on the main memory 13. In the following, during normal operation, only SM-BIOS is executed in the “ROM operation” mode, and when an event indicating switching from “ROM operation” to “RAM operation” occurs, SM-BIOS is stored in the main memory 13. It is assumed that the SM-BIOS execution mode is switched from the “ROM operation” mode to the “RAM operation” mode.
[0030]
Next, the flow of processing executed by the system BIOS will be described with reference to the flowchart of FIG.
[0031]
When the computer is turned on, first, a POST process is executed by the system BIOS, and various hardware are initialized and tested (step S101). In the POST process, the system BIOS further copies the SMI handler and the BIOS driver group to the main memory 13 (SM-BIOS is not copied and is executed in the “ROM operation” mode). In this case, the system BIOS sets the memory address range corresponding to at least the SM-BIOS in the BIOS-ROM 18 to cache enable. The system BIOS also sets the memory address range on the main memory 13 corresponding to the SMI handler and the BIOS driver group to cache enable.
[0032]
Thereafter, an OS boot process for starting the OS is executed (step S102). During normal operation after OS startup, the SM-BIOS is executed in the “ROM operation” mode. That is, when the SMI is generated, the CPU 11 executes an interrupt process, and the SM-BIOS is executed in the “ROM operation” mode in the interrupt process. In this case, in the interrupt process, the SMI handler is first executed, and the cause of the interrupt is examined by the SMI handler. Then, the SM-BIOS in the BIOS-ROM 18 corresponding to the system management service requested by the interrupt factor is called by the SMI handler, and the SM-BIOS is read from the BIOS-ROM 18 and executed.
[0033]
On the other hand, when the interrupt factor is a ROM / RAM switching event (YES in step S103), the SMI handler copies the SM-BIOS from the BIOS-ROM 18 to a specific area on the main memory 13, and stores the specific area. Set cache enable. Thereafter, when the system management service is requested, the SMI handler calls the SM-BIOS on the main memory 13 corresponding thereto.
[0034]
That is, as shown in the flowchart of FIG. 5, the SM-BIOS is in the “ROM operation” mode every time a system management service is requested, or in “RAM operation” after copying to the main memory 13. In the “ROM operation” mode, the “ROM operation” mode is set so that the corresponding SM-BIOS is read from the BIOS-ROM 18 and in the “RAM operation” from the main memory 13. Or the “RAM operation” mode, the memory address for reading the SM-BIOS is switched (steps S112 and S113).
[0035]
Next, with reference to FIG. 6, a flow of a series of processes when performing BIOS update will be described.
[0036]
As described above, during normal operation, the system BIOS (SM-BIOS) is executed in the “ROM operation” mode. When the user activates the BIOS update utility during the OS operation, the BIOS update utility notifies the system BIOS of the start of BIOS update through a register in the PCI-ISA bridge 15. In this case, SMI is input to the CPU 11 in response to register access by the BIOS update utility. Thereby, the SMI handler is executed.
[0037]
When the SMI handler detects that the SMI occurrence factor is a BIOS update start notification event, the SM-BIOS is copied from the BIOS-ROM 18 to the main memory 13 and the execution mode of the SM-BIOS is switched to the “RAM operation” mode. Thereafter, a BIOS update process is started in which a new BIOS image is read from the location designated by the BIOS update start notification from the BIOS update utility and written into the BIOS-ROM 18. When the BIOS update process ends, an end notification is sent from the system BIOS to the BIOS update utility.
[0038]
The BIOS update utility issues a shutdown request or shutter down and reboot request to the OS, and causes the OS to execute shutdown processing or shutter down and reboot processing. By the SMI, for example, when an event such as docking between the expansion unit and the computer main body occurs between the time when the execution mode of the SM-BIOS is switched to the “RAM operation” mode and the OS is shut down. When the system management service is requested, the SM-BIOS is read from the main memory 13 and executed.
[0039]
Next, the flow of processing executed by the system BIOS when updating the BIOS will be described with reference to the flowchart of FIG.
[0040]
As described above, when the computer is turned on, first, the POST process is executed by the system BIOS, and various types of hardware are initialized and tested (step S201). In the POST process, the system BIOS further copies the SMI handler and the BIOS driver group to the main memory 13 (SM-BIOS is not copied and is executed in the “ROM operation” mode). In this case, the system BIOS sets the memory address range corresponding to at least the SM-BIOS in the BIOS-ROM 18 to cache enable.
The system BIOS also sets the memory address range on the main memory 13 corresponding to the SMI handler and the BIOS driver group to cache enable.
[0041]
Thereafter, an OS boot process for starting the OS is executed (step S202). During normal operation after OS startup, the SM-BIOS is executed in the “ROM operation” mode. If an SMI due to a BIOS update start event occurs during normal operation (YES in step S203), the SMI handler copies the SM-BIOS from the BIOS-ROM 18 to a specific area on the main memory 13, and cache-enables the specific area. (Step S204). Thereafter, when the system management service is requested, the SMI handler calls the SM-BIOS on the main memory 13 corresponding thereto.
[0042]
Next, the SMI handler starts a BIOS update process of reading a new BIOS image from a location instructed by the BIOS update start notification from the BIOS update utility and writing it into the BIOS-ROM 18 (step S205). When the BIOS update process ends, the SMI handler sends an end notification to the BIOS update utility (step S206).
[0043]
As described above, in the present embodiment, during normal operation, the cache-on “ROM operation” mode, which is excellent in performance and reliability, is used, and when a trigger for operating a specific function is received, the system BIOS is A process of copying from the BIOS-ROM 18 onto the main memory 13 and switching to the “RAM operation” mode is executed. As a result, it is possible to ensure a good balance between system performance and system reliability and stability.
[0044]
Further, the present invention is not limited to the above-described embodiment, and various modifications can be made without departing from the scope of the invention in the implementation stage. Further, the above embodiments include inventions at various stages, and various inventions can be extracted by appropriately combining a plurality of disclosed constituent elements. For example, even if some constituent requirements are deleted from all the constituent requirements shown in the embodiment, the problem described in the column of the problem to be solved by the invention can be solved, and the effect described in the column of the effect of the invention Can be obtained as an invention.
[0045]
【The invention's effect】
As described above, according to the present invention, it is possible to ensure a good balance between system performance and system reliability and stability by dynamically switching the execution mode of the system program according to the system operating environment. It becomes.
[Brief description of the drawings]
FIG. 1 is a block diagram showing a configuration of a computer system according to an embodiment of the present invention.
FIG. 2 is a view for explaining “ROM operation” and “RAM operation” in the system according to the embodiment;
FIG. 3 is a view for explaining switching between “ROM operation” and “RAM operation” in the system of the embodiment;
FIG. 4 is an exemplary flowchart showing a flow of processing executed by a system BIOS used in the system according to the embodiment;
FIG. 5 is an exemplary flowchart illustrating a processing procedure of SM-BIOS used in the system according to the embodiment;
FIG. 6 is an exemplary view for explaining a flow of a series of processes when BIOS update is performed in the system according to the embodiment;
FIG. 7 is an exemplary flowchart showing the flow of processing executed by the system BIOS when updating the BIOS in the system according to the embodiment;
[Explanation of symbols]
11 ... CPU
12 ... Host bridge 13 ... Main memory 15 ... PCI-ISA bridge 16 ... I / O controller 18 ... Flash BIOS-ROM
151. SMI generation circuit

Claims (5)

CPU,
A nonvolatile memory storing a system BIOS including a BIOS driver group and a system management program ;
Main memory in which the operating system is temporarily stored during operation of the operating system;
Means for copying the BIOS driver group from the non-volatile memory to the main memory at power-on;
When executing the rewriting operation of the nonvolatile memory during the operation of the operating system , the system management program is executed when the BIOS driver group is executed on the main memory and a system management interrupt signal is input to the CPU. The system management program is copied to the main memory from the first mode that is read from the nonvolatile memory and executed, and the system management program is read from the main memory when a system management interrupt signal is input to the CPU. the information processing system characterized by comprising a switching means for performing switching to a second mode for executing. The CPU includes a cache memory that performs a cache operation on a code or data within a memory address range set to cache enable in a memory address space accessible by the CPU,
2. The apparatus according to claim 1, further comprising means for setting a memory address range corresponding to the system management program in the nonvolatile memory in a cache enable in the memory address space of the CPU in the first mode. Information processing system. 3. The information processing system according to claim 2, further comprising means for setting a memory address range corresponding to an area on the main memory to which the BIOS driver group is copied in the first mode to cache enable. . The switching means is
When the system management interrupt signal is input to the CPU, it is activated by the CPU to determine whether the current execution mode of the system management program is the first mode or the second mode, and the determination result 2. The information processing system according to claim 1, further comprising means for switching a memory address for reading the system management program based on the information. A non-volatile memory in which a system BIOS including a BIOS driver group and a system management program is stored, and a cache operation using a cache memory can be performed on a code or data within a memory address range set to cache enable. A program execution mode control method applied to an information processing system having a CPU and a main memory,
When the power is turned on, the BIOS driver group is copied from the nonvolatile memory to the main memory,
When executing the rewriting operation of the non-volatile memory during the operation of the operating system, the system management program is executed when the BIOS driver group is executed on the main memory and a system management interrupt signal is input to the CPU. The system management program is copied to the main memory from the first mode that is read from the nonvolatile memory and executed, and when the system management interrupt signal is input to the CPU, the system management program is read from the main memory. A program execution mode control method characterized by executing switching to a second mode to be executed.

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