JP5894044B2 - Method and portable computer for storing data in a hybrid disk drive - Google Patents

Description

  The present invention relates to a technique for expanding the use range of a nonvolatile semiconductor memory that functions as a cache of a hybrid disk drive, and more particularly to a technique for controlling the power state of a computer using a hybrid disk drive.

  In portable computers, it is particularly important to ensure battery operating time. Therefore, the portable computer transitions to various sleeping states defined in ACPI. In ACPI, in addition to the power-on state (S0 state) and the power-off state (S5 state), a sleeping state from the S1 state to the S4 state is defined. The recovery time becomes longer. There is a trade-off between reducing standby power, which affects battery operation time, and reducing recovery time, which affects usability for immediate use when you want to use it.

  In the S4 state (also referred to as the hibernation state), which consumes the least amount of power in the sleeping state, the main memory storage state (hereinafter referred to as saved data) during power-on is referred to as a hard disk drive (HDD) or solid state. -Most devices are powered off after being stored in a state drive (SSD) or other disk drive, and when recovering, the saved data is restored from the disk drive rather than starting from the power-off state. Time can be shortened.

  Intel Corporation (Intel is a registered trademark) provides a technology called Intel Smart Response Technology (ISRT) as part of a RAID management tool called Intel Rapid Storage Technology (IRST). ISRT is a technology that realizes high-speed reading by using an SSD connected to an interface called Mini SATA as an HDD cache.

  In ISRT, the OS is stored only in the HDD, and in the SSD, the data area and the cache area are partitioned by partitions. When the host issues a write command, data is written to both the SSD and the HDD as in write-through caching. Or, like write-back caching, data is first written only to the SSD and written to the HDD during idle. In response to a read command issued by the host, when there is data in the SSD, it is read from the SSD, and when there is no data in the SSD, it is read from the HDD and returned.

  Patent Document 1 discloses a first hibernate that hibernates data in an NVRAM prepared separately from a hard drive. When the OS writes the current system state in the hibernate area of the DRAM, the embedded processor (EP) shuts down the CPU core. The EP then supplies power only to the circuitry necessary to copy the hibernate area to NVRAM and wake it up. When resuming, the EP returns the context from NVRAN to the DRAM, and the OS performs a return process for the DRAM context.

  Patent Document 2 discloses a technique for effectively using a nonvolatile semiconductor memory mounted on a hybrid HDD. The nonvolatile semiconductor memory is divided into a hybrid HDD data area, a read data area, and a write data area. When the host system issues a write command, data is written to the disk medium, and if the write command is registered PINN, it is written to the hybrid HDD data area, and if it is not registered, it is written to the write data area. . When the host system issues a read command registered with PINN, it reads from the hybrid HDD data area, and when it issues a read command not registered with PINN, it reads from the read data area or the disk medium.

  Japanese Patent Application Laid-Open No. 2004-228561 discloses a technique of dividing a nonvolatile semiconductor memory mounted on a hybrid HDD into an area that uses a cache and an area that uses a logical address and stores an actual data as an SSD. Patent Document 4 discloses a technique of using a flash memory mounted on a magnetic disk device in addition to a magnetic disk as a part of a data storage area of the magnetic disk. In this technology, frequently accessed files are stored in a flash memory, so that high-speed access is possible without the waiting time and seek time of the magnetic disk.

U.S. Pat. No. 7,971,081 JP 2009-187604 A JP 2011-90460 A JP-A-6-314177

  When saving data is stored in a general HDD at the time of transition to the S4 state, access to the magnetic disk occurs, so that more time is spent for writing and reading than SSD. If an SSD is provided as an HDD cache as in ISRT, high-speed access to the HDD can be realized. However, a dedicated SSD is prepared only for temporary storage of saved data, so that cost and space are reduced. It's not a good idea.

  In addition, since the SSD and the HDD independently control the power, the capacity of the power source for both needs to be designed based on the sum of the maximum power of each. In this regard, if the non-volatile semiconductor memory mounted on the hybrid HDD can be used instead of the SSD, the hybrid HDD controls access to the magnetic disk and access to the non-volatile semiconductor memory. The capacity of the power source can be greatly reduced.

  However, the primary role of the nonvolatile semiconductor memory mounted on the hybrid HDD is to function as a magnetic disk cache, and therefore it cannot be used as a memory in which the host device can completely control reading and writing. For example, for the hybrid HDD disclosed in Patent Document 2, PINN registered data can be read from and written to the hybrid HDD data area of the nonvolatile semiconductor memory.

  However, since the data area for the hybrid HDD is used as a cache area of the magnetic disk, it is necessary to write data to the magnetic disk at the time of writing, which slows down the writing time. Further, the saved data stored in the hybrid HDD when transitioning to the S4 state is temporary data having no utility value after the return. Therefore, if the hybrid HDD data area is used as a temporary storage location for saved data, the capacity that can be used as the original cache in the entire nonvolatile semiconductor memory is reduced, which is not preferable in terms of utilization.

  In the hybrid HDD of Patent Document 3, a part of the nonvolatile semiconductor memory is used as an SSD, and in the HDD of Patent Document 4, the entire nonvolatile semiconductor memory is used as a part of the magnetic disk. The problem remains. As described above, in the conventional hybrid HDD, since the use form of the nonvolatile semiconductor memory is either the cache or the memory, it is used especially for a temporary storage area of saved data generated when shifting to the sleeping state. It was uneconomical to do.

  SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a method for storing data while effectively using a nonvolatile semiconductor memory that functions as a cache of a hybrid disk drive. It is a further object of the present invention to provide a method for reading / writing temporary data from / to a nonvolatile semiconductor memory functioning as a cache of a hybrid disk drive without affecting the capacity of the cache.

  A further object of the present invention is to provide a method for storing data in a nonvolatile semiconductor memory functioning as a cache of a hybrid disk drive while reducing power consumption. It is a further object of the present invention to provide a method for controlling the power state of a computer using a non-volatile semiconductor memory that functions as a cache of a hybrid disk drive. It is a further object of the present invention to provide a hybrid disk drive, portable computer, and computer program that implements such a method.

  A first aspect of the present invention provides a method for a host device to store data in a hybrid hard disk drive comprising a nonvolatile semiconductor memory and a magnetic disk. The host device sets the hybrid hard disk drive to the cache mode or the memory mode. The hybrid hard disk drive set to the cache mode writes data received from the host device to the nonvolatile semiconductor memory and the magnetic disk. The hybrid hard disk drive set to the memory mode writes the data sent from the host device to an area used in the cache mode of the nonvolatile semiconductor memory without accessing the magnetic disk.

  As a result, the host device can use the non-volatile semiconductor memory as a cache or a memory according to the setting of the operation mode and improve the utilization rate. Cache mode and memory mode use a common storage area of non-volatile semiconductor memory, so it is necessary to allocate a part of the cache to memory or to prepare additional memory for use in memory mode Disappears. Further, when using in the memory mode, power consumption can be reduced because the magnetic disk is not accessed. When a read command is received from the host device while the memory mode is set, data stored in the nonvolatile semiconductor memory can be output without accessing the magnetic disk.

  When a read command is received from the host device while the cache mode is set, data stored in the magnetic disk or the nonvolatile semiconductor memory can be output. When the nonvolatile semiconductor memory includes a read cache area for storing read data and a write cache area for storing write data when the cache mode is set, the nonvolatile semiconductor memory is not configured when the memory mode is set. A memory area in which data received from the host device is written in the volatile semiconductor memory can be defined as a write cache area.

  In this case, it is possible to prevent data in the read cache area from being lost by writing data in the memory mode. The memory area may include all or part of the read cache area. When a part of the read cache area is used as a memory area, it is desirable to secure the space for the memory area by rearranging the positions of the data stored in the memory cache area. If the nonvolatile semiconductor memory is a flash memory, the data written to the nonvolatile semiconductor memory during the memory mode can be erased when setting to the cache mode, immediately after switching to the cache mode. Therefore, it is possible to secure a use area as a cache.

  The second aspect of the present invention provides a method for a computer to control the power state using a hybrid hard disk drive. The hybrid hard disk drive includes a nonvolatile semiconductor memory and a magnetic disk, and can be set to a cache mode or a memory mode. The hybrid hard disk drive writes data created by the computer to the magnetic disk and the nonvolatile semiconductor memory while being set to the cache mode.

  The hybrid hard disk drive does not access the saved data stored in the main memory of the computer in response to the sleep event generated while the memory mode is set, and does not access the magnetic disk to store the cache data in the nonvolatile semiconductor memory. It is possible to shift to the sleeping state after storing in the area used in the mode. Since there is no access to the magnetic disk, it is possible to reduce power consumption and write time.

  In response to a recovery event generated while the hybrid hard disk drive is set to the memory mode, the saved data is transferred from the nonvolatile semiconductor memory to the main memory without accessing the magnetic disk and powered on. The state can be changed. When the sleep state is entered, the system context is saved in the main memory in response to the sleep event, and the first sleeping power supply other than the power supply necessary for holding the main memory is stopped. After a predetermined time following the first sleeping state, the saved data stored in the main memory is saved in the nonvolatile semiconductor memory, and the second power consumption is lower than that in the first sleeping state. It is possible to enter the sleeping state.

  At this time, the operating system can shift to the first sleeping state, and the BIOS can shift to the second sleeping state. When the user performs a return operation to resume use while transitioning to the first sleeping state, the user can return in a short time, and when the user does not perform the return operation after a predetermined time, compare Since there are many cases where there is no plan to use for a long time, it is possible to achieve a balance between convenience and reduction of power consumption by transitioning to the second sleeping state with lower standby power. When transitioning to the power on state, the BIOS may transition from the second sleeping state to the first sleeping state, and the operating system may transition from the first sleeping state to the power on state. it can. When shifting to the power-on state, the memory mode can be switched to the cache mode.

  According to the present invention, it is possible to provide a method for storing data while effectively using a nonvolatile semiconductor memory functioning as a cache of a hybrid disk drive. Furthermore, according to the present invention, it has been possible to provide a method for reading / writing temporary data from / to a nonvolatile semiconductor memory functioning as a cache of a hybrid disk drive without affecting the capacity of the cache.

  Furthermore, according to the present invention, it has been possible to provide a method for storing data in a nonvolatile semiconductor memory functioning as a cache of a hybrid disk drive while reducing power consumption. Furthermore, according to the present invention, a method for controlling the power state of a computer using a nonvolatile semiconductor memory that functions as a cache of a hybrid disk drive can be provided. Furthermore, according to the present invention, it is possible to provide a hybrid disk drive, a portable computer, and a computer program that realize such a method.

2 is a functional block diagram showing a hardware configuration of a notebook PC 10. FIG. It is a figure explaining the transition of the power state of notebook PC10. 2 is a functional block diagram showing a configuration of a hybrid HDD 100. FIG. 2 is a diagram illustrating a configuration of a flash memory 109. FIG. 4 is a diagram for explaining a data structure of a BIOS_ROM 25. It is a figure explaining the logic for the POST selection code 105 to determine the execution path of BIOS. It is a flowchart which shows the procedure in case notebook PC10 changes a power state from S0 state to Sx state. It is a flowchart which shows the procedure in case notebook PC10 changes a power state from S0 state to Sx state. It is a flowchart which shows the procedure in case notebook PC10 changes a power state from Sx state to S0 state. It is a flowchart which shows the procedure in case notebook PC10 changes a power state from Sx state to S0 state.

[Power State]
FIG. 1 is a functional block diagram showing a hardware configuration of a notebook personal computer (notebook PC) 10. Since many hardware configurations are well known, they will be described here within the scope necessary for the present invention. A CPU 11 is connected to the platform controller hub (PCH) 21. A main memory 15 and a video controller 17 are connected to the CPU 11. An LCD 19 is connected to the video controller 17.

  In FIG. 1, the hybrid HDD 100 is typically connected to the SATA, the BIOS_ROM 25 is connected to the SPI, and the embedded controller (EC) 27 and the NVRAM 31 are connected to the LPC. . A keyboard 29 and a power controller 33 are connected to the EC 27. A power button 37, a lid sensor 38, and a DC / DC converter 35 are connected to the power controller 33.

  The notebook PC 10 supports an ACPI (Advanced Configuration and Power Interface) power saving function and plug and play. FIG. 2 is a diagram for explaining the power state transition of the notebook PC 10. ACPI defines four sleeping states (power-saving state), S0 state (power-on state), and S5 state (power-off state) from the S1 state to the S4 state. As for an example of the ACPI sleeping state, the notebook PC 10 defines only the S3 state and the S4 state, but other sleeping states may be defined.

  The S3 state is a so-called suspend state, in which the storage of the main memory 15 is held and the power supply unnecessary for holding the storage of the main memory 15 is stopped. When entering the S3 state, the operating system (OS) saves the system context held by the device whose power is stopped to the main memory 15, and returns it to each device when the power is restored.

  The S4 state is a so-called hibernation state, and is the state in which the time to start is the longest among the sleeping states supported by ACPI and the power consumption is low. When the notebook PC 10 transitions from the S0 state to the S4 state, the OS stores the saved data stored in the main memory 15 in the hybrid HDD 100 and then a device other than the device necessary for starting the power source such as the power controller 33 Turn off the power to the.

  The S5 state is also called so-called soft-off, and basically the range of devices that supply power is the same as the S4 state except that the OS does not save the saved data to the hybrid HDD 100. Hereinafter, the S3 state, the S4 state, and the S5 state are collectively referred to as the Sx state. In contrast to the Sx state, the S0 state is a state in which power is supplied to all devices necessary for the operation of the notebook PC 10 in principle.

  In order to describe the present embodiment, for the S0 state, the HW_S0 state is defined focusing only on the power supply state. The HW_S0 state supplies power to devices in the same range as the S0 state, but the storage state of the main memory 15 and the system context of each device are different from the S0 state. For example, in a transitional state transitioning from the S4 state to the S0 state, the power supply returns to the power-on state, but the state before the saved data stored in the hybrid HDD 100 is transferred to the main memory 15 is Although it can be said to be the HW_S0 state, it cannot be said that it is neither the S0 state nor the S4 state when the data state is included.

  In the present embodiment, the S34 state is defined based on the viewpoint of whether the execution subject on the software when the power state is shifted is the OS or the BIOS. The S34 state is a state in which the OS changes from the S0 state to the S3 state, and then the BIOS automatically changes from the S3 state to the S4 state. Since the OS performs the process of shifting from the S0 state to the Sx state and the process of returning from the Sx state to the S0 state, the power state recognized by the OS and the actual power state are in principle the same. In contrast, in the S34 state, the OS recognizes that the transition destination is the S3 state, but the power supply state and the data state substantially correspond to the S4 state.

  Since the OS includes a code for returning from the S3 state to the S0 state in the system context when the OS makes a transition from the S0 state to the S3 state, the OS cannot directly return from the S34 state to the S0 state. When returning from the S34 state to the S0 state, it is necessary for the OS that has taken over the control right from the BIOS after the BIOS temporarily returns the system from the S34 state to the S3 state to return from the S3 state to the S0 state.

  On the other hand, when transitioning from the S0 state to the S4 state, the OS stores the saved data stored in the main memory 15 in the hybrid HDD 100 after the OS writes the system context in the main memory 15. Since the OS includes a code for returning from the S4 state to the S0 state in the system context, the system can directly return the system from the S4 state to the S0 state. When the state transitions from the S0 state to the S34 state, the time that remains in the S3 state is referred to as S34 time. In the following description, the Sx state includes the S34 state.

  When returning from the Sx state to the S0 state, the BIOS executes POST (Power On Self Test) on the reset device. POST refers to an operation in which a code stored in the BIOS_ROM 25 is set to a parameter in the controller of the PCH 21 or a peripheral device so that the code can be used after the reset signal is supplied to the CPU 11 and before loading of the OS is started. . POST is all processing performed by the BIOS code from when the CPU 11 is reset to when the OS starts loading, or processing other than initialization for basic devices such as the CPU 11 and the main memory 15 from among them. It may be processing excluding.

[Major hardware]
Returning to FIG. 1, the PCH 21 includes an RTC (Real Time Clock) 50 and an RTC memory 51. The RTC 50 and the RTC memory 51 can be supplied with power from the button battery when the power of the AC / DC adapter and the battery pack is stopped and the PCH 21 is not supplied with power from the DC / DC converter 35. The RTC memory 51 is a volatile memory that stores BIOS setup data, time information generated by the RTC, and the like. The RTC memory 51 stores an S34 flag and an S34 time that are referred to by the BIOS when transitioning to the S3 state. The S34 flag and S34 time are set in the RTC memory 51 when the S34 enable is set in the data area 83 (see FIG. 5) of the BIOS_ROM 25 by the BIOS setup code 119 (see FIG. 5). Do.

  The S34 flag is information for instructing the BIOS to perform the process of transitioning to the S34 state when the OS transitions the notebook PC 10 to the S3 state. The S34 time is the time from when the OS changes the system to the S3 state until the BIOS automatically changes to the S34 state. The PCH 21 includes an ACPI register 57 and a register 58 in which power is maintained in the S5 state.

  The ACPI register 57 and the register 58 may be configured by a nonvolatile memory. The ACPI register 57 corresponds to an SLP_TYP register and an SLP_EN register defined in ACPI. The ACPI register 57 is set by the OS when transitioning from the S0 state to the Sx state. A time-up bit is set in the register 58 by the RTC 50 when S34 time has elapsed since the transition to the S3 state.

  The hybrid HDD 100 is a large-capacity storage device that stores an OS, a device driver, an application program, user data, and the like. The hybrid HDD 100 is a boot disk drive in the present embodiment, and stores a boot image that is loaded when the notebook PC 10 is activated. However, the present invention can also be applied to a hybrid HDD other than a boot disk. The present invention can also be applied to an external type hybrid HDD directly connected via a wired or wireless interface such as a USB or a hybrid HDD connected via a network. The configuration of the hybrid HDD 100 will be described in detail with reference to FIG.

  The EC 27 is a microcomputer composed of a CPU, ROM, RAM, and the like, and further includes an A / D input terminal, a D / A output terminal, a timer, and a digital input / output terminal. The EC 27 can execute a program related to management of the operating environment inside the notebook PC 10 independently of the CPU 11. The EC 27 includes a keyboard controller.

  The power controller 33 is a wired logic digital control circuit (ASIC) that controls the DC / DC converter 35 based on an instruction from the EC 27. The DC / DC converter 35 converts a DC voltage supplied from an AC / DC adapter or a battery pack into a plurality of voltages necessary for operating the notebook PC 10, and further supplies power defined according to the power state. Power is supplied to each device based on the partition.

  The power button 37 is arranged on the surface of the casing of the notebook PC 10 so that the user can press it. The lid sensor 38 operates in conjunction with opening and closing of the display housing. When the activation event is generated by pressing the power button 37 or the operation of the lid sensor during the transition to the Sx state, the power controller 33 supplies power to all the devices of the notebook PC 10, and the system To HW_S0 state. The power button 37 and the lid sensor 38 are examples of devices that generate an activation event. Other than that, a fingerprint authentication device or a network card that receives a WOL magic packet can also generate an activation event.

[Configuration and operation mode of hybrid HDD]
FIG. 3 is a functional block diagram showing the configuration of the hybrid HDD 100. The hybrid HDD 100 includes a SATA interface 101, a hard disk controller (HDC) 103, a read / write channel 105, a memory controller 107, a NAND flash memory 109, a DRAM 111, an MPU 113, a ROM 115, a RAM 117, and a NAND flash memory. 119, a servo controller 121 and a driver 123 are included. The hybrid HDD 100 further includes a voice coil motor 125, a magnetic head 127, a magnetic disk 129, and a spindle motor 131.

  The flash memory 109 is an example of a readable / writable non-volatile semiconductor memory, and has a smaller capacity than the magnetic disk 129 but a faster access speed. The configuration of the flash memory 109 will be described with reference to FIG. The SATA interface 101 is connected to the PCH 21. The DRAM 111 functions as a buffer that adjusts the difference in data transfer speed between the system (host device) of the notebook PC 10 and the hybrid HDD 100.

  The MPU 113 executes the firmware stored in the ROM 115 using the RAM 117 as a work area. The MPU 113 interprets a command received from the host device through the HDC 103 and controls the operation of the hybrid HDD 100. The command includes a special command newly introduced in the present embodiment in addition to a command defined in ACPI. The hybrid HDD 100 has two operation modes related to how to use the flash memory 109.

  The first operation mode is a method of using the flash memory 109 as a cache in order to perform an original operation as a hybrid HDD, and the operation mode of the hybrid HDD 100 at that time is referred to as a cache mode. The second operation mode is a method in which the host device uses the flash memory 109 as a memory, and the operation mode of the hybrid HDD 100 at that time is referred to as a memory mode.

  The cache mode is an operation mode of a normal hybrid HDD, but the memory mode is a new operation mode introduced in the present invention. The hybrid HDD 100 operating in the memory mode does not respond to a read or write command specified by the ATA, but only a special command issued by the host device. The host device can send a special command to the hybrid HDD 100 operating in the memory mode to write the write data to the flash memory 109 and read the read data from the flash memory 109. At this time, the MPU 113 performs control so as not to access the magnetic disk 129 in both cases of reading and writing.

  When the hybrid HDD 100 operating in the cache mode receives a read / write command specified by the ATA from the host device, the flash memory 109 is used as a cache, and the read / write to the magnetic disk 129 and the flash memory 109 is performed using a known algorithm. To do. The flash memory 119 stores a mode flag for setting an operation mode and a flag necessary for transition to the S34 state.

  The hybrid HDD 100 can change the operation mode by resetting after setting the mode flag. When reset with the mode flag not set, it operates in cache mode, and when reset with the mode flag set, it operates in memory mode. The hybrid HDD 100 is in the power-on state only when the notebook PC 10 is in the HW_S0 state including the S0 state, and is in the power-off state when in the Sx state.

  The hybrid HDD 100 in the power-on state reduces power consumption by executing power management such as active, idle, standby, or sleep by a command from the host device or a unique algorithm. In standby and sleep, the rotation of the magnetic disk 129 is stopped. The configuration of the hybrid HDD 100 is well known except for data such as firmware stored in the ROM 115 and mode flags set in the flash memory 119.

[Flash memory structure]
FIG. 4 is a diagram for explaining the configuration of the flash memory 109. The configuration in FIG. 4 is an example, and other configurations in accordance with the gist of the present invention can be employed. 4A shows the configuration in the cache mode, and FIGS. 4B and 4C show the configuration in the memory mode. In FIG. 4A, the storage area of the flash memory 109 is divided into a system area 151, a reserve area 153, a read cache area 155, and a write cache area 157.

  In the system area 151, a part of the system code necessary for the operation of the hybrid HDD 100 is stored. The hybrid HDD 100 can process some commands such as an initialization command of the host device without executing the system code stored in the system area 151 at the time of resetting and reading the system data from the magnetic disk 129. .

  The reserved area 153 stores data that is read frequently among data written to the magnetic disk 129. The reserved area 153 is an area for storing data having a particularly high priority among the data stored in the read cache area. The read cache area 155 writes the same data when the host device first reads the data written to the magnetic disk 129, and the next time the host device makes a read request to the same data, This is an area for reading from the read cache area 155.

  The data in the read cache area 155 is replaced with new data by a predetermined algorithm so that the hit rate becomes the highest. The write cache area 157 is an area in which data to be written to the magnetic disk 129 by the host device is written at high speed. Data written by the host device to the write cache area 157 is also written to the magnetic disk 129 by write-back caching or write-through caching.

  In FIG. 4B, a memory area 159 is defined as an area allocated to the write cache area 157. In one example, the memory area 159 is an area for saving the save data stored in the main memory 15 when transitioning to the S34 state. In FIG. 4B, even if the saved data is stored in the memory area 159, the data stored in the read cache area 155 is not affected.

  In FIG. 4C, the memory area 161 is defined as a part of the write cache area 157 and the read cache area 155. Since the read cache area 155 used in the cache mode is reduced to the read cache area 155a, it may be necessary to erase the data stored so far in order to store the saved data. At this time, the memory controller 107 can erase the low-priority data or rearrange the storage location so as not to erase the data in the read cache area 155. It is also possible to erase all data in the read cache area 155 and set the entire write cache area 157 and the entire read cache area 155 in the memory area 161.

[Configuration of BIOS_ROM]
FIG. 5 is a diagram for explaining the data structure of the BIOS_ROM 25. The BIOS code stored in the BIOS_ROM 25 is configured by UEFI firmware as an example. The BIOS_ROM 25 includes a BIOS area 81 that stores the BIOS code and a data area 83 that is used by the BIOS code. The BIOS_ROM 25 employs a boot block method in order to reduce the risk associated with rewriting the BIOS code. The BIOS area 81 is divided into a boot block 85 and a system block 87. The boot block 85 is a write-protected storage area, and the program or code stored here is treated as a CRTM (Core Root of Trust for Measurement) defined in the TPM (Trusted Platform Module) specifications and has a special authority. It is impossible to rewrite without it.

  In the boot block 85, the basic device initialization code 101, the consistency authentication code 103, the POST selection code 105, and the save code 113 are stored as CRTM. The CRTM is configured as a consistent part of the BIOS code and is always executed first when the notebook PC 10 boots. All consistency measurements regarding the platform of the notebook PC 10 are performed by the consistency authentication code 103. The basic device initialization code 101 is stored in the CPU 11, main memory necessary for processing until the BIOS 10 is loaded into the main memory 15 and execution is started when the notebook PC 10 is activated and returns from the Sx state to the S0 state. Detection, inspection, and initialization of the memory 15 and other basic devices are performed to a minimum extent.

  The POST selection code 105 includes the logical value table of FIG. 6, and refers to the registers 57 and 58 of the PCH 21 and the S34 flag of the RTC memory 51, and the basic POST code 107, simple POST code 111, S3 POST code 115 or save. It is determined which one of the codes 113 is executed, and the execution path of the BIOS code is controlled. The save code 113 transfers the save data stored in the main memory 15 in the S3 state to the hybrid HDD 100 when transitioning from the S0 state to the S34 state. The save code 113 can be transferred after the save data stored at discrete addresses in the main memory 15 is formed into continuous data. Therefore, the size of the saved data can be made significantly smaller than the capacity of the main memory 25.

  In order to boot from the S4 state or the S5 state, the basic POST code 107 performs a complete POST process such as detection, inspection, and initialization for all internal devices. The basic POST code 107 acquires a parameter from a peripheral device connected to the PCH 21, selects an optimum parameter in the current system, and sets it in a controller included in the PCH 21.

  In this way, inspecting the internal device and setting the optimal parameter selected based on the information obtained from it in the controller is called initialization, and the parameter set in the past saved in one of the locations is called initialization. Setting to the corresponding controller is called restoration. The restoration can be completed in a shorter time than the initialization because the processing for detecting the internal device, inspecting, and selecting the optimum parameter is omitted.

  The authentication code 109 displays a prompt for setting a BIOS password such as a power-on password, HDD password, and administrator password on the LCD 19, or authenticates the input password or sends it to the hybrid HDD 100 to lock it. Or cancel. When the simple POST code 111 returns from the S34 state to the S0 state, the POST processing such as detection of some devices, inspection, and selection of optimum parameters is omitted, and the booting is performed in a shorter time than the basic POST code 107. To complete. The devices that omit the POST process include devices that spend a lot of time for initialization because of the long response time such as the hybrid HDD 100, USB device, and wireless module, and the OS is initialized from the operation timing. You can select a device that does not cause any problems.

  The optimum parameters set by the basic POST code 107 executed when booting from the S4 state or the S5 state, the device information at that time (hereinafter referred to as parameters), and the like are stored in the data area 83 of the BIOS_ROM 25 or the NVRAM 31. . The simple POST code 111 can shorten the POST time by restoring parameters stored except for the basic device when booting.

  The S3 POST code 115 completes the POST process in a shorter time than the simple POST code 111 when resuming from the S3 state. The parameters set by the basic POST code 107 when booting from the S4 state or S5 state are stored in the main memory 15 in the S0 state. When suspending from the S0 state to the S3 state, the parameters stored in the main memory 15 and the storage of the S3POST code 115 are maintained. The S3 POST code 115 can complete the controller setting in a short time by restoring the parameters stored in the main memory 15.

  The I / O code 117 provides an input / output interface for accessing peripheral devices when the CPU 11 operates in the real mode. The BIOS setup code 119 provides an interface for the user to customize settings for internal devices such as boot drive selection, enable / disable features of each device, enable / disable security, etc. . When a predetermined key is operated in the initial stage of booting, the BIOS setup code 119 is executed, and the BIOS setup screen is displayed on the LCD 19.

  Most of the setup data set by the user is stored in the RTC memory 51 in the PCH 21. The CPU 11 refers to the setup data stored in the RTC memory 51 when executing the basic POST code 107, the simple POST code 111, or the S3 POST code 115. The user can enable or disable the use of the S34 state through the BIOS setup screen.

  Further, when the use of the S34 state is enabled, the S34 time can be set. The set S34 enable flag and S34 time are stored in the data area 83. The environmental utility code 121 controls the temperature and power of the notebook PC 10. Each BIOS code does not need to be composed of independent codes as shown in FIG. 3, but may be configured to control an execution path so that a part of the code is shared and each function is performed. The present invention can also be applied to a BIOS_ROM that does not employ a boot block method, or a BIOS_ROM in which the entire BIOS area is a boot block.

[Transition from S0 state to Sx state]
7 and 8 are flowcharts showing a procedure when the notebook PC 10 changes the power state from the S0 state to the Sx state. In block 301, it is assumed that the notebook PC 10 first transits to the S5 state and the ACPI register 57 is set to the S5 state. Further, it is assumed that some values are set for the S34 flag and S34 time of the register 58 and the RTC memory 51. When the power button 37 is operated to generate a startup event and the notebook PC 10 is powered on, the power controller 33 operates the DC / DC converter 35 to transition the notebook PC 10 to the HW_S0 state.

  Since the mode bit is not set in the flash memory 119, the reset hybrid HDD 100 operates in the cache mode. The PCH 21 that has received the activation event from the EC 27 sends a reset signal to the CPU 11 to perform power-on reset. The reset CPU 11 is configured to execute from the basic device initialization code 101 stored in the boot block 85.

  The CPU 11 that has received the reset signal initializes the internal cache and the register when the voltage is stabilized. The CPU 11 then accesses a predetermined BIOS_ROM 25 address (reset vector) and fetches an instruction. The CPU 11 switches the reset vector that is the access destination to the address of the basic device initialization code 101 in the BIOS_ROM 25.

  The CPU 11 reads out the BIOS code stored in the boot block 85 to the cache, and performs basic device detection, inspection, and initialization necessary for executing the BIOS code such as the main memory 15 and the PCH 21. The basic device initialization code 101 writes parameters set in the controller for initialization to the data area 83 and, if necessary, the NVRAM 31.

  When the main memory 15 becomes available, the basic device initialization code 101 then loads the BIOS code stored in the system block 87 and the parameters of the data area 83 into the main memory 15, and the main memory 15 15 can be used as a shadow RAM. When the execution of the consistency authentication code 103 and the POST selection code 105 stored in the boot block 85 is completed, the CPU 11 accesses the main memory 15 and executes the loaded BIOS code.

  Next, the consistency authentication code 103 verifies the modification of the BIOS code stored in the system block 87. When the verification is completed, the CPU 11 executes the POST selection code 105 in block 303. The POST selection code 105 first refers to the S34 flag in the RTC memory 51. When the POST selection code 105 confirms that the S34 flag is not set, the POST selection code 105 refers to the ACPI register 57. When the POST selection code 105 confirms that the S5 bit is set in the ACPI register 57, the control right is transferred to the basic POST code 107 according to the execution path # 4 in FIG. The POST selection code 105 that is executed each time the CPU 11 is reset in the following procedure determines the execution path in the same procedure with reference to the logical value table of FIG.

  In block 305, at the initial stage when the basic POST code 107 is being executed, when the user presses a predetermined function key on the keyboard 29, the BIOS setup code 119 is called to display the setup screen on the LCD 19. . In relation to the present invention, the user sets the S34 flag and the S34 time for the data area 83 of the BIOS_ROM 25 through the setup screen. In consideration of the convenience of the S3 state and the power saving effect of the S34 state, the user can set the S34 time between 0 hours and a predetermined time. As an example, S34 time is set to 3 hours. The BIOS set-up code 119 stores other input set-up data in the RTC memory 51.

  The user can set a necessary capacity as the memory area 159 or the memory area 161 in the flash memory 109 of the hybrid HDD 100 through the setup screen. The basic POST code 107 stores the set capacity of the memory areas 159 and 161 in the flash memory 119 of the hybrid HDD 100. When the user finishes the BIOS setup code 119, the interrupted basic POST code 107 is executed. The basic POST code 107 detects, inspects, and initializes all remaining devices that are not processed by the basic device initialization code 101.

  When the boot process of the BIOS code is completed, loading of the OS is started in block 307. Programs such as an OS, a device driver, and an application are loaded from the hybrid HDD 100 to the main memory 15 and executed. After that, the OS releases the storage area of the main memory 15 loaded with the BIOS code for a general program except for the code necessary for resuming from the S3 state to the S0 state, and makes a transition to the S0 state. The hybrid HDD 100 is initialized by the basic device initialization code 101 every time the state transitions to the S0 state including the subsequent procedure.

  In block 309, the user performs an operation of shifting the notebook PC 10 from the S0 state to the Sx state by pressing the power button 37, lid closing, operating the Fn key, operating through the OS interface, or executing power management. The relationship between the operation type and the transition destination is predefined. The operation for shifting to the S3 state and the operation for shifting to the S34 state can be the same.

  That is, after executing the BIOS setup code 119 and setting the S34 flag, the user does not need to perform an operation in consideration of the transition to the S34 state. When the user performs an operation for transition to the S3 state, the notebook PC 10 transitions to the S3 state, and automatically transitions to the S34 state when S34 time elapses. When transitioning to the S3 state, the process proceeds to block 311, and when transitioning to the S4 state or S5 state, the process proceeds to block 313 to perform each processing. Further, when the state transits to the S34 state, it is processed in a block 315.

  When the S34 flag of the BIOS_ROM 25 is set to disable, the process of block 311 is performed. When the OS sets the ACPI register 57 to enable the transition to the S3 state, the notebook PC 10 transitions to the S3 state. The SMI handler that traps the setting in the ACPI register checks the S34 flag in the BIOS_ROM 25 and clears the S34 flag and S34 time in the RTC memory 51.

  In block 313, the OS makes a transition by setting the ACPI register 57 so that the S4 state or the S5 state is enabled. Since the SMI handler does not trap the setting in the ACPI register, it does not set the S34 flag for the RTC memory 51. When the S34 flag of the BIOS_ROM 25 is set to enable, the process of the block 315 that transits to the S34 state is performed. The procedure of block 315 will be described with reference to FIG.

  FIG. 8 shows the operation of the notebook PC 10 system and the corresponding operation of the hybrid HDD 100. In block 401, when the PCH 21 that detected the operation event generated in block 309 interrupts the CPU 11, the OS instructs the operating program to perform processing for transitioning to the S3 state, and the OS and as necessary. The system context in which the device driver and BIOS disappear in the S3 state is stored in the main memory 15.

  The system context includes a software context such as a hardware context that is set in a register of each device by the OS or device driver, and control data that the OS or device driver stores in the cache of the CPU 11 and other devices. . The OS writes the system context in the main memory 15 when transitioning from the S0 state to the S3 state or the S4 state.

  In block 451 corresponding to this time point, the hybrid HDD 100 is set to the cache mode, and has transitioned to one of the power states such as active, idle, standby, and sleep. In block 403, the OS sends a SET FEATURES command for setting Power Up in Standby defined by the ATA to the hybrid HDD 100 through the I / O code 117. Receiving the command, the MPU 113 sets power up in standby enable in the flash memory 119. The setting of Power Up in Standby is not released by any of power-on reset, hardware reset, or software reset unless a command to be released thereafter is received.

  When Power Up in Standby is enabled, the hybrid HDD 100 that is powered on next transitions to standby and processes ATA commands such as SET FEATURES, IDENTIFY DEVICE, and IDENTIFY PACKET DEVICE without rotating the magnetic disk 129. can do. Thereafter, when a read / write command for the magnetic disk 129 is received from the host device, the magnetic disk 129 is rotated for processing. In block 405, the OS sends a command for setting the memory mode to the hybrid HDD 100 through the I / O code 117. Receiving the command in block 453, the MPU 113 sets a mode flag in the flash memory 119.

  When the OS receives notification from each program that preparation for transition to the S3 state has been completed, the OS sets the ACPI register 57 so that transition to the S3 state is enabled. When the SMI handler traps the setting in the ACPI register 57 and confirms that the S34 flag is set in the BIOS_ROM 25, the SMI handler sets the S34 flag and the S34 time in the RTC memory 51. When the ACPI register 57 is set to enable, the PCH 21 instructs the EC 27 to stop the power supply other than the power supply necessary for maintaining the storage in the main memory 15, and operates the alarm mechanism (RTC Resume) of the RTC 50. In block 407, the notebook PC 10 is shifted to the S3 state. At this time, in block 455, the power supply of the hybrid HDD 100 is also stopped.

  When the time counted by the RTC 50 in block 409 reaches the S34 time set in the RTC memory 51, the process proceeds to block 411. In block 411, the RTC 50 sets a time-out bit in the register 58, and further instructs the EC 27 to transit to the HW_S0 state. At this time, the hybrid HDD 100 transitions to the power-on state in block 457, but the magnetic disk 129 does not rotate because Power Up in Standby is enabled.

  The CPU 11 reset in block 411 executes CRTM from the first address. The POST selection code 105 selects the execution path # 2 in FIG. 6 with reference to the register 58 and the RTC memory 51, and then releases the time-up bit of the register 58. At block 413, the control right is transferred to the save code 113. The initialized MPU 113 of the hybrid HDD 100 refers to the flash memory 119 in block 461 and confirms the setting of the mode flag, and shifts to the memory mode. In block 415, the save code 113 issues a special initialization command for using the flash memory 409 in memory mode.

  Upon receiving the command, the MPU 113 instructs the memory controller 107 to initialize the flash memory 109 in block 463 and form the memory area 159 or the memory area 161. At this time, the MPU 113 secures a space for the memory area 161 by changing the storage location of the data stored in the read cache area 155 as necessary. In the write cache area 157 or the read cache area 155 corresponding to the memory area 159 or the memory area 161, the data stored so far is erased and new data can be recorded.

  In block 417, the save code 113 configures the discrete addresses of the save data stored in the main memory 15 into continuous addresses and then issues a special write command to hybridize the save data including the system context. Transfer to HDD 100. Depending on the address configuration, the size of the saved data to be transferred can be reduced to less than half the size of the main memory 15. In the data transfer in the memory mode, the save code 113 can be transferred by notifying the size of the save data without specifying the LBA of the magnetic disk 129 as in the case where the OS transfers the write data to the hybrid HDD 100. Since serial transfer is performed from the PCH 21 to the hybrid HDD 100 by using SATA, it is desirable to add a parity check for each appropriate size.

  Receiving the command in block 465, the MPU 113 sets the HDC 103, the memory controller 107, and the like so as to write the saved data received through the SATA interface 101 to the memory area 159 or the memory area 161. At this time, the MPU 113 does not rotate the magnetic disk 129. Further, even if the MPU 113 receives an ATA write command, it does not respond to it. At this time, the save code 113 may cancel the setting of Power Up in Standby by sending a SET FEATURES command. When the MPU 113 finishes writing the saved data to the flash memory 109, the MPU 113 sets a flag indicating that the saved data is written to the flash memory 119.

  When the transfer is completed, the save code 113 stops the power supply other than the power supply of the minimum device necessary for starting the power controller 33 or the like through the EC 27 in block 419. Accordingly, in block 467, the hybrid HDD 100 is powered off. At this point, the notebook PC 10 recognizes that the OS has transitioned to the S3 state, but the actual power state and data state transition to the S34 state, which is the S4 state.

[Transition from Sx state to S0 state]
9 and 10 are flowcharts showing a procedure when the notebook PC 10 changes the power state from the Sx state to the S0 state. When the power button 37 is pressed or the lid sensor 38 is operated in block 503 for the notebook PC 10 that has transitioned to the Sx state in block 501, a start event is generated, and the power controller 33 is switched to DC / DC. The converter 35 is operated and in block 505, the system is shifted to the HW_S0 state.

  The hybrid HDD 100 reset at this time operates in the memory mode because the mode flag is set in the flash memory 119. If the setting of Power Up in Standby is not cancelled, the magnetic disk 129 does not rotate. The MPU 113 initializes the flash memory 109 even if a special command for initialization is received while the flag indicating that the saved data is stored in the flash memory 119 is set. do not do. In block 507, the CPU 11 executes the POST selection code 105.

  The POST selection code 105 confirms the S34 flag of the RTC memory 51 and the bit of the register 57, and selects the execution path of FIG. When it is determined that the POST selection code 105 is a return from the S3 state, the execution path # 3 is selected and the control right is transferred to the S3 POST code 115 in block 509. When the S3 POST code 115 ends the POST process, the notebook PC 10 returns to the state before the transition to the S3 state. When it is determined that the POST selection code 105 is a return from the S4 and S5 states, the execution path # 4 is selected and the basic POST code 107 is executed in the block 511 to return the system to the S0 state.

  The return processing from the S34 state in block 513 will be described with reference to FIG. When the POST selection code 105 selects the execution path # 1 in block 601, the control right is transferred to the simple POST code 111. At this time, in block 651, the hybrid HDD 100 operates in the memory mode. In block 603, the simple POST code 111 issues a special read command for reading saved data to the hybrid HDD 100. Since the saved data is always transferred in a batch, a special read command only requires a read instruction.

  During the memory mode, the MPU 113 does not respond to the ATA read command and outputs the data written in the memory areas 159 and 161 of the flash memory 109. The MPU 113 that has received the command in block 653 transfers the saved data written in the flash memory 109 to the main memory 15. At this time, the MPU 113 controls so that the magnetic disk 129 does not rotate.

  In block 605, the simple POST code 111 issues a special mode switching command for changing the hybrid HDD 100 to the cache mode. Receiving the command in block 655, the MPU 113 clears the mode flag set in the flash memory 119. In block 607, the simple POST code 601 issues a special initialization command for using the flash memory 109 in the cache mode. Receiving the command, the MPU 113 initializes the flash memory 109 so as to be in the state shown in FIG.

  In block 609, the simple POST code 111 sends a DEVICE RESET command specified by the ATA to the hybrid HDD 100. When the MPU 113 receiving the command confirms that the mode flag of the flash memory 119 has been cleared during the reset operation, the MPU 113 shifts to the cache mode in block 659. If the simple POST code 111 cancels the power-up in standby at this point, the magnetic disk 129 does not rotate at all during the transition to the S34 state, and the power consumption can be further reduced.

  At this time, the data state of the notebook PC 10 is the S3 state, but the power state is the HW_S0 state. When the data transfer is completed, the simple POST code 111 transfers the control right to the OS in block 611. The OS refers to the ACPI register 57, recognizes that the power state of the transition source is the S3 state, and transitions to the S0 state, so that the system context cooperates with the device driver and the BIOS as necessary. Is returned to each reset device and transitions to the S0 state. The return from the S34 state to the S0 state can be completed in a short time because the saved data is read from the flash memory 109 without accessing the magnetic disk 129 and the return processing is performed with the simple POST code 111.

  Although the present invention has been described with the specific embodiments shown in the drawings, the present invention is not limited to the embodiments shown in the drawings, and is known so far as long as the effects of the present invention are achieved. It goes without saying that any configuration can be adopted.

100 Hybrid HDD
109 Flash memory 155 Read cache area 157 Write cache area 159, 161 Memory area

Claims (8)

Hybrid hard disk drive comprising a non-volatile semiconductor memory that can be set to a cache mode or a memory mode and includes a magnetic disk and a common storage area that can be used in the cache mode and the memory mode A computer that has access to the drive to control the power state,
Writing the data created by the computer to the magnetic disk and the common storage area while the cache mode is set;
Setting the hybrid hard disk drive to the memory mode in response to a sleep event ;
Storing the saved data stored in the main memory of the computer in the common storage area without accessing the magnetic disk and then entering the sleeping state.   In response to a return event generated while the memory mode is set, the save data is transferred from the common storage area to the main memory without accessing the magnetic disk, and is in a power-on state. The method of claim 1 including the step of transitioning.   The method of claim 2, wherein the step of transitioning to the power on state comprises switching from the memory mode to the cache mode. Hybrid hard disk drive comprising a non-volatile semiconductor memory that can be set to a cache mode or a memory mode and includes a magnetic disk and a common storage area that can be used in the cache mode and the memory mode A computer that has access to the drive to control the power state,
Writing the data created by the computer to the magnetic disk and the common storage area while the cache mode is set;
The first sleeping state in which the system context is saved in the main memory after the memory mode is set in response to the sleep event, and the power supply other than the power supply necessary for holding the main memory is stopped. The steps to transition to
After a predetermined time following the first sleeping state, the saved data stored in the main memory is saved in the common storage area without accessing the magnetic disk and is consumed from the first sleeping state. Transitioning to a low power second sleeping state. The method according to claim 4 , wherein an operating system causes the computer to perform a function of transitioning to the first sleeping state, and a BIOS causes the computer to perform a function of transitioning to the second sleeping state. The BIOS causing the computer to perform a function of transitioning from the second sleeping state to the first sleeping state;
The method according to claim 5 , further comprising the step of causing the operating system to perform a function of transitioning from the first sleeping state to a power-on state. A computer capable of transitioning to a sleeping state,
Main memory,
Hybrid hard disk drive comprising a non-volatile semiconductor memory that can be set to a cache mode or a memory mode and includes a magnetic disk and a common storage area that can be used in the cache mode and the memory mode Drive,
A means for generating a sleep event;
Setting means for setting the hybrid hard disk drive to the cache mode or the memory mode;
After the cache mode is set, data is written to the magnetic disk and the common storage area, and the save data stored in the main memory after the memory mode is set in response to the sleep event is stored in the magnetic mode. A computer having control means for storing in the common storage area without accessing a disk and then shifting to the sleeping state; Hybrid hard disk drive comprising a non-volatile semiconductor memory that can be set to a cache mode or a memory mode and includes a magnetic disk and a common storage area that can be used in the cache mode and the memory mode On a computer that has access to the drive,
The ability to generate sleep events;
A function of setting the hybrid hard disk drive to the cache mode or the memory mode;
A function of writing data to the magnetic disk and the common storage area after setting the cache mode;
A function of storing saved data stored in a main memory after setting the memory mode in response to the sleep event in the common storage area without accessing the magnetic disk and then entering a sleeping state; A computer program for realizing

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