JP5913770B2 - Method for controlling the power state of a storage device comprising a rotating disk and portable computer - Google Patents

Description

  The present invention relates to a technique for timely updating data of a portable computer equipped with a storage device having a rotating disk, and further to prevent damage to the storage device, reduce the risk of data loss, or ensure data update. The present invention relates to technology for improving the performance.

  The computer implements an application program (AOAC application) that requires timely data updates, such as social network service (SNS), e-mail, or news. Intel (registered trademark) provides a usage mode called AOAC (Always On Always connected) for always connecting to a network and communicating on demand for an AOAC application.

  When implementing AOAC, it is necessary to put the computer in a power-on state. In a notebook personal computer (notebook PC) to which a desktop PC and an AC / DC adapter are connected, in which power consumption is not a big problem, AOAC can be realized by always connecting to a network. However, in order to realize AOAC on a notebook PC operating in a mobile environment, it is necessary to consider the battery life and the time that can be connected to the network while moving.

  Intel (registered trademark) provides Intel (registered trademark) Smart Connect Technology (ISCT) in order to realize AOAC in a notebook PC while preventing battery consumption. Notebook PCs with ISCT are periodically waked to a power-on state when in a sleep state. Alternatively, when a notebook PC with ISCT is moved to various places in the sleep state, the WiFi card detects a previously connected access point (AP) and automatically wakes the notebook PC. After that, the notebook PC that has established a connection to the network virtually realizes AOAC by performing AOAC processing in which the AOAC application updates data and then transitioning to the sleep state again.

  AOAC processing requires execution of an AOAC application and storage of update data. Therefore, in a notebook PC equipped with a hard disk drive (HDD) as a large-capacity storage device, the magnetic disk is spun up whenever a wake from the sleep state occurs due to AOAC processing. The wake for AOAC processing occurs even when the notebook PC is moving with the user, but if the notebook PC is spun up with vibration, shock, or shaking (collectively vibration), the HDD is damaged. The risk of doing it increases.

  Patent Document 1 discloses a storage device that switches an operation mode when vibration or impact is detected. This storage device has a battery installed therein, and maintains power sources such as a cache memory, an impact sensor, and a controller when the main power supply is stopped. In the case of the smallest vibration state, the write back method, which is a cache method during normal operation, is set. In the next largest vibration state, the write-through method is set. In the case of a larger vibration state, the write back method is set. When the maximum vibration is detected, the power supply of the storage device is stopped and the data is saved to the external auxiliary storage device. The saved data is then returned to the storage device.

JP 2007-200196 A

  Although the unit price per bit is lower than that of a flash SSD, the HDD has a rotation mechanism and has low resistance to vibration and high power consumption. Since a system incorporating ISCT automatically wakes up when the AP is detected without knowing the user, there is a high possibility that the HDD will be damaged. Although it is possible to prevent damage to the HDD by stopping the wake or detecting access to the HDD when vibration is detected, a situation occurs in which AOAC processing cannot be performed in a timely manner.

  In particular, if the time during which an AP can be accessed while moving in an airport or a station is short, the data cannot be updated at all if the access to the HDD is stopped until the vibration stops. A technique is known in which a nonvolatile semiconductor memory (HDD cache) that functions as a cache is provided for the HDD to shorten the access time to the HDD. The HDD cache can operate by selecting one of two cache modes of a write-through method and a write-back method.

  In the write-through method, data is written to both the HDD cache and the magnetic disk at the time of writing. Although the writing time cannot be shortened because the system recognizes that writing has been completed when it is written to the magnetic disk, it can be read in a short time as long as the data is held in the HDD cache. In the write back method, when the data is written to the HDD cache at the time of writing, the system recognizes that the writing is completed, so that the writing process can be completed in a short time. Writing from the HDD cache to the magnetic disk is performed using the idle time of the system when the HDD cache is low.

  Data synchronization between the HDD cache and the magnetic disk is managed by a program loaded into the main memory and executed. If the system hangs up or the power supply becomes unstable when transferring write data from the HDD cache to the magnetic disk (flash), there is an increased risk of loss of data before flash because of loss of synchronization, The HDD cache managed by the system is set to the write-through method. Therefore, even if an HDD cache is provided, access to the magnetic disk occurs during AOAC processing. The present invention provides a method for solving problems derived from such AOAC processing.

  Accordingly, an object of the present invention is to provide a method for preventing damage to a storage device including a rotary disk mounted on a portable computer. A further object of the present invention is to provide a method for reducing the risk of data loss during synchronization while preventing damage to the storage device. A further object of the present invention is to provide a method for reducing power consumption while preventing damage to a storage device. It is a further object of the present invention to provide a method for improving the reliability of AOAC processing while preventing damage to a storage device. A further object of the present invention is to provide a computer program and a portable computer for realizing such a method.

  The present invention controls a power state of a portable computer equipped with a storage device having a rotating disk and a nonvolatile semiconductor memory functioning as a cache of the storage device by setting to a write-back method or a write-through method. Regarding the method. In a first aspect, resume processing is initiated in response to a first system event generated during the sleep state. In response to determining that the acceleration generated in the portable computer during the resume process is greater than or equal to a predetermined value, the write-back method is set. In response to the second system event generated after the transition to the power-on state, the transition from the power-on state to the sleep state occurs.

  The risk of storage damage that occurs in the power-on state is determined by the magnitude of acceleration measured during the resume process. The cache mode is controlled according to the risk of damage. When the acceleration is high, the write-back method is set to reduce the spin-up frequency, thereby reducing the risk of damage to the storage device. In addition, since the frequency of spin-up is reduced by setting the write-back method, power consumption can be reduced.

  In response to determining that the acceleration is equal to or less than a predetermined value during the resume process, the write-through method can be set. If the acceleration is small, the risk of damage to the storage device does not increase even if the write-through method is set. In addition, if the write-through method is set, there is a risk of data loss due to system hang-up or power failure when synchronizing the data stored in the semiconductor memory with the data stored in the disk by flashing. Can be eliminated.

  The first system event may be generated when the portable computer detects a predetermined wireless access point. Or you may make it the time measuring apparatus of a portable computer generate | occur | produce at a fixed time interval. In the power-on state, the portable computer can execute a predetermined program to acquire and store update data from a wirelessly connected network. At that time, by selecting the cache mode, it can be resumed regardless of the presence or absence of vibration, so that it can be reliably updated even when the time available for connection to the wireless network is short. Furthermore, if the write-back method is set, writing update data can be completed in a short time, so that the reliability of timely update can be improved.

  The storage device includes a rotation suppression mechanism that stops the rotation of the disk when power is turned on, and the rotation suppression mechanism can be enabled before generating the first system event. As a result, since the spin-up is not performed at the same time as the power is turned on, the spin-up time in an unprotected state before the protection system functions in the power-on state can be shortened. In this case, the resume time can be prevented from being delayed by reading data necessary for initialization of the storage device stored in the disk during the resume process from the nonvolatile memory.

  When a wake event is generated in response to a user operation, the write-through method can be set. Since the user wake intended for use by the user can be assumed to be performed with the portable computer stationary, the storage device and the nonvolatile semiconductor memory can be used while reducing the risk of data loss during synchronization. . Monitoring the available capacity of the nonvolatile semiconductor memory in the power-on state, and writing the data stored in the nonvolatile semiconductor memory to the disk when it is determined that the available capacity is less than a prescribed value, to ensure the prescribed available capacity it can.

  As a result, since the update data can be written only in the nonvolatile semiconductor memory by setting the write-back method, the risk of damage to the storage device can be further reduced by reducing the spin-up frequency. The remaining capacity of the battery that supplies power to the portable computer can be monitored, and the write-back method can be set when the remaining capacity is greater than a predetermined value. As a result, it is possible to reduce the risk of data loss at the time of synchronization that occurs when the write-back method is set when the power supply is unstable.

  In the second aspect, the resume process is started in response to the wake event generated during the sleep state. Determine the type of wake event during the resume process. In response to determining that the wake event is a system event, the write back method is set. Then, in response to a system event generated after shifting to the power-on state, the power-on state shifts to the sleep state.

  System events are often generated when a portable computer is being carried and vibrating. In this case, the risk of damage to the storage device can be reduced by setting the write back method. The magnitude of acceleration generated in the portable computer during the resume process can be determined, and the setting of the write-back method can be executed when the acceleration is equal to or less than a predetermined value. In response to determining that the wake event is a user event, the write-through method can be set. Only when it is determined that the remaining capacity of the battery that supplies power to the portable computer is greater than a predetermined value, the write-back method can be set.

  According to the present invention, a method for preventing damage to a storage device including a rotary disk mounted on a portable computer can be provided. Furthermore, the present invention can provide a method for reducing the risk of data loss during synchronization while preventing damage to the storage device. Furthermore, according to the present invention, a method for reducing power consumption while preventing damage to a storage device can be provided. Furthermore, according to the present invention, it is possible to provide a method for improving the reliability of the AOAC process while preventing damage to the storage device. Furthermore, according to the present invention, it is possible to provide a computer program and a portable computer for realizing such a method.

It is a functional block diagram for demonstrating an example of the hardware constitutions of notebook PC. It is a figure explaining an example of a software configuration of notebook PC. It is a time chart which shows the execution procedure of a 1st AOAC process. It is a flowchart which shows the execution procedure of a 1st AOAC process. It is a flowchart which shows the execution procedure of a 1st AOAC process. It is a flowchart which shows the execution procedure of a 1st AOAC process. It is a flowchart which shows the execution procedure of a 1st AOAC process. It is a time chart which shows the execution procedure of a 2nd AOAC process. It is a flowchart which shows the execution procedure of a 2nd AOAC process. It is a flowchart which shows the execution procedure of a 2nd AOAC process. It is a flowchart which shows the execution procedure of a 2nd AOAC process. It is a flowchart which shows the execution procedure of a 2nd AOAC process.

[Note PC configuration and power state]
FIG. 1 is a functional block diagram for explaining an example of the hardware configuration of the notebook PC 10, and FIG. 2 is a diagram for explaining an example of a program stored in the magnetic disk 24. Since many hardware configurations are well known, they will be described here within the scope necessary for understanding the present invention. First, the power state of the notebook PC 10 will be described. The notebook PC 10 corresponds to a power saving function of ACPI (Advanced Configuration and Power Interface). ACPI defines four sleeping states (sleep state), S0 state (power-on state), and S5 state (power-off state or soft-off state) from the S1 state to the S4 state.

  Of the ACPI sleeping states, the notebook PC 10 defines only the S3 state and the S4 state as an example, but other sleeping states may be defined. Further, the S5 state may be included in the S4 state without being defined independently. When in the sleep state, the CPU 11 and HDD 23 are always powered off. Accordingly, when waking up from the sleep state, the HDD 23 is reset. In the S3 state (suspended state), power to devices other than those necessary for storing and storing the main memory 13 and turning on the power of the notebook PC 10 is stopped. When entering the suspend state, the OS saves the system context stored in the cache and registers of the CPU 11 and other devices whose power is stopped to the main memory 13 and returns it to the power-on state. Restore to each device.

  The S4 state (hibernation state) is a power state having the longest latency and the low power consumption among the sleeping states supported by ACPI. When the notebook PC 10 transitions from the power-on state to the hibernation state, the OS stores the hibernation data stored in the main memory 13 in the hibernation area of the HDD 23 or the flash memory 19, and then the power controller 33 and the like. Stop power to devices other than those required to power on.

  The S5 state is also called so-called soft-off, and basically the range of devices that supply power is the same as the S4 state except that the OS does not store hibernation data in the HDD 23 or the like. The S4 state in the present invention includes a state in which the system firmware automatically transitions to the S4 state when a predetermined time has elapsed since the OS transitioned to the S3 state. In this case, the OS recognizes that the system has transitioned to the S3 state, but the actual power state is the S4 state. Hereinafter, the sleep state and the power-off state are collectively referred to as the Sx state.

  A CPU 11, flash memory 19, HDD 23, WiFi card 26, firmware ROM 25, and embedded controller (EC) 27 are connected to a platform control hub (PCH) 17 configured as a chip set. The chip set can be composed of ICH and MCH, or can be composed of IOH and ICH, instead of PCH17. A main memory 13 and an LCD 15 are connected to the CPU 11. The PCH 17 has various standard interface functions. In FIG. 1, the flash memory 19 is typically connected to the SATA controller, the HDD 23 is connected to the SATA controller, the WiFi card 26 is connected to the PCI, and the SPI is connected to the SPI. A firmware ROM 25 is connected, and an EC 27 is connected to the LPC.

  The flash memory 19 includes a system-on-chip (SOC) including an mSATA interface, and in one example, a cache area used as a cache of the HDD 23 and hibernation data for storing hibernation data when transitioning to the S4 state. It is separated by two partitions in the area. When the flash memory 19 does not include a hibernation area, the HDD 23 can store hibernation data. In normal use of the flash memory 19, the cache area is set to the write-through method, and the hibernation area is set to the write-back method.

  As shown in FIG. 2, the HDD 23 has an APS application 80, an AOAC application 81 such as a mailer or SNS application, a power management (PM) utility 83, an OS 85, a device driver 87, and a magnetic disk 24 for storing user data. Including. The HDD 23 stores a boot file that is loaded when the notebook PC 10 resumes with a boot disk drive. The HDD 23 includes a flash memory for setting a power up in standby (PUIS).

  The firmware ROM 25 is a non-volatile semiconductor memory in which stored contents can be electrically rewritten, and includes a code area and a data area. The code area stores UEFI (Unified Extensible Firmware Interface) firmware (hereinafter referred to as UEFI firmware) composed of a plurality of code groups. The UEFI firmware is a new specification system firmware used in place of or in addition to the BIOS established by the UEFI Firmware Forum. The UEFI firmware is executed first whenever the CPU 11 is powered on and reset when the notebook PC 10 resumes from the power off state or the sleep state to the power on state.

  The UEFI firmware executes a so-called POST (Power On Self Test) that checks whether there is any alteration to its code, resumes password authentication, or initializes the device when resuming. The UEFI firmware can change the contents of POST according to the power state of the transition source when the system resumes. For example, when resuming from the S5 state, a complete POST is performed in which parameters are obtained from all devices and set in the interface.

  Also, when resuming from the S4 state, the POST time is shortened by entrusting the POST of some devices to the OS or restoring previously set parameters to the device. When resuming from the S3 state, a simpler POST is executed so that it can be completed in a short time. The data area stores HDD data used by the UEFI firmware when resuming. The HDD data is data that is conventionally read from the magnetic disk 24 by the UEFI firmware in order to POST the HDD 23 when resuming from the sleep state to the power-on state. The UEFI firmware requires HDD data during or after the resume after the POST of the HDD 23 to make the system use the HDD 23.

  The UEFI firmware can read HDD data from the data area of the firmware ROM 25 when PUIS is set to enable. The area where the HDD data is stored by the UEFI firmware need not be limited to the firmware ROM 25, but other nonvolatile memory such as the flash memory 19 that the UEFI firmware can access during POST or the flash memory stored in the HDD 23. It can also be a volatile memory.

  In the HDD 23 that is powered on at the time of resuming, the internal CPU powers on and resets and the spindle motor operates to rotate the magnetic disk 24. This operation of the HDD 23 is called spin-up. The HDD 23 in the power-on state executes a power management operation such as active, idle, standby, or sleep by a command from the system or a unique algorithm to reduce power consumption. In standby and sleep, the spindle motor stops and the magnetic disk 24 stops rotating. This operation of the HDD 23 is called spin down. Since the head is retracted to the ramp mechanism during the spin down, the impact resistance of the HDD 23 is improved.

  ATA defines an operation mode called PUIS as a method for maintaining the spin-down in the HDD 23 that is turned on. The magnetic disk 24 stores specific data (HDD data) for identifying the HDD 23, such as rated capacity, manufacturer name, model, partition information, information indicating that the disk is rotating, and whether or not PUIS is supported. The UEFI firmware needs to read HDD data from the magnetic disk 24 in order to complete POST of the HDD 23. Also, the HDD 23 needs to be spun up and self-inspected before sending a ready signal to the UEFI firmware during POST. The UEFI firmware can read HDD data from the magnetic disk 24 after receiving a ready signal from the HDD 23 that has been spun up.

  If an impact is applied to the notebook PC 10 while the HDD 23 is spinning up, the HDD 23 may be damaged. The APS application 80 processes the acceleration detected by the acceleration sensor 29 when the notebook PC 10 is in a power-on state with a predetermined algorithm, and moves the head back to the ramp mechanism when a possibility of a large impact is predicted. The system (S0_APS) is configured. An example of an impact handling system is disclosed in Japanese Patent Application Laid-Open No. 2004-146036. S0_APS prevents the operation of the HDD 23 from being stopped more than necessary by retracting the head only when a dangerous impact is predicted.

  In order for the system to receive the ready signal and recognize the HDD 23, it is necessary to spin up the HDD 23 and read the HDD data when resuming. However, since S0_APS does not function before the OS is executed, there is an increased risk of damage to the HDD 23 from when the power is turned on until S0_APS functions, especially when resuming during movement. When the UEFI firmware or the OS sets PUIS to be enabled, the HDD 23 maintains the spin down when the power is turned on or reset. The PUIS set to enabled does not return to disabled unless the HDD 23 subsequently receives a command to set to disabled.

  If PUIS is set to enable, spin down can be maintained to prevent damage due to impact when power is supplied to the HDD 23 by waking up. However, in order to terminate POST, the UEFI firmware needs to read the HDD data after sending a command to the HDD 23 to spin up and receiving a ready signal. This procedure results in an increase in POST time. Further, when the user resumes to use the system, it is necessary to finish POST in as short a time as possible. In this embodiment, PUIS is enabled at the timing of each resume, and HDD data stored in advance in the firmware ROM 25 instead of the magnetic disk 24 is read to prevent damage to the HDD before S0_APS functions. Both resume time can be shortened.

  The PCH 17 includes an RTC (Real Time Clock) 50 and an RTC memory 51. The RTC 50 and the RTC memory 51 can receive power from the button battery when the power of the AC / DC adapter 39 and the battery pack 41 is stopped and power is not supplied from the DC / DC converter 37 to the PCH 17. The RTC memory 51 is a volatile memory that stores setup data set in the device by the UEFI firmware, time information generated by the RTC 50, and the like.

  The user stores in the RTC memory 51 through the UEFI firmware setup code various settings information relating to the setting for enabling AOAC processing and other AOAC processing. When the system in the sleep state automatically wakes up for AOAC processing, the AOAC application 81 updates data and returns to the sleep state after transitioning to the S0 state. The power state woken for the AOAC process is the S0 state, but focusing on the fact that it is a special S0 state that automatically transitions to the sleep state when the AOAC process ends, this is referred to as the AOAC_S0 state.

  The AOAC process corresponds to an operation in which the AOAC application 81 connects to the network and updates data in the AOAC_S0 state. In the AOAC_S0 state, when the user does not access the system with the mouse or the keyboard, the system automatically shifts to the sleep state when the AOAC process is completed. When the user presses the power button 35 or operates the lid sensor 36 in the sleep state, the power is turned on to shift to the power-on state, which is called user wake.・ I will call it an event.

  User events are generated when a user uses the system. Note that the user event includes an event generated when the user operates an input device such as a mouse or a keyboard in the power-on state. The case where the system does the same thing is called a system wake and a system event. The system wake is performed for the system to perform power management and AOAC processing.

  A system wake for AOAC processing is called an AOAC wake, and a system event generated at that time is called an AOAC event. System events can be generated by either the WiFi card 26 or the RTC 50. An AOAC event can be generated when the WiFi card 26 detects an SSID transmitted by a predetermined AP. Further, the RTC 50 can be generated at a predetermined time or a predetermined cycle. Note that the terms user event and system event also apply to a sleep event for transitioning the system from a power-on state to a sleep state.

  The PCH 17 includes registers 53, 55, 57, and 59 whose memory is maintained even during the sleep state. The register 53 corresponds to an SLP_TYP register and an SLP_EN register defined in ACPI. The register 53 is set by the OS when transitioning from the S0 state to the Sx state. The OS sets the power state of the transition destination in the register 53 when the system is ready to transition to the Sx state. When the transition state power state is set in the register 53, the PCH 17 causes the system to transition to the set power state through the EC 27.

  The UEFI firmware refers to the register 53 when resuming from the Sx state, and determines the POST execution path according to the power state of the transition source. In the POST execution path selected by the UEFI firmware, the POST time is maximized when the transition source power state is the S5 state, and is minimized when the UEFI firmware is in the S3 state. A wake bit is set in the register 55 when the RTC 50 or the WiFi card 26 generates an AOAC event.

  The PCH 17 supplies power to each device through the EC 27 when the wake bit is set in the register 57 in the sleep state. An acceleration flag is set in the register 57 by the EC 27. The register 59 is set with an AOAC flag when an AOAC event is generated. The UEFI firmware sets the AOAC flag when resuming with an AOAC event, and clears the AOAC flag when resuming with a user event or when a user event is generated in the AOAC_S0 state.

  The PCH 17 includes a cache controller 53 for causing the flash memory 19 to function as a cache of the HDD 23. The cache controller 53 can set the cache mode for the HDD 23 of the flash memory 19 to either the write-back method or the write-through method. The UEFI firmware can set the cache mode when resuming.

  An acceleration sensor 29 and a power controller 33 are connected to the EC 27. The EC 27 is a microcomputer composed of a CPU, ROM, RAM, and the like. The EC 27 can execute a program related to management of the operating environment inside the notebook PC 10 independently of the CPU 11. The EC 27 controls the operation of the DC / DC converter 37 through the power controller 33. The EC 27 periodically communicates with the battery pack 41 to acquire battery remaining capacity data.

  The acceleration sensor 29 outputs the acceleration generated in the notebook PC 10 to the EC 27. S0_APS configured by the acceleration sensor 29 and the APS application 80 does not function until the OS is executed at the time of resume. However, when power is supplied to the EC 27 and the acceleration sensor 29, the EC 27 can detect the magnitude of acceleration. In the present embodiment, this acceleration is used for selecting the cache mode.

  This mechanism is called S3_APS to distinguish it from S0_APS. Unlike S0_APS, S3_APS cannot adopt a complicated algorithm, and may be spun down more than necessary when used for spin-up control of the HDD 23. However, S3_APS functions without difficulty when used for selecting a cache mode. The UEFI firmware sets the register 61 to enable / disable S3_APS. When S3_APS is enabled, the EC 27 sets an acceleration flag in the register 57 when the acceleration acquired from the acceleration sensor 29 during resume exceeds a predetermined value. The EC 27 resets the acceleration flag when the acceleration falls below the threshold for a predetermined time.

  The power controller 33 is connected with control circuits for a power button 35, a lid sensor 36 and a DC / DC converter 37. The power controller 33 is a wired logic digital control circuit (ASIC) that controls the DC / DC converter 37 based on an instruction from the EC 27. The power controller 33 includes a register 63 for setting a wake bit.

  The power controller 33 maintains power even in the Sx state in order to resume the notebook PC 10. The wake bit of the register 63 is set by the logic circuit of the power controller 33 when the power button 35 is pressed or the lid sensor 36 is operated. The signal of the power button 35 or the lid sensor 36 corresponds to a user event.

  The AC / DC adapter 39 and the battery pack 41 are power sources for the notebook PC 10. The DC / DC converter 37 converts the DC voltage supplied from the AC / DC adapter 39 or the battery pack 41 into a plurality of voltages necessary for operating the notebook PC 10, and is further defined according to the power state. Power is supplied to each device based on the power supply category.

[Basic principles of AOAC processing]
This embodiment has the following features in order to solve various problems that occur in AOAC processing. Regarding the relationship between the type of wake and the possibility of vibration, it is assumed that the possibility of vibration is low because the user wake is in the state used by the user, and the AOAC wake occurs unexpectedly away from the user's intended use Assume that the possibility of vibration is high.

  In order to prevent damage to the HDD due to spin-up during POST, it is desirable to shorten the spin-up time as long as possible without being protected by S0_APS from when the power is turned on until S0_APS functions. Therefore, PUIS is set to enable so that it does not spin up at the same time as the power is turned on. Also, HDD data is stored in advance in the firmware ROM 25 so that the POST time is not delayed by enabling PUIS.

  The shortening of the POST time results in an increase in the reliability of the AOAC process and a reduction in power consumption even if the connection time with the AP is short. In order to reconcile the reduction of the risk of HDD damage due to spin-up in the AOAC_S0 state and the reduction of the risk of data loss during synchronization when the write-back method is adopted, in addition to SO_APS, the following two Adopt one of the methods. In the first method, the presence or absence of vibration is inspected during POST. If there is no vibration, the flash memory 19 is set to the write-through method, and if there is vibration, the write-back method is set. When there is no vibration, priority is given to reducing the risk of data loss during synchronization by setting the write-through method. If there is vibration, priority is given to reducing the risk of HDD damage by reducing the spin-up frequency by setting the write-back method.

  When the write-back method is set, even if S0_APS functions and does not spin up, as long as there is free space in the flash memory 19, update data can be written there for AOAC processing. In order to reduce the spin-up frequency when the write-back method is set, it is necessary to secure sufficient free space in the flash memory 19 before the transition to the AOAC_S0 state. In this embodiment, a flash timing is provided between the AOAC_S0 states to reduce the spin-up frequency.

  In the first method, when it is determined that there is no vibration during POST and the write-through method is set, if vibration occurs during the AOAC_S0 state, S0_APS functions and the AOAC processing is stagnated. In the second method, as long as the AOAC wake continues continuously, the write back method is set until the user wake is generated. If the write back method is set, the writing time can be shortened. Further, since AOAC processing can be performed even if S0_APS functions as long as there is free space in the flash memory 19, the write time is shortened to improve the reliability of AOAC processing and reduce power consumption. Can do. The second method is particularly effective when continuous vibration is expected and the time to connect to the AP is short.

[First method]
FIG. 3 is a time chart for explaining a first method of AOAC processing, and FIGS. 4 to 7 are flowcharts showing procedures corresponding thereto. Note that the times t0 to t7 described in the flowchart are added for the convenience of description of the flowchart, and the timing of the procedure and the time described in the figure may not match. In block 101 of FIG. 4, the system has transitioned to the S0 state. PUIS is set to disabled, the cache mode of the cache controller 53 is set to the write-through method, and S3_APS is set to disabled. Since the CPU 11 executes the OS 85 and the APS application 80, the S0_APS functions effectively.

  In block 103, a sleep event is generated that transitions to the S3 state at time t0. The sleep event can be a system event generated when the OS 85 measures a predetermined idle time or a user event generated by pressing the power button 35, operating the lid sensor 36, or operating the GUI. . In block 105, the OS 85 sets S3_APS enable to the register 61 via the UEFI firmware, and in block 107 sets the HDD 23 to PUIS enable.

  In block 109, when the OS 85 saves the system context in the main memory 13 and receives notification of completion of preparation for transition to the S3 state from each application, the OS 85 sets the S3 bit in the register 53. The PCH 17 in which the register 53 is set instructs the EC 27 to stop the power supply of devices that are not required to hold the main memory 13 and devices that are not required to generate the AOAC event. It should be noted that power is supplied to some functions of the PCH 17 necessary for power-on and the power controller 33 during the S3 state. When the system transitions to the S3 state, the operation of the APS application 80 stops, so the function of S0_APS stops.

  Thereafter, a scenario is assumed in which the user carries the notebook PC 10 in a bag. In block 111, a wake event for resuming from the sleep state is generated (time t1, t3, t5, t7). The wake event includes a user event intended for use by the user and a system event (AOAC event) for the system to perform AOAC processing. In block 201 of FIG. 5, power is supplied to a device operating in the S0 state at any wake event.

  The EC 27 monitors the output of the acceleration sensor 29 to realize S3_APS, and sets an acceleration flag in the register 57 and notifies the PCH 17 when the output exceeds a predetermined threshold. The EC 27 cancels the acceleration flag when the predetermined time acceleration falls below the threshold value. The HDD 23 to which power is supplied starts the reset operation by the internal CPU, but since the PUIS is enabled, the spin down is maintained until a spin-up command is received immediately after the power is turned on. .

  The UEFI firmware initializes basic devices necessary for starting the execution of POST, such as the CPU 11 and the main memory 13, and further verifies the consistency of the platform. In block 203, the UEFI firmware inspects interfaces of devices such as the PCH 17, the flash memory 19, and the HDD 23, and then sets and initializes parameters stored in the RTC memory 51 therein. Thereafter, the UEFI firmware waits for a ready signal from each device including the HDD 23.

  In block 205, the UEFI firmware reads HDD data from the data area of the firmware ROM 25. The UEFI firmware performs POST using the HDD data read from the firmware ROM 25 and proceeds to block 207. In block 207, the UEFI firmware refers to the PCH 17 register 55 and the power controller 33 register 63 to check the type of wake event. When the AOAC processing is enabled in the RTC memory 51 and the wake bit is set in the register 55, it is determined that the AOAC wake is detected, and the process proceeds to block 209 (time t1, t3, t5). When the wake bit is set in the register 63, it is determined that the user wakes up and the process proceeds to block 401 in FIG. 7 (time t7).

  In block 209, the UEFI firmware checks whether vibration has occurred and an acceleration flag is set in the register 57. When the UEFI firmware determines in block 211 that the acceleration flag is set, the process proceeds to block 213 (time t1, t5), and when it is determined that the acceleration flag is not set, the process proceeds to block 231 (time t3). The UEFI firmware queries the EC 27 for the remaining capacity of the battery pack 41 at block 213. When the UEFI firmware determines that the remaining capacity of the battery pack 41 is greater than the predetermined threshold, the UEFI firmware proceeds to block 215, and when it determines that the remaining capacity is less than the predetermined threshold, the UEFI firmware returns to block 211.

  In block 215, the UEFI firmware sets the cache controller 53 to the write-back method, and in block 231 to the write-through method. According to the procedures of blocks 211 and 213, when there is no vibration, the write-through method is set, and when there is vibration and the remaining capacity of the battery pack 41 is large, the write-through method is set. When the UEFI firmware vibrates and the remaining capacity of the battery pack 41 is small, POST is interrupted until it stops. The UEFI firmware is set to the write-through method because the power supply may become unstable when the battery capacity is low.

  In block 217, the UEFI firmware sets an AOAC flag in register 59 to inform AOAC application 81 that the system has woken for AOAC processing. In block 219, the UEFI firmware sets the register 61 to S3_APS disabled, and after using the function of S3_APS for the vibration determination in block 211, stops it until the next resume.

  When the UEFI firmware sends a spin-up command to the HDD 23 in block 221, the HDD 23 spins up. The HDD 23 that has started the spin-up performs a self-inspection of a servo system such as an actuator that drives the head and a spindle motor that rotates the magnetic disk 24. This servo system inspection takes more time than the electronic circuit system inspection. The HDD 23 sends a ready signal to the UEFI firmware when the self-inspection of the servo system is completed.

  In the procedure so far, the HDD 23 is not spun up from the block 201 to the block 219 by setting PUIS to be enabled. Since the spin-up starts at block 221, it is possible to reduce the risk of damaging the HDD 23 due to vibration by shortening the spin-up time in a time zone in which S0_APS does not function. However, the resume is also performed at the user event. If the spin-up timing is delayed when resuming due to a user event, the POST time is delayed, which causes stress on the user.

  In order to prevent a delay in the POST time at the time of a user event, the UEFI firmware sends a spin-up command when PUIS is enabled in block 205 and receives the ready signal from the HDD 23 before receiving the HDD data from the magnetic disk 24. Do not read. Before receiving the ready signal, the UEFI firmware uses the HDD data stored in the firmware ROM 25 to advance the POST, and spins up when the POST advances to receive the ready signal, and sets PUIS to enable. The delay of the POST time due to this is suppressed.

  In block 301 of FIG. 6, the UEFI firmware receives ready signals from each device and confirms that they are available. When the ready signal is received from all devices, the resume processing is taken over from the UEFI firmware to the OS. The UEFI firmware notifies the AOAC application 81 of the AOAC wake when taking over POST to the OS.

  The OS restores the system context to the cache and registers of the CPU 11 and other devices in order to return the system to the state of the block 101 in FIG. In block 303, the system transitions to the AOAC_S0 state. In the AOAC_SO state, the system returns to the state of the block 101, and the AOAC application 81 accesses the network through the WiFi card 26 and starts update processing.

  In block 305, the AOAC application 81 starts the update operation. At this time, the cache controller 53 is set to the write-through method when there is no vibration before transitioning to the AOAC_SO state, and is set to the write-back method when there is vibration. When the write-through method is set, the magnetic disk 24 is spun up when writing to the HDD 23. However, there is no vibration, so that there is no risk of damaging the HDD 23, and there is no data loss during synchronization. Risk can be reduced.

  When the write-back method is set, the update data is written only to the flash memory 19 if the flash memory 19 has free space, so the magnetic disk 24 does not spin up. When there is vibration, it is more advantageous to reduce the risk of HDD damage by setting the write-back method than setting the write-through method. Therefore, in the AOAC_S0 state, AOAC processing can be performed regardless of the presence or absence of vibration, and harmony between prevention of HDD damage and reduction of the risk of lost update data during synchronization can be achieved.

  In block 307, the PM utility 83 inquires of the free space of the flash memory 19 to the cache controller 53 through the OS 85. When the free capacity of the flash memory 19 becomes less than the predetermined value, the process proceeds to block 309, and when there is a sufficient free capacity, the process proceeds to block 315. In block 309, the PM utility 83 inquires the cache controller 53 about the current cache mode through the OS 85. When the write-through method is set assuming that there is no vibration, the process proceeds to block 311, and when the write-back method is set assuming that there is vibration, the process proceeds to block 315.

  In block 311, the PM utility 83 inquires the remaining capacity of the battery pack 41 from the EC 27 through the UEFI firmware. When the remaining capacity of the battery pack 41 is large, the process proceeds to block 313, and when it is small, the process proceeds to block 315. In block 313, the PM utility 83 requests the cache controller 53 to flush the flash memory 19 through the OS 85. As a result, predetermined data in the flash memory 19 is written to the magnetic disk 24 to form a free space. When the free space of the flash memory 19 is sufficient, when the remaining capacity of the battery pack 41 is low, or when the write back method is set, the flash is not flashed in the current AOAC_S0 state, and the transition to the AOAC_S0 state is performed thereafter. At the opportunity.

  The user may continue to use the notebook PC 10 using the fact that the system has transitioned to the AOAC_S0 state. In this case, it is necessary to change the system to the S0 state. At block 315, PM utility 83 monitors for the presence of user events. When a user event is generated by the user operating the mouse or keyboard, the process proceeds to block 411 in FIG. 7, and when a user event is not generated, the process proceeds to block 317. When the PM utility 83 that has determined that the AOAC processing is completed in block 317 generates a sleep event (system event) (time t2, t4, t6) and requests the OS 85 to transition to the S3 state, block 319 Then, the system transits to the S3 state and proceeds to block 109 in FIG.

  In block 401 of FIG. 7, the UEFI firmware sets the cache controller 53 to the write-through method. In block 403, the UEFI firmware sets the HDD 23 to PUIS disabled. In block 405, the UEFI firmware sets the EC61 register 61 to S3_APS disabled. In block 407, the UEFI firmware sends a spin-up command to the HDD 23. When the UEFI firmware receives a ready signal from all devices at block 409, the AOAC flag of the register 59 is cleared at block 411 and POST is transferred to the OS85.

  When the block 315 in FIG. 6 is shifted to the block 411, the AOAC_S0 state is shifted to the S0 state at this point, and the system does not shift to the S3 state even when the AOAC process is completed. The system transitioned to the S0 state in block 413 moves to block 103 in FIG. In the above procedure, the AOAC wake is continuously performed. In one example, an AOAC event is generated each time the WiFi card 26 detects an SSID of a connectable AP. In another example, when the WiFi card 26 first detects an AP, the WiFi card 26 generates an AOAC event, and thereafter, the RTC 50 generates an AOAC event at a constant period until a user event is generated. Can do.

[Second method]
FIG. 8 is a time chart for explaining a second method of AOAC processing, and FIGS. 9 to 12 are flowcharts showing procedures corresponding thereto. 9 to 12 include many procedures common to FIGS. 4 to 7, the same reference numerals are assigned to the common procedures, and description thereof is omitted or simplified. In FIG. 9, the procedure of block 107 in FIG. 4 is omitted. When a transition is made to block 109 via a path via block 319 (time t4, t6, t8) in FIG. 11, PUIS is set to enable, cache mode is set to write back, and S3_APS is set to disabled. Yes.

  When a transition is made to block 109 via a path passing through block 101 (time t0) in FIG. 9 or block 413 (time t2) in FIG. 12, PUIS is set to disabled, cache mode is set to write through, and S3_APS is set to Enabled is set. That is, when transitioning from the S0 state to the S3 state, PUIS is disabled, the cache mode is set to write through, and S3_APS is enabled.

  When the state transitions from the AOAC_S0 state to the S3 state, PUIS is set to enable, the cache mode is set to write back, and S3_APS is set to disabled. When PUIS is disabled in block 501 of FIG. 10, the HDD 23 is spun up at the same time as the power is turned on.

  The state in which PUIS is disabled in the S3 state is a case where the state transitions from the S0 state at times t0 and t2 in FIG. The transition between the S0 state and the S3 state is repeated when the user uses the system. At this time, a user event is generated in block 111 of FIG. Since the user event may be assumed to be generated in a stationary state, even if PUIS is set to disable and the HDD 23 is turned on when the power is turned on, there is little risk of damage to the HDD 23. In addition, since the HDD 23 can transmit a ready signal to the UEFI firmware in a short time, the POST time can be shortened and the convenience of the user can be improved.

  However, when used in an environment in which the prevention of damage to the HDD 23 is prioritized over this convenience, the PUIS may be enabled even if the transition source for the S3 state is either the S0 state or the AOAC_S0 state. In the case of AOAC wake in block 207 of FIG. 10, the process proceeds to block 503 (time t3, t5, t7), and in the case of user wake, the process proceeds to block 551 in FIG. 12 (time t1, t9). In block 503, the process proceeds to block 221 when the AOAC flag is set in the register 59, and to block 209 when it is not set.

  That is, in the case of the second and subsequent AOAC wakes among consecutive AOAC wakes, the AOAC flag has already been set, so that write back is set in block 215, S3_APS is disabled in block 219, and block 511 Thus, PUIS is set to enable. At this time, the UEFI firmware skips the path from block 209 to block 511 and transmits a spin-up command in block 221. By skipping the path from block 209 to block 511, the resume process is completed in a short time, and the feasibility of the timely AOAC process is improved.

  In the case of the first AOAC wake, since the AOAC flag is not set, PUIS is set to disable, the cache mode is set to write through, and S3_APS is set to enable. In the case of AOAC wake, the notebook PC 10 may be vibrating. In block 505, POST is stopped while S3_APS detects vibration. Then, when S3_APS does not detect vibration, the path from block 507 to block 511 is executed, and the process proceeds to block 301 in FIG.

  When the remaining capacity of the battery pack 41 is small at block 507, the resume is stopped at block 509 so that the write back mode is not set when the power source is unstable. In this case, it is necessary to charge the battery pack 41 in order to perform the AOAC process. In order to completely prohibit the operation in the write-back method in a state where the power supply is unstable, the procedure of blocks 507 and 509 can be put in the middle of the path from block 503 to block 221.

  In block 511, PUIS is enabled. In block 315 of FIG. 11, if a user event is generated during the AOAC_S0 state, PUIS is disabled in block 531 and cache mode is set to write-through in block 533, and the block of FIG. 411. In block 551 of FIG. 12, the current cache mode is determined at the time of user wake.

  When the AOAC wake does not occur between the S0 state and the S3 state, the write-through method is set, but when the AOAC wake occurs, the write back is set. When the write back method is set, the block 401 sets the write through method. When the write-through method is set, the process proceeds to block 405.

[Others]
The AOAC processing method described with reference to FIGS. 3 to 12 shows an example of the present invention, and it is not necessary to execute all the procedures shown in the flowchart as long as the principle of the present invention can be realized. Procedures can be interchanged, different known methods can be employed, and additional procedures can be added. Here, the S3 state has been described as an example of the sleep state, but the present invention is not limited to this, and when a certain period of time has elapsed since the S4 state or OS 85 capable of system wake-up transitions to the S3 state. The S4 state may be automatically changed by the UEFI firmware.

  The flash memory 19 can be stored in the HDD 23 as long as the system is a cache that manages caching. The arrangement of various registers provided in the PCH 17, the EC 27, and the power controller 33 is not limited to the exemplified device, and may be provided in a device different from the exemplified device. In the present invention, when the write back method is set in the AOAC_S0 state, the free space of the flash memory 19 is secured to reduce the spin-up frequency.

  When access to the HDD 23 occurs in the AOAC_S0 state, the UEFI firmware needs to spin up the HDD 23 at the resume stage and receive a ready signal. Access to the HDD 23 can be completely stopped in the AOAC_S0 state by securing a capacity of the flash memory 19 that can be used for executing a program operating in the AOAC process and storing data. In that case, the HDD 23 can be kept in the spin-down state at the resume stage, so that the risk of HDD damage can be further reduced.

  Although the present invention has been described with the specific embodiments shown in the drawings, the present invention is not limited to the embodiments shown in the drawings, and is known so far as long as the effects of the present invention are achieved. It goes without saying that any configuration can be adopted.

10 Notebook PC
17 Chip set (PCH)
19 Flash memory 23 HDD
24 Magnetic disk 25 Firmware ROM
33 Power controller

Claims (17)

A method of controlling a power state by a portable computer equipped with a storage device having a rotating disk and a nonvolatile semiconductor memory functioning as a cache of the storage device set to a write-back method or a write-through method. And
Transitioning to a sleep state in which the portable computer is set to the write-back method or the write-through method, and the storage device is powered off ;
Initiating a resume process in response to a first system event generated during the sleep state to perform a predetermined process in a power-on state ;
In response to determining that the acceleration generated in the portable computer during the resume process is greater than or equal to a predetermined value, and setting the write back method;
A step of migrating in response to the second system events generated in response to the end of the predetermined processing after the transition to the power-on state from the power-on state to the sleep state,
And setting to the write-through method during a resume process in response to a user event generated by a user operation during the sleep state .   The method of claim 1, further comprising setting the write-through method in response to determining that the acceleration is less than or equal to a predetermined value during a resume process in response to the first system event.   3. A method according to claim 1 or claim 2, wherein the first system event is generated when the mobile computer in motion detects a predetermined wireless access point.   4. A method according to any one of claims 1 to 3, wherein the first system event is generated at regular time intervals by the timekeeping device of the mobile computer being moved. The predetermined process, the method according to any one of claims 1 to claim 4, portable computer having a processing of acquiring and storing the update data from a network connected wirelessly by executing a predetermined program.   The storage device comprising a rotation suppression mechanism that stops rotation of the disk when power is turned on, and enabling the rotation suppression mechanism before generating the first system event; A method according to any one of claims 1 to 5, comprising:   The method according to claim 6, further comprising reading data necessary for initializing the storage device stored in the disk during the resume process from a nonvolatile semiconductor memory. Monitoring the free capacity of the nonvolatile semiconductor memory in the power-on state;
8. The method according to claim 1, further comprising: writing data stored in the non-volatile semiconductor memory to the disk when it is determined that the free capacity is less than a predetermined value, and securing a predetermined free capacity. The method described. Monitoring the remaining capacity of a battery that supplies power to the portable computer;
The method according to any one of claims 1 to 8, wherein the step of setting the write back method is executed when it is determined that the acceleration is equal to or greater than a predetermined value and the remaining capacity is greater than a predetermined value. This is a method for controlling the power state of a portable computer equipped with a storage device having a rotating disk and a nonvolatile semiconductor memory functioning as a cache of the storage device set to a write-back method or a write-through method. And
Initiating a resume process in response to a wake event generated during a sleep state in which the storage device is powered off ;
Determining the type of the wake event during the resume process;
Responsive to determining that the wake event is a system event for performing predetermined processing in a power-on state, setting the write back method during the resume processing ;
In response to determining that the wake event is a user event, setting the write-through method during the resume process ;
A step to shift to the sleep state from the power-on state in response to system events generated in response to the end of the predetermined processing after the transition to the power-on state,
Having a method. Determining the magnitude of acceleration generated in the portable computer during a resume process in response to the system event;
The method according to claim 10, wherein the step of setting the write back method is executed when the acceleration is equal to or less than a predetermined value. Monitoring the remaining capacity of a battery that supplies power to the portable computer;
The method according to claim 11, wherein the step of setting the write back method is executed when the acceleration is equal to or less than a predetermined value and the remaining capacity is greater than a predetermined value. A portable computer equipped with a storage device with a rotating disk and a non-volatile semiconductor memory functioning as a cache for the storage device set to write-back method or write-through method is connected to the wireless access point while moving A method for updating data by a predetermined application program,
Transition to a sleep state in which the portable computer is set to the write-back method or the write-through method and the storage device is powered off ;
Initiating a resume process in response to a system event generated by the portable computer for updating data in a power-on state ;
A step in which the portable acceleration generated in the computer is transferred to the power-on state is set to the write-back method in response to determining that the predetermined value or more during the resume process,
Communicating with the wireless access point in the power-on state to update data;
Transitioning from the power-on state to the sleep state in response to completion of data update;
And setting to the write-through method during resume processing in response to a user event generated by a user operation. A portable computer equipped with a storage device with a rotating disk and a non-volatile semiconductor memory functioning as a cache for the storage device set to write-back method or write-through method is connected to the wireless access point while moving A method for updating data by a predetermined application program,
Transitioning the portable computer to a sleep state in which the storage device is powered off ;
Initiating a resume process in response to a wake event generated by the portable computer;
Determining the type of the wake event during the resume process;
To the power-on state is set to the write-back method during the resume process in response to the wake event it is determined to be the system event for the updating of the data in the power-on state The transition steps,
In response to determining that the wake event is a user event, setting the write through method during the resume process and transitioning to a power on state;
Communicating with the wireless access point in a power-on state set to the write back method to update data;
Transitioning from the power-on state to the sleep state in response to completion of data update. In a portable computer equipped with a storage device including a rotating disk and a nonvolatile semiconductor memory that can be set to a write-back method or a write-through method with respect to the disk,
Setting the write-back method or the write-through method to enter a sleep state in which the power of the storage device is stopped ;
Initiating a resume process in response to a system event generated during the sleep state to write update data in a power-on state ;
In response to determining that vibration is occurring in the portable computer during the resume process, setting to the write back method;
A step of migrating the power-on and connected to the network after the transition to state a predetermined program in response the particular writing update data in the nonvolatile semiconductor memory from said power-on state to the sleep state,
A computer program for executing a process having a step of setting to the write-through method during a resume process in response to a user event generated by a user operation during the sleep state . In a portable computer equipped with a storage device including a rotating disk and a nonvolatile semiconductor memory that can be set to a write-back method or a write-through method with respect to the disk,
Initiating a resume process in response to a wake event generated during a sleep state in which the storage device is powered off ;
Determining the type of the wake event during the resume process;
Responsive to determining that the wake event is a system event for writing update data in a power-on state, setting the write back method during the resume process ;
In response to determining that the wake event is a user event, setting the write-through method during the resume process ;
After transitioning to the power-on state set in the write-back method, the sleep mode is switched from the power-on state to the sleep in response to a predetermined program writing update data to the nonvolatile semiconductor memory after connecting to the network. A computer program for executing a process having a step of shifting to a state.   A computer comprising a storage device storing the computer program according to claim 15 or 16.

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