CN116243997A - Chip system, starting method thereof and electronic equipment - Google Patents

Abstract

A chip system, a starting method thereof and electronic equipment are provided. The chip system includes: the first memory is a disposable memory; the second memory is an erasable memory; the first-stage starting module is positioned in the first memory and is used for starting the dormancy wakeup module under the condition that the dormancy wakeup mode is determined; the dormancy wakeup module is positioned in the second memory and used for enabling the chip system to restore to an operation state before the dormancy mode. The embodiment of the application puts the quick wake-up function into the erasable memory instead of the disposable memory, and can modify the software function according to the requirement at a later stage. The embodiment of the application is beneficial to reducing the complexity of the curing codes of the disposable memory, improving the expansibility of a chip system and shortening the development time of the curing software.

Description

Chip system, starting method thereof and electronic equipment

Technical Field

The embodiment of the application relates to the technical field of data storage, and more particularly relates to a chip system, a starting method thereof and electronic equipment.

Background

In recent years, with the wide application of the system-in-chip, the performance requirement of the system-in-chip is also higher and higher. The chip is started by adopting a two-stage starting or multi-stage starting mode. The two-stage boot is called a first-stage boot and a second-stage boot, respectively, and the first-stage boot is usually cured in a Read Only Memory (ROM) of a system-on-chip. The system-level chip has higher performance requirements on dormancy wakeup, and the system-level chip can recover to a normal working state as soon as possible after receiving a wakeup event so as to meet application requirements.

The current fast wake-up module is usually stored in ROM and cannot be modified after chip streaming. The quick wake-up function is usually complex, needs to realize the development requirement of individuation of users, and is put into the solidified ROM software, so that the complexity of solidified codes is increased, and the subsequent expansion is inconvenient.

Disclosure of Invention

The embodiment of the application provides a chip system, a starting method thereof and electronic equipment. Various aspects related to embodiments of the present application are described below.

In a first aspect, there is provided a chip system comprising: the first memory is a disposable memory; the second memory is an erasable memory; the first-stage starting module is positioned in the first memory and is used for starting the dormancy wakeup module when the dormancy wakeup mode is determined; the dormancy wakeup module is positioned in the second memory and is used for enabling the chip system to restore to an operation state before the dormancy mode.

In a second aspect, a method for starting a chip system is provided, the chip system including: the first memory is a disposable memory; the second memory is an erasable memory; the first-stage starting module is positioned in the first memory; the dormancy wakeup module is positioned in the second memory; the starting method comprises the following steps: when the chip system is electrified, the primary starting module is operated to determine a starting mode of the chip system; and if the chip system is in the sleep and wake-up mode, operating the sleep and wake-up module so as to enable the chip system to be restored to the operating state before the sleep mode.

In a third aspect, an electronic device is provided, comprising a chip system as described in the first aspect.

The embodiment of the application puts the quick wake-up function into the erasable memory instead of the disposable memory, and can modify the software function according to the requirement at a later stage. The embodiment of the application is beneficial to reducing the complexity of the curing code of the disposable memory, increasing the stability of the software cured to the disposable memory, improving the expansibility of a chip system and shortening the development time of the cured software.

Drawings

Fig. 1 is a schematic diagram of a chip system provided in an embodiment of the present application.

FIG. 2 is a schematic diagram of the structure of two boot image files.

FIG. 3 is a flow chart of one possible start-up mode of the chip system of FIG. 1.

Fig. 4 is a flow chart of another possible start-up mode of the chip system of fig. 1.

Fig. 5 is a flow chart of one possible implementation of step S3080 of fig. 4.

Fig. 6 is a flow chart of one possible implementation of step S3090 of fig. 4.

Fig. 7 is a flow chart of one possible implementation of step S3100 of fig. 4.

Fig. 8 is a flowchart of a method for starting up a chip system according to an embodiment of the present application.

Fig. 9 is a schematic structural diagram of an electronic device according to an embodiment of the present application.

Detailed Description

The following description of the technical solutions in the embodiments of the present application will be made clearly and completely with reference to the drawings in the embodiments of the present application, and it is apparent that the described embodiments are only some embodiments of the present application, not all embodiments.

In recent years, with the wide application of the system-in-chip, the performance requirement of the system-in-chip is also higher and higher. The start-up of the chip is a very important loop, and the start-up of the chip includes powering up the chip circuit, loading firmware required for the start-up of the chip, and the like.

A system-on-chip (SOC), also known as a system-on-chip (SOC), refers to a set of interconnected electronic circuits that are integrated into a complete system on a single chip. A SoC is typically an integrated circuit with dedicated targets that contains the complete system and has the entire contents of embedded software. The SoC may include, but is not limited to, a hardware core, memory, peripheral circuitry, and a communication interface. The hardware cores may include a variety of different types of processors, such as general purpose processors, CPUs, digital signal processors (digital signal processor, DSPs), graphics processing units (graph processing unit, GPUs), acceleration processing units (accelerated processing unit, APUs), auxiliary processors, single-core processors, and multi-core processors. In addition, the hardware core may also be embodied as other hardware and hardware combinations, such as application specific integrated circuits (application specific integrated circuits, ASICs), field programmable gate arrays (field programmable gate array, FPGAs), other programmable logic devices, split gate logic devices, transistor logic devices, performance monitoring hardware, watchdog hardware, time references, and the like. The integrated circuit may be configured such that components of the integrated circuit are located on a single piece of semiconductor material (e.g., silicon).

Firmware (firmware) is typically stored in a Read Only Memory (ROM), an electrically erasable read only memory (electrically erasable programmable ROM, EEPROM), a FLASH chip, and a program that can be updated by a user through a specific refresh program. The software, which typically acts as the most basic, bottom-most work, may refer to the device "driver" that is stored inside the device.

At present, a two-stage starting or multi-stage starting mode is adopted for starting the chip. The following is an illustration of a two-stage start-up. A chip (for example, VC 0728) is loaded by a two-stage boot (boot) loading system, which are called a first boot and a second boot, respectively, where the first boot is a bootloader, and the first boot is cured in a Read Only Memory (ROM) of an SoC, and the size of the ROM is 128KB. ROM operates in a non-destructive read mode, and only information which cannot be written can be read. The data stored in the ROM is usually written in advance. The ROM has stable stored data, and the stored data can not be changed after power failure, thus being applicable to storing various fixed programs and data. Therefore, the SoC chip development has higher requirements on solidifying ROM software, such as high stability, short development time, no influence on the chip streaming time node, and good expansibility.

The chip has a further 32KB of static random access memory (static random access memory, SRAM) for the running of the bootloader. SRAM is a type of random access memory that can be read and written at any time and is fast. By "static", it is meant that such memory is constantly maintained for data stored therein as long as it remains powered on.

The primary boot is a first code segment operated after the chip is electrified, and has the main functions of initializing the chip in a starting process and loading a secondary boot program stored on a solid storage medium into a memory for operation. The solid state storage medium may be, for example, SPI flash memory, SD card, EMMC, etc. Flash memory (Flash) may be generally classified into Nand Flash memory (Nand Flash), and Flash memory (Nor Flash), and Flash memory may employ a serial peripheral interface (serial peripheral interface, SPI). A secure digital card (secure digital memory card, SD card) is a high-speed memory device based on semiconductor flash memory. The embedded multimedia card (embedded multimedia card, EMMC) refers to a packaged memory consisting of a flash memory and a flash memory controller integrated on the same silicon chip.

The memory may be dynamic random access memory (dynamic random access memory, DRAM), DDR, etc. The data stored in the DRAM needs to be periodically updated and the power down data is lost.

The secondary boot may be a universal boot (U-boot), or may be an operating system kernel (such as kernel), or may be packaged together with the kernel to form a zImage image file. zImage is a compressed image file.

The normal starting-up flow of the chip is as follows: powering up, firstly, running a first boot, and loading a second boot into a memory; then, the whole process takes about 10 seconds to run to the user preset start-up program. The shorter this time, the better the user experience, especially in some applications requiring fast start-up, such as low power consumption products with batteries, e.g. law enforcement, parking recorders, etc.

Electronic products, particularly electronic products with battery, have high requirements for low power consumption, including: the power consumption of the sleep standby is low, the power of the module which can be powered down is reduced as much as possible, and the power of the module which cannot be powered down is reduced as much as possible. Meanwhile, the SoC has higher performance requirements on dormancy awakening, the awakening time is short, and the SoC needs to recover to a normal working state as soon as possible (within 2 seconds for example) after receiving an awakening event so as to meet application requirements.

The fast WAKE-up module (such as wkupimage. Bin) has the scene function before the fast recovery dormancy, and the important basis of the scene implementation is that the PMU module is always electrified, and the register value, the bus clock, the DDR register value, the WAKE_PC address (recovery scene function address) and the like of the CPU are saved before the system goes into dormancy.

The current fast wake-up module is usually stored in the ROM, when the system exits from the sleep mode, in the first boot operation stage, the wake-up source is judged first, if the wake-up source is fast wake-up (wakeup), the fast wake-up module (wkupimage. Bin) in the ROM is loaded, and the specified entry function of the wkupimage. Bin is jumped to execute the sleep wake-up process, so that the scene before sleep is quickly restored.

Since the firmware in the disposable memory (such as ROM) cannot be modified after the chip is streamed, if the ROM has firmware problems, the chip cannot be started normally. The quick wake-up function is generally complex and needs to realize the individual development requirement of the user, and is put into the solidified ROM software, so that the complexity of the solidified code is increased, the development difficulty is high, the development time of the solidified software is long, and the subsequent expansion is inconvenient.

Therefore, how to develop a fast wake-up start-up scheme with good flexibility is a problem to be solved.

Based on this, the embodiment of the application proposes a chip system. Fig. 1 is a schematic diagram of a chip system provided in an embodiment of the present application. The following describes the chip system in the embodiment of the present application in detail with reference to fig. 1. As shown in fig. 1, the chip system 100 may include a first memory 110 and a second memory 120.

The first memory 110 is a disposable memory such as a Read Only Memory (ROM). The data stored in the first memory 110 is stable, and the data stored after power failure is not changed, so that the method is suitable for storing various fixed programs and data. Programs in disposable memories after chip streaming are typically not modifiable.

The second memory 120 is an erasable memory. The erasable memory may be a memory device having an erasable memory function such as a flash memory, an SD card, an EMMC, an EEPROM, or the like. The second memory 120 may also hold data after the system is powered down and may be used to hold mirrored programs and data.

The first memory 110 includes a primary starting module, and the primary starting module has a data reading function. At power-on-chip start-up, the primary start-up module may be configured to start up a sleep wakeup module located in the second memory 120 when it is determined to be in a sleep wakeup mode.

The dormancy wakeup module is used for enabling the chip system to restore to an operation state before the dormancy mode. The sleep wake module is located in the second memory 120. Sleep mode, or sleep mode, refers to a state in which a desktop or computer will hold a copy of the desktop and all open files and images of the documents when not in use, and then may be powered off directly. When the power supply is started later, the files and the documents are restored and opened on the desktop according to the original use state. Sleep wakeup, or referred to as sleep wakeup, is not differentiated by the embodiments of the present application. Wake source events for sleep wake include, but are not limited to, key wake, PMU general purpose input output (PMU_GPIO) wake, real Time Clock (RTC) alarm wake, TIMER (TIMER) timed wake, etc.

The primary boot module typically contains a boot strap (or firmware) for the sleep wakeup module that is used to boot the sleep wakeup module.

The second memory 120 also typically includes a secondary boot module for performing system-on-chip initialization. The primary boot module further comprises a boot loader (or firmware) of the secondary boot module, and the primary boot module is further configured to load the boot loader of the secondary boot module in a normal boot mode to operate the secondary boot module. Such as a boot loader (bootloader) of the secondary boot module, is located in the primary boot module.

Therefore, in some implementations, when the chip is powered on, the first-stage starting module may quickly read the pre-stored sleep wakeup module from the second memory 120 according to the boot program of the sleep wakeup module, and quickly write the pre-stored sleep wakeup module into the static random access memory (or the memory) to start to operate the sleep wakeup module, so that the chip system is restored to the operating state before the sleep mode. In addition, when the dormancy wakeup module is updated, parameters are changed and the operation is wrong, corresponding parameter modification can be performed based on the programming capability of the dormancy wakeup module, so that the flexibility of parameter configuration during the operation of the chip is improved, and the configuration restarting times of the chip are reduced.

In some implementations, when the chip is powered on and started, the first-stage starting module may quickly read the pre-stored second-stage starting module from the second memory 120 and quickly write the pre-stored second-stage starting module into the static random access memory (or the memory) when the first-stage starting module is determined to be in the normal starting mode, so that the second-stage starting module completes the initialization of the chip based on the starting firmware of the chip. In addition, when the chip is updated, the parameters are changed and the operation is wrong, corresponding parameter modification or reset starting can be performed based on the programming capability of the secondary starting module, so that the flexibility of the parameter configuration during the operation of the chip is improved, and the configuration restarting times of the chip are reduced.

The chip system 100 may include a processor. The processor may be a general-purpose processor including a central processor, a micro-control unit, a network processor, or other conventional processor. But may be a special purpose processor including a digital signal processor, an application specific integrated circuit, a field programmable gate array or other programmable logic device, a discrete gate or transistor logic device, a discrete hardware component.

The chip system 100 may include a power management unit. The power management unit (power management unit, PMU) is a microcontroller that controls the power functions of the digital platform. The PMU may include firmware and software, memory, input/output functions, timers to measure time intervals, and analog-to-digital converters to measure main battery or supply voltage, etc. Even if the system-on-chip is completely shut down, powered by a battery backup, the PMU is typically one of the devices that can remain active.

The chip system 100 may further include a third memory, which is a static random access memory, for storing operation state information when the chip system is switched to the sleep mode. Such as saving the CPU's register values, bus clock, resume scene function (wake_pc) address to a third memory (which is not powered down during sleep) before the system goes to sleep. The third memory may be an independent sram or an sram inside the power management unit.

In some implementations, to further save power in sleep mode, only the PMU module may be powered up and the other modules all powered down, including the processor. During the sleep mode, the power management unit may enable the processor to be in a power-down state, and, to quickly resume the running state before sleep after the fast wake-up mode is started, the power management unit may control the third memory to be in a power-up state, so as to maintain the validity of the data stored in the third memory.

The chip system 100 may further include a fourth memory, which is a dynamic random access memory, for storing operation data of the processor and storing dynamic data during operation of the chip. The dynamic random access memory may be, for example, DRAM, synchronous dynamic random access memory (synchronous dynamic random access memory, SDRAM), double data rate synchronous dynamic random access memory (double data rate synchronous dynamic random access memory, DDR SDRAM), DDR2, DDR3, etc.

In some implementations, to enable a fast recovery to the running state before sleep after the fast wake mode is started, the power management unit is further configured to control the fourth memory to be in the self-refresh mode in the sleep mode to maintain validity of data in the fourth memory.

Dynamic random access memories generally include Auto Refresh (AR) and Self Refresh (SR). The AR, also known as periodic refresh, operates on the system clock. The SR is mainly used for data storage in a sleep mode low-power consumption state, does not depend on a system clock to work any more, and performs refresh operation according to an internal clock. Typically, all external signals during the SR, except the clock enable signal (CKE), are inactive, and only re-enabling CKE can exit the self-refresh mode and enter the normal operating state.

The embodiment of the application puts the quick wake-up function into the erasable memory instead of the disposable memory, and can modify the software function according to the requirement at a later stage. The embodiment of the application is beneficial to reducing the complexity of the curing code of the disposable memory, increasing the stability of the software cured to the disposable memory, improving the expansibility of a chip system and shortening the development time of the cured software.

Fig. 2 (b) is a schematic diagram of a boot image file of the system on chip of fig. 1. According to the embodiment of the application, the implementation flow of the dormancy rapid awakening is optimized, the dormancy awakening function is separated from the solidified ROM software and is used as an independent executable image (wkupimage. Bin), and the independent executable image and a secondary boot file zImage are packaged into a boot image (boot. Img) file which is stored in a second memory. And the software function can be modified according to the requirement in the later stage, and the boot. Img file can be modified.

Fig. 2 (a) is a schematic structural diagram of a Boot image file of a conventional chip system, where a conventional Boot. Img file generally includes Boot information (such as a 2K Info for Boot) and a kernel image (zImage) file. As shown in fig. 2 (b), compared with a conventional Boot. Img file, the Boot. Img file in the embodiment of the present application may include a Boot information (2K Info for Boot), a fast wake image (wkupimage. Bin), and a kernel image (zImage) file.

The size of the Boot information (e.g., 2K Info for Boot) may be 2K bytes (byte). The content of the 2K Info for Boot is mainly the initialization parameters driven by the second memory (e.g. SD, NAND Flash, EMMC), such as clock frequency, division ratio, line mode, transmission mode, etc. The 2K Info for Boot also includes the location, size, address loaded into memory, execution address, etc. of the wkupimage, bin and zlamge images on the storage medium (i.e., the second memory). In some embodiments, the 2K Info for Boot also includes initialization parameters for the DDR. The 2K Info for Boot information is very important, and in the practical application process, backup and data integrity verification are usually carried out, so that data storage errors are avoided, and starting failure is caused.

The fast wakeup image file is wkimage. wkImage. Bin has the scene function before the fast recovery dormancy, and an important basis for the scene implementation is that the PMU module is always electrified. Before the system goes to sleep, the register value, bus clock, DDR register value, resume scene function (e.g. WAKE_PC) address, etc. of the CPU are saved in the third memory, i.e. the static random access memory of the PMU module. The sram does not power down during sleep, so that the sram data remains in an active state during sleep. In some embodiments, the PMU module and enters a low power self-refresh mode into a system memory (e.g., DDR) such that the DDR data remains active during sleep.

When the PMU enters into dormancy, the PMU module can control the power supply domain of the CPU to be powered down, so that low-power-consumption dormancy is realized. If a wake-up source event is received during sleep, such as key wake-up, PMU general purpose input output (PMU_GPIO) wake-up, real Time Clock (RTC) alarm wake-up, TIMER (TIMER) wake-up, the PMU can control the CPU power domain to power up, start executing a primary boot process solidified in ROM, and read the PMU wake-up source status register.

If the wake-up source is fast wake-up (wakeup), loading wkimage. Bin to a preset memory address, executing a preset entry address function of the wkimage. Bin, and entering into executing a fast wake-up function. And clearing the WAKE-up source to avoid misjudging the WAKE-up source when starting next time, setting the DDR physical layer (PHY) as a normal working mode, acquiring a register value of the CPU, bus clock information, WAKE_PC address and DDR register value from a Static Random Access Memory (SRAM) of the PMU, and recovering the register value to a register of a corresponding module. So that the system resumes the running state before dormancy, exits the DDR self-refresh mode and runs the WAKE_PC address. The specific start-up procedure is described in detail below.

zImage is a compressed kernel image file, which may contain a universal boot (U-boot) and an operating system kernel (kernel). When the system is powered on or started, if the wake-up source is judged not to be the quick wakeup, initializing a memory (e.g. DDR), then loading zImage into the memory (e.g. DDR) from a second memory, executing a preset zImage address, and completing the initialization function of the system.

The U-boot is a boot loader mainly used for an embedded system, and can support a plurality of different computing system structures. U-boot can be generally divided into a primary boot and a secondary boot.

FIG. 3 is a flow chart of one possible start-up mode of the chip system of FIG. 1. The structure of the boot file of the system on chip of fig. 3 can be seen in fig. 2 (b). In the boot file of fig. 3, the hibernation wakeup function is used as an independent executable image, and may be a fast wakeup image (wwkupimage. Bin) file, which is stored in a second memory (erasable memory) together with a secondary boot file boot, and the software function may be modified later according to the requirement.

In the sleep mode of the chip system of fig. 3, the PMU module may control the power supply terminal of the DDR physical layer (PHY), so that the DDRPHY is in a low power consumption state during the sleep mode of the chip, and control the DDR to perform self-refresh, so as to maintain the validity of data. The chip exits from the sleep mode, and the PMU module can control the power supply end of the DDRPHY to enable the DDRPHY to exit from the low power consumption state to enter into the working state, and enable the DDR to exit from the self-refresh mode.

And in the primary boot operation stage, before the secondary boot is loaded, judging a wake-up source. If the wake is fast, loading a fast wake image (wkupimage. Bin), and jumping to the designated entry function of wkupimage. Bin to execute the sleep wake flow.

The fast wake-up start-up procedure in fig. 3 mainly includes steps S310 to S390, which are described in detail below. It should be understood that, the sequence number of each step in the embodiment of the present application does not mean that the execution sequence of each process should be determined by the function and the internal logic of each process, and should not limit the implementation process of the embodiment of the present invention in any way.

At step S310, a primary start-up module is started.

In step S320, a wake-up source is acquired.

In step S330, it is determined whether the wake source is fast wake? Before loading the secondary starting module, the wake-up source is judged. If the fast wake-up is a key wake-up, a PMU_GPIO wake-up, an RTC alarm wake-up, a TIMER timed wake-up start-up, then go to step S340; if not, go to step S390.

In step S340, the wake-up source is cleared to avoid misjudging the wake-up source next time (e.g., at the time of start-up).

In step S350, the DDR physical layer (PHY) is set to be in an operation mode.

In step S360, the system clock frequency is obtained from the static random access memory (i.e., the third memory) of the PMU, and the corresponding register is configured to control the clock frequency switching. The system clock frequency may include: the clock frequency of the ARM of the processor, the clock frequency of the Bus, the clock frequency of the memory (such as DDR), and the like.

In step S370, the configuration register of the DDR controller is obtained from the static random memory of the PMU, and the DDR is controlled to exit self-refresh.

In step S380, the operation jumps to the resume scene function (i.e., wake_pc) address.

In step S390, the wake-up source is cleared, and a Program Counter (PC) is set to zero, i.e., pc=0, so that the normal flow is restarted next time.

The embodiments of the present application place the fast wake-up function into erasable memory rather than into disposable memory. The software functions can be modified according to the requirements in the later stage, so that the complexity of the curing codes of the disposable memory is reduced, the stability of the software cured to the disposable memory is improved, the expansibility of a chip system is improved, and the development time of the cured software is shortened.

Fig. 4 is a flow chart of another possible start-up mode of the chip system of fig. 1. The structure of the boot file of the system on chip of fig. 4 can be seen in fig. 2 (b). In the boot file of fig. 4, the hibernation wakeup function is an independent executable image, which may be a fast wakeup image (wkupimage. Bin), and is stored in a second memory (erasable memory) together with a secondary boot file boot, and the software function may be modified later according to the user's requirement.

The fast wake-up start-up procedure in fig. 4 mainly includes steps S4010 to S4160, which are described in detail below.

In step S4010, power-on is started.

In step S4020, the interrupt is turned off, the shutdown Cache (Cache) and the memory management unit (memory manage unit, MMU) are cleared, the code is moved, and the first-level boot module is loaded into the static memory (or the memory).

In step S4030, the C-environment is entered to Start a Boot function, such as a vim_boot_start () function.

In step S4040, a clock frequency is initialized, such as a Bus, a universal asynchronous receiver transmitter (universal asynchronous receiver/transmitter, UART), and a Timer (Timer).

In step S4050, the serial port is initialized. And serial ports such as UART serial ports.

In step S4060, a timer is initialized.

In step S4070, a secondary boot method is selected. If the EMMC start mode is the EMMC start mode, the process goes to step S4080; if the SPI NAND flash memory starting mode is adopted, the step S4090 is entered; if the SD startup mode, the process advances to step S4100.

In step S4080, the EMMC is reconfigured for the EMMC start-up mode according to the start-up information (e.g., 2K Info for Boot).

In step S4090, for the SPI NAND flash Boot mode, the NAND flash is reconfigured according to the Boot information (e.g., 2K Info for Boot).

In step S4100, for the SD startup mode, the SD is reconfigured according to startup information (e.g., 2K Info for Boot).

In step S4110, it is determined whether the wake source is fast wake? If the fast wake-up is a key wake-up, a PMU_GPIO wake-up, an RTC alarm wake-up, a TIMER timed wake-up start-up, then go to step S4120; if not, the process proceeds to step S4140.

In step S4120, the fast wakeup image is loaded from the corresponding storage medium to the SRAM. For example, SPI NAND flash start mode, a fast wake up image is loaded from the NAND flash to the SRAM.

In step S4130, the specified address on the quick wakeup image (wkimage. Bin) is performed. And running a rapid wake-up module.

In step S4140, the DDR controller is initialized.

In step S4150, a kernel image (zImage) file is loaded from the corresponding storage medium to the DDRAM. For example, SD start-up mode, zImage is loaded from SD to DDRAM.

In step S4160, the specified address on zImage is executed. And running a kernel image (zImage) file to finish the initialization of the chip system.

Further details of step S3080, step S3090 and step S3100 in fig. 4 are developed below.

Fig. 5 is a flow chart of one possible implementation of step S3080 of fig. 4. The EMMC start-up mode flow in fig. 5 may mainly include steps S510 to S550, which will be described in detail below.

In step S510, the EMMC starts.

In step S520, EMMC initialization is performed.

In step S530, boot information (e.g., 2K Info for Boot) is attempted to be started from the EMMC.

In step S540, the clock frequency is switched according to the start-up guidance information.

In step S550, the EMMC is reconfigured according to the start-up guidance information.

Fig. 6 is a flow chart of one possible implementation of step S3090 of fig. 4. The SPI NAND flash start-up mode flow in fig. 6 mainly includes steps S610 to S650, which are described in detail below.

In step S610, SPI NAND Flash starts.

In step S620, NAND Flash initialization is performed.

In step S630, boot information (e.g., 2K info for boot) is attempted to be started from NAND Flash.

In step S640, the clock frequency is switched according to the start-up guidance information.

In step S650, the NAND Flash parameters are reconfigured according to the start-up boot information.

Fig. 7 is a flow diagram of one possible implementation of step S3100 of fig. 4. The SD start-up mode flow in fig. 7 mainly includes steps S710 to S750, which are described in detail below.

In step S710, SD starts.

In step S720, SD is initialized.

In step S730, boot information (e.g., 2K info for boot) is attempted to be started from SD.

In step S740, clock frequency switching is performed according to the start-up guidance information.

In step S750, the SD parameters are reconfigured according to the start-up guidance information.

Fig. 8 is a schematic structural diagram of an electronic device according to an embodiment of the present application. The electronic device 800 may include a chip system 810 as described in any of the preceding.

It should be noted that, the electronic device mentioned in the embodiments of the present application may be a device that provides voice and/or data connectivity to a user, and may be used to connect people, things, and machines, for example, a handheld device with a wireless connection function, an in-vehicle device, and so on. The electronic device may be referred to as a terminal, a portable terminal, a mobile terminal, a communication terminal, a portable mobile terminal, a touch screen, or the like. For example, the electronic device may be a smart phone, a portable phone, a game console, a television, a display unit, a notebook computer, a laptop computer, a personal computer (personal computer, PC), a personal media player (personal media player, PMP), a personal digital assistant (personal digital assistant, PDA), a mobile power source (charger, travel charger), an unmanned aerial vehicle, an electronic book, a smart electronic device (e.g., a wristwatch, a bracelet, a smart glasses, a sweeping robot, etc.), a small electronic product (e.g., a wireless headset, a bluetooth sound, an electric toothbrush, a chargeable wireless mouse), and the like. The electronic device may also be a portable communication terminal having a wireless communication function and a pocket size. The electronic device may communicate with an external electronic device such as a server or the like, or perform operations through interworking with the external electronic device.

The chip system and device embodiments of the present application are described in detail above in connection with fig. 1-8, and the method embodiments of the present application are described in detail below in connection with fig. 9. It is to be understood that the description of the method embodiments corresponds to the description of the system embodiments, and that parts not described in detail may therefore be referred to the previous system embodiments.

Fig. 9 is a flowchart of a method for starting up a chip system according to an embodiment of the present application. The system-on-chip may include a first memory and a second memory, the first memory being a disposable memory and the second memory being an erasable memory. The first-stage starting module is located in the first memory, and the dormancy wakeup module is located in the second memory.

As shown in fig. 9, the starting method mainly includes steps S910 to S920, which are described in detail below. It should be understood that the sequence number of each step in the foregoing embodiment does not mean that the execution sequence of each process should be determined by the function and the internal logic, and should not limit the implementation process of the embodiment of the present invention.

In step S910, when the chip system is powered on, the first-level start-up module is operated to determine a start-up mode of the chip system.

In step S920, if the chip system is in the sleep wake mode, the sleep wake module is operated to restore the chip system to the operation state before the sleep mode.

Optionally, the primary start-up module includes a boot program of the sleep wakeup module. The starting method of the embodiment of the application comprises the following steps: running a bootstrap program of the dormancy wakeup module to start the dormancy wakeup module; and operating the dormancy wakeup module to restore the chip system to an operation state before the dormancy mode.

Alternatively, the system-on-chip may include a secondary boot module located in the second memory. The primary start-up module also includes a boot strap for the secondary start-up module. The starting method of fig. 9 further includes: if the starting mode is the normal starting mode, a bootstrap program of the secondary starting module is operated to start the secondary starting module; and operating the secondary starting module to finish the initialization of the chip system.

The chip system may include: a processor; the third memory is a static random access memory; a power manager. Optionally, the starting method of the embodiment of the application includes: when the chip system is switched to the sleep mode, the third memory is used for storing the running state information of the chip system; in the sleep mode, the control processor is in a power-down state, and the third memory is controlled to be in a power-up state.

Optionally, the chip system further includes a fourth memory, where the fourth memory is a dynamic random access memory, and is used for storing operation data of the processor. The starting method of the embodiment of the application can further comprise the following steps: in the sleep mode, the fourth memory is controlled to be in a self-refresh mode.

In the above embodiments, it may be implemented in whole or in part by software, hardware, firmware, or any other combination. When implemented in software, may be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. When loaded and executed on a computer, produces a flow or function in accordance with embodiments of the present disclosure, in whole or in part. The computer may be a general purpose computer, a special purpose computer, a computer network, or other programmable apparatus. The computer instructions may be stored in a machine-readable storage medium or transmitted from one machine-readable storage medium to another machine-readable storage medium, for example, the computer instructions may be transmitted from one website, computer, server, or data center to another website, computer, server, or data center by a wired (e.g., coaxial cable, fiber optic, digital subscriber line (digital subscriber line, DSL)) or wireless (e.g., infrared, wireless, microwave, etc.). The machine-readable storage medium may be any available medium that can be accessed by a computer or a data storage device including one or more servers, data centers, etc. integrated with the available medium. The usable medium may be a magnetic medium (e.g., a floppy disk, a hard disk, a magnetic tape), an optical medium (e.g., a digital video disc (digital video disc, DVD)), or a semiconductor medium (e.g., a Solid State Disk (SSD)), or the like.

Those of ordinary skill in the art will appreciate that the elements and algorithm steps described in connection with the embodiments disclosed herein can be implemented as electronic hardware, or combinations of computer software and electronic hardware. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the solution. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present disclosure.

It should be understood that, in various embodiments of the present application, "first," "second," etc. are used to distinguish between different objects, and not to describe a specific order, the size of the sequence numbers of each process described above does not mean that the order of execution should not be construed as to imply that the order of execution of each process should be determined by its function and inherent logic, but should not be construed as limiting the implementation of the embodiments of the present application.

In the several embodiments provided in the present disclosure, it should be understood that the disclosed systems, devices, and methods may be implemented in other manners. For example, the apparatus embodiments described above are merely illustrative, e.g., the division of the units is merely a logical function division, and there may be additional divisions when actually implemented, e.g., multiple units or components may be combined or integrated into another system, or some features may be omitted or not performed. Alternatively, the coupling or direct coupling or communication connection shown or discussed with each other may be an indirect coupling or communication connection via some interfaces, devices or units, which may be in electrical, mechanical or other form.

In several embodiments provided herein, it will be understood that when a portion is referred to as being "connected" or "connected" to another portion, it means that the portion can be "directly connected" or "electrically connected" while another element is interposed therebetween. In addition, the term "connected" also means that the portions are "physically connected" as well as "wirelessly connected". In addition, when a portion is referred to as "comprising" an element, it is meant that the portion may include the other element without excluding the other element, unless otherwise stated.

The units described as separate units may or may not be physically separate, and units shown as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

In addition, each functional unit in each embodiment of the present disclosure may be integrated in one processing unit, or each unit may exist alone physically, or two or more units may be integrated in one unit.

The foregoing is merely specific embodiments of the disclosure, but the protection scope of the disclosure is not limited thereto, and any person skilled in the art can easily think about changes or substitutions within the technical scope of the disclosure, and it is intended to cover the scope of the disclosure. Therefore, the protection scope of the present disclosure shall be subject to the protection scope of the claims.

Claims (11)

1. A chip system, comprising:

the first memory is a disposable memory;

the second memory is an erasable memory;

the first-stage starting module is positioned in the first memory and is used for starting the dormancy wakeup module when the dormancy wakeup mode is determined;

the dormancy wakeup module is positioned in the second memory and is used for enabling the chip system to restore to an operation state before the dormancy mode.

2. The system on a chip of claim 1, wherein the primary start-up module includes a boot program of the sleep wakeup module, the boot program configured to start up the sleep wakeup module.

3. The chip system of claim 1, comprising:

the second-level starting module is positioned in the second memory and is used for finishing the initialization of the chip system;

the primary starting module further comprises a bootstrap program of the secondary starting module, and the primary starting module is further used for loading the bootstrap program of the secondary starting module in a normal starting mode so as to operate the secondary starting module.

4. A chip system according to claim 3, comprising:

a processor;

the third memory is a static random access memory and is used for storing running state information when the chip system is switched to the sleep mode;

and the power management unit is used for controlling the processor to be in a power-down state and controlling the third memory to be in a power-up state in the sleep mode.

5. The chip system of claim 4, comprising:

the fourth memory is a dynamic random access memory and is used for storing operation data of the processor;

the power management unit is further configured to control the four memories to be in a self-refresh mode in the sleep mode.

6. A method of starting a chip system, the chip system comprising:

the first memory is a disposable memory;

the second memory is an erasable memory;

the first-stage starting module is positioned in the first memory;

the dormancy wakeup module is positioned in the second memory;

the starting method comprises the following steps:

when the chip system is electrified, the primary starting module is operated to determine a starting mode of the chip system;

and if the chip system is in the sleep and wake-up mode, operating the sleep and wake-up module so as to enable the chip system to be restored to the operating state before the sleep mode.

7. The method of claim 6, wherein the primary start-up module includes a boot program of the sleep wakeup module, and wherein the running the sleep wakeup module to resume the on-chip system to an operational state prior to a sleep mode includes:

running a bootstrap program of the dormancy wakeup module to start the dormancy wakeup module;

and operating the dormancy wakeup module so as to enable the chip system to restore to an operating state before the dormancy mode.

8. The method of starting up of claim 6, wherein the system-on-chip comprises:

the second-level starting module is positioned in the second memory;

the primary starting module further comprises a bootstrap program of the secondary starting module;

the starting method further comprises the following steps:

if the starting mode is a normal starting mode, a bootstrap program of the secondary starting module is operated so as to start the secondary starting module;

and operating the secondary starting module to finish the initialization of the chip system.

9. The method of starting up of claim 8, wherein the chip comprises:

a processor;

the third memory is a static random access memory;

a power manager;

the starting method further comprises the following steps:

when the chip system is switched to the sleep mode, the third memory is utilized to store the running state information of the chip system;

and in the sleep mode, controlling the processor to be in a power-down state and controlling the third memory to be in a power-up state.

10. The method of starting up of claim 9, wherein the chip system comprises:

the fourth memory is a dynamic random access memory and is used for storing operation data of the processor;

the starting method further comprises the following steps:

and in the sleep mode, controlling the fourth memory to be in a self-refresh mode.

11. An electronic device comprising a chip system according to any of claims 1-5.

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