JP6018113B2 - Method, computer and host device for preventing data loss of nonvolatile memory - Google Patents

Description

  The present invention relates to a technique for preventing data loss of a nonvolatile memory over time, and further relates to a technique for preventing data loss while a host device is transitioning to a standby state.

  A solid state drive (SSD) equipped with an electrically rewritable flash memory has been adopted in a host device such as a computer or a tablet terminal in place of a conventional hard disk drive (HDD). Unlike the DRAM, the flash memory can maintain the memory for a relatively long time even when the power of the SSD is stopped, but the data retention time (Retention time) is limited. It is known that this data holding time is shortened depending on the number of times of erasing or writing of memory cells.

  Japanese Patent Application Laid-Open No. 2004-228561 discloses an invention in which the SSD connected to the main body manages the power supply stop and turn-on times of the main body to calculate the elapsed time while the SSD is stopped, and determines the retention check timing. Here, in the retention check, when reading data, a normal read voltage is applied to the control gate to read data, and a voltage higher than the normal read voltage is applied to the control gate to read and read data 2 When the logics of two data are different, it means an operation of reprogramming by judging that the threshold voltage of the memory cell is lowered.

  Patent Document 2 discloses an invention in which a memory card detached from a main body refreshes by managing data retention time with an internal battery. In the present invention, the data retention time from the point when writing to the page is completed is managed by the memory card with less power consumption, and refreshed at intervals shorter than the data retention time. Patent Document 3 discloses an invention in which power is periodically supplied to a circuit necessary for refreshing a memory chip and refreshed when the device is stopped in order to maintain the storage of a deteriorated ferroelectric memory. Is disclosed.

  Patent Document 4 discloses an invention in which a flash memory device refreshes periodically or by receiving a command from the host while the host is powered on. Patent Document 5 discloses an RTC wakeup function that wakes up a computer at a predetermined time using a real time clock (RTC) incorporated in a chip set.

Special table 2010-515953 gazette JP 2007-48347 A Japanese Patent Laid-Open No. 2004-28097 JP 2009-223876 A JP 2012-226777 A

  The SSD connected to the host device receives power supply from the host device. When the host device is not used, the host device may shift to a power saving state and stop the power of the SSD. While both the host device and the SSD are operating while being supplied with power, a retention check can be performed as in the invention of Patent Document 1 to prevent data loss. Further, as in the invention of Patent Document 4, it is possible for the SSD to receive a command from the host or to periodically refresh itself. However, such a method cannot be adopted when the power of the host device or the SSD is stopped in the standby state.

  When an internal battery is mounted on an SSD as in the invention of Patent Document 2, refreshing is possible even in a standby state, but in addition to an increase in cost and an increase in size, battery capacity management and the like become problems. A method in which the host device periodically powers on and refreshes the SSD as in Patent Document 3 is applied to the host device that transitions to a standby state because the host device is presumed to be powered on. It is not possible. In addition, standby power of the host device increases when the SSD is periodically turned on regardless of the data holding time.

  SUMMARY OF THE INVENTION An object of the present invention is to provide a method for preventing data loss in a nonvolatile memory connected to a host device that transits to a standby state. It is another object of the present invention to provide a method for preventing data loss in a nonvolatile memory while reducing standby power of a host device. It is a further object of the present invention to provide a method for preventing data loss in a non-volatile memory while minimizing hardware changes. A further object of the present invention is to provide a host device and a computer that realize such a method.

  The non-volatile memory according to the present invention considers that the reliability of data is reduced and substantially lost when the data holding time has elapsed since writing. In order to prevent such loss of data in the nonvolatile memory, it is effective to measure the elapsed time from the data writing time and to refresh before the data holding time elapses. However, since the power supply of the storage device needs to be stopped when the computer transits to the standby state, the elapsed time cannot be measured in a storage device without an internal power source.

  The computer measures and monitors the elapsed time from the transition to the standby state in the standby state to the disappearance time at which the data stored in the nonvolatile memory is lost. Information about the writing time and data holding time necessary for calculation of the disappearance time can be acquired from the storage device before transition to the standby state. In the first aspect of the present invention, when the computer determines that the disappearance time has arrived based on the elapsed time, the computer turns on power to the storage device and circuits necessary for sending a refresh command. Send a refresh command to. Therefore, loss of data can be prevented while maintaining the standby state.

  The storage device may be a static disk drive that stores an operating system. The non-volatile memory may be a hard disk drive cache. The type of non-volatile memory is not particularly limited as long as it can prevent data loss by refresh. If the refresh command is sent before the operating system is loaded after the standby computer is turned on, it is useful for preventing an increase in standby power and shortening the refresh time.

  The power supply control unit can reduce standby power by stopping the power supply in the standby state, wakeup at a predetermined timing, and monitoring the elapsed time. The predetermined timing of the wake-up may be a fixed cycle, or may be set to a different cycle by setting a different time each time before the power is stopped again after wake-up. If the timing unit is a control unit of a battery unit that controls charging / discharging of the battery that supplies power to the computer, there is no need to change hardware, and standby power does not increase for the timing operation. The power supply control unit sets the elapsed time until the disappearance time before the power supply stops after transitioning to the standby state, and if the battery unit wakes up the power supply control unit when the elapsed time arrives, The control unit will not wake up unnecessarily.

  In addition, the timing unit may be a wakeup circuit including a real time clock that generates system time information. The power supply control unit can set the disappearance time in the wakeup circuit before the power supply stops after the transition to the standby state, and the wakeup circuit can also wake up the power supply control unit when the disappearance time arrives. In this case as well, there is no need to change hardware, and standby power for timekeeping operation does not increase.

  In the second aspect of the present invention, the storage device includes a refresh terminal that is referred to by the controller to determine the necessity of refresh. The timer unit counts the remaining time until the data stored in the non-volatile memory disappears after transitioning to a standby state in which the power of the storage device is stopped. The power control unit turns on the power to the storage device in response to the passage of the remaining time. The setting unit sets a refresh terminal by outputting a refresh signal in response to the passage of the remaining time. In this case, in the standby state, if power is turned on to the power supply of the storage device and the circuit that outputs the refresh signal, the data can be refreshed before being lost.

  The setting unit can set the refresh terminal via a sideband that does not use an interface. If the clock unit and the setting unit are configured by a battery unit that supplies power to the computer, or if a wake-up circuit that includes a real time clock that generates system time information is configured, the standby power is not increased. However, you can refresh just by adding sidebands.

  According to the present invention, it is possible to provide a method for preventing data loss of a nonvolatile memory connected to a host device that transits to a standby state. Furthermore, according to the present invention, it is possible to provide a method for preventing data loss in the nonvolatile memory while reducing standby power of the host device. Furthermore, according to the present invention, it is possible to provide a method for preventing data loss in a nonvolatile memory while minimizing hardware changes. Further, according to the present invention, a host device and a computer that realize such a method can be provided.

It is a functional block diagram for demonstrating a structure required for understanding of this embodiment of notebook PC10 as an example of a host apparatus. 4 is a diagram for explaining the structure of a nonvolatile memory 37 of the SSD 30 and the data structure of a block management table 81. FIG. It is a figure for demonstrating the data structure of the refresh management tables 83 and 85 which EC40 stores. It is a flowchart for demonstrating the procedure in which the notebook PC10 performs the 1st refresh method.

[Meaning of terms]
First, terms used in this specification will be explained. The host device is a device capable of controlling the power supply of the SSD. The host device stops the power supply of the SSD during the transition to the power saving state (standby state), but can temporarily turn on the power at a timing that requires refreshing. The data retention time is assumed to maintain the data storage by maintaining the time or charge from the time when data is written to the flash memory page until the charge injected into the floating gate is lost and the data is assumed to be lost. Say time. When the elapsed time from the data writing time reaches the data holding time, it cannot be said that the data is stored with sufficient reliability, and is treated as being in a state equivalent to being substantially lost.

  The data retention time is an inherent performance of the flash memory and is shortened by the influence of the deterioration parameter. In the present invention, the method by which the host device acquires the data holding time is not limited. The data retention time is provided as a value associated with a degradation parameter that can be obtained from the active SSD by the flash memory or SSD manufacturer. The deterioration parameter can be mainly the number of erasures that is a premise of the number of times of writing, but the data holding time may be acquired including other deterioration parameters such as the number of readings and the use time. In the present embodiment, the deterioration parameter is typically described as the number of erasures.

  In this embodiment, since erasure is performed in units of blocks, which are a set of a plurality of pages, each of which is the minimum unit of reading and writing, the number of erasures occurs for each block, and the data retention time also occurs for each block. The write time is the time when data is written to the page. The disappearance time is the time when the data retention time has elapsed from the writing time. The remaining time is the time from the present time corresponding to the difference between the disappearance time and the current time until the data disappears. At this time, the data holding time corresponds to the time from the writing time to the disappearance time. Since erasure is performed in units of blocks, the disappearance time can be grasped as a concept of blocks. The disappearance time of each block corresponds to the time when the data retention time of the block elapses from the write time of the page written earliest in the block.

  Refresh refers to a process of reading data from a flash memory to a RAM and writing it to the same block before the disappearance time of each block arrives. In refresh, in order to prevent data loss when the SSD power supply stops during refresh, the data written in the original block is read to the RAM and written to the block in the refresh area, and then the original block is erased and a new refresh is performed. It can also be performed by a method of allocating as an area. The unit of the block to be refreshed is not particularly limited. Therefore, when one of the blocks approaches the disappearance time, all the blocks may be refreshed at once, or a single block whose disappearance time has arrived or a plurality of blocks that are close to the disappearance time are refreshed. May be.

[Configuration of notebook PC]
FIG. 1 is a functional block diagram for explaining a configuration necessary for understanding the present embodiment of a notebook personal computer (notebook PC) 10 as an example of a host device. In the present specification, three refresh execution modes from the first refresh method to the third refresh method will be described later. Each execution mode uses one of the elements shown in FIG. Therefore, all the elements shown in FIG. 1 are not essential elements of each execution mode. The essential elements of the present invention are as set forth in the appended claims.

  The notebook PC 10 transitions to a sleeping state such as a suspend state (S3 state) and a hibernation state (S4 state) in addition to a power-on state (S0 state) and a soft-off state (S5 state) defined by ACPI. The soft off state and the sleeping state are collectively referred to as a standby state in the present embodiment. Note that the normal operation of the notebook PC 10 returns from the soft-off state and the sleeping state to the power-on state, but in the standby state according to the present embodiment, power is supplied only to some devices required for refresh. There is also. The standby state of the present invention does not necessarily have to be associated with the ACPI power state, but the power supply of the SSD 30 is stopped in the standby state.

  Note that the standby state to which the present invention can be applied is not limited to the power state exemplified here, and can be a power saving state in which the power of at least the SSD 30 and the CPU 11 is stopped. Further, the standby power in the standby state does not always have to be constant. The standby state includes a state in which power is temporarily supplied to the SSD 30, the CPU 11, and other devices for refresh.

  The chip set 20 includes a USB (Universal Serial Bus), a SATA (Serial AT Attachment) bus, an SPI (Serial Peripheral Interface) bus, a PCI (Peripheral Component Interconnect) bus, a PCI-Express (PCIe) bus, and an LPC (Low Pin). An I / O controller 25 serving as an interface such as a (Count) bus is provided, and various devices corresponding to them can be connected.

  FIG. 1 illustrates a CPU 11, a system memory 13, a firmware ROM 15, an SSD 30, and an embedded controller 40 connected to the chip set 20 in order to understand the present embodiment. In a typical notebook PC, a USB connector, a communication module, a display, an audio device, and the like (not shown) are further connected to the chip set 20. The chip set 20 can supply power for each of a plurality of functional blocks. While power is supplied to all functional blocks in the power-on state, power can be reduced by supplying power only to the minimum necessary functional blocks corresponding to the power state in the standby state.

  As an example, the SSD 30 is connected to the SATA port, and the EC 40 is connected to the SPI port. The chip set 20 further includes an RTC 21 and an RTC memory 23. The RTC 21 performs a time measuring operation for generating a calendar time used by the system.

  The RTC memory 23 stores the calendar time generated based on the timing operation of the RTC 21. The OS can periodically correct the calendar time stored in the RTC memory 23 with the standard time acquired through the network. The calendar time stored in the RTC memory 23 is provided to the system and peripheral devices and used for file time stamps and schedule management.

  The RTC 21 and the RTC memory 23 operate with power supplied to the chip set 20 but operate with power supplied from a button battery (not shown) when power is not supplied. The generation of the calendar time does not stop regardless of the transition to any power state. The chip set 20 has a well-known RTC wakeup function.

  The RTC wakeup function refers to a process in which the chip set 20 changes the system from the standby state to the power-on state at the time set in the RTC memory 23 using the calendar time of the RTC memory 23. The RTC wakeup function is executed by the RTC wakeup circuit 24 configured by an input / output circuit for the RTC 21, the RTC memory, and the EC 40. When the RTC wakeup function is enabled, power is supplied to the RTC wakeup circuit 24 in the standby state.

  The RTC wakeup circuit 24 uses the RTC wakeup function to wake up the EC 40 when the disappearance time has arrived in the second refresh method. The RTC wakeup circuit 24 includes a code for setting the refresh terminal 39 through the sideband 34 when the disappearance time comes in the third refresh method.

  The SSD 30 includes an interface 31 that is connected to the chip set 20 via a serial bus 32, an MPU 33, a ROM 34 that stores firmware executed by the MPU 33, a RAM 35, a NAND flash memory 37, and a cache memory configured by DRAM or MRAM. 36 etc. are included. The SSD 30 is supplied with power from the DC / DC converter 51. The SSD 30 may be a built-in type housed in the casing of the notebook PC 10 or an external type connected by a connector provided on the casing.

  The MPU 33 functions as a controller that executes firmware and performs reading, writing, wear leveling, and refreshing on the flash memory 37. In order to realize a third refresh method to be described later, the SSD 30 can be provided with a refresh terminal 39 that is referred to by the MPU 33 when the power is turned on to determine the necessity of refresh. The refresh terminal 39 is connected to the RTC clock circuit 24 by the side band 34 and is connected to the battery unit 60 by the side band 38. The sidebands 32 and 38 are communication paths for sending a refresh signal when the power supply is stopped and communication using the serial bus 32 or the SM (System Management) bus 62 which is a basic communication path is not possible. is there.

  The RTC clock circuit 24 or the battery unit 60 can output a refresh signal and set the refresh terminal 39. The refresh terminal 39 can be composed of various known circuits. In one example, the FET is connected to the ground and the internal power supply of the SSD 30, and the refresh signal can be used as a terminal that changes to the ground potential when the FET is turned on and changes to the power supply potential when the FET is turned off. The MPU 33 of the SSD 30 provided with the refresh terminal 39 refers to the refresh terminal 39 every time the power is turned on and, when set, can perform refreshing in an idle state where there is no access from the CPU 11.

  As shown in FIG. 2, the flash memory 37 is logically divided into a management area, a spare area, a refresh area, and a user area. The management area is an area that cannot be accessed by the host device, and stores a block management table 81 in addition to an address conversion table that converts a logical block address (LBA) designated by the host device into a physical block address (PBA). Yes. The block management table 81 is a table for recording the number of times of erasure, the writing date and time, and the data holding time of each block constituting the spare area, the refresh area, and the user area.

  Here, the erase count corresponds to a deterioration parameter for estimating the data retention time. The MPU 33 updates the block management table 81 every time the number of deletions increases. The MPU 33 can determine the data holding time for each block based on the erase count and write it in the block management table 81. The data holding time can also be determined by the system based on the number of writes received from the SSD 30. In that case, it is not necessary to record the data holding time in the block management table 81.

  In the flash memory 37, for example, reading and writing are performed with a fixed unit page having a minimum unit of 512 + 16 bytes as a minimum unit. A block can be configured as a collection of any number of pages. The MPU 33 can acquire the calendar time of the RTC memory 23 from the system every time the SSD 30 is powered on. The MPU 33 writes the writing date and time when data is first written in any block constituting each block in the block management table 81.

  The spare area is an alternative storage area when a defective page occurs. The refresh area is an area used as a new write destination block at the time of refresh. The SSD 30 is a boot drive, and user data 97 is stored in the user area in addition to programs such as the OS 91, the application 93, and the refresh manager 95. The refresh manager 95 is an application that performs processing related to refresh.

  The firmware ROM 15 stores system firmware, such as BIOS and UEFI, which mainly performs initialization and authentication of devices at the time of power activation. The system firmware is a program that is always executed first by the reset CPU 11. In the first refresh method and the second refresh method, which will be described later, when power is supplied to the CPU 11 in a standby state for refresh, the system firmware sends a refresh command to the SSD 30 before passing the boot process to the OS 91. Send.

  The EC 40 is a microcomputer including an MPU 41, a ROM 43, a RAM 45, a flash memory 47, a logic circuit 49, and the like. The EC 40 further includes a DMA controller (not shown), an interrupt controller, an SM port connected to the battery unit 60, an SPI port connected to the chip set 20, and the like. The EC 40 operates independently of the CPU 11 and controls the operation of the DC / DC converter 51 according to the power state.

  The EC 40 is connected with a control circuit for the DC / DC converter 51, a power button 53 operated by the user, a lid sensor 55 for detecting opening / closing of the housing, a timer 57, and a charger 58, and further with an SM bus 62 and a side. A battery unit 60 is connected by a band 64. The ROM 43 includes codes for determining the disappearance time for the MPU 41 to refresh and for controlling the activation of the power source. The flash memory 47 stores a refresh management table 83 shown in FIG.

  The refresh management table 83 records the disappearance time or remaining time for each block number. The MPU 41 receives the writing date / time and the data holding time for each block number stored in the block management table 81 from the SSD 30 every time the system transitions to the standby state, and disappears based on the calendar time stored in the RTC memory 23. The time can be calculated and stored in the refresh management table 83.

  When the MPU 41 cannot receive the data retention time from the SSD 30, the MPU 41 may receive the refresh management table 85 indicating the relationship between the erase count and the data retention time through the refresh manager 95 and store it in the flash memory 47 in advance. it can. The refresh management table 85 is provided by a flash memory or SSD manufacturer. In this case, the MPU 41 receives the write date / time and the erase count for each block number stored in the block management table 81 from the SSD 30 and extracts the data retention time from the refresh management table 85 every time immediately before the system transitions to the standby state. Thus, the disappearance time can be calculated based on the calendar time stored in the RTC memory 23.

  The EC 40 is in a standby state and power is stopped except for the logic circuit 49. The timer 57 consumes less power than the EC 40. In the first refresh method, the timer 57 always supplies power for use in a standby state. The MPU 41 sets an operation time in the timer 57 immediately before entering the standby state. The timer 57 measures the operation time set by the MPU 41 in the standby state and outputs a time-up signal to the logic circuit 49. In the first refresh method, the logic circuit 49 receives the time-up signal of the timer 57 in the standby state, controls the DC / DC converter 51, supplies power to the EC 40, and wakes up. When the accuracy of the timer 57 cannot be ensured sufficiently, the EC 40 can calibrate the timer 57 using the system clock before transitioning to the standby state.

  In the second refresh method, the logic circuit 49 can wake up the EC 40 by controlling the DC / DC converter 51 when receiving a wake-up signal from the battery unit 60 through the sideband 64 in the standby state. Further, in the second refresh method, the logic circuit 49 can wake up the EC 40 by controlling the DC / DC converter 51 when receiving a wake-up signal from the RTC wake-up circuit 24 in the standby state.

  The logic circuit 49 detects the depression of the power button 53 or the operation of the lid sensor 55 in the standby state, controls the DC / DC converter 51, and shifts the notebook PC 10 to the power-on state. The DC / DC converter 51 receives power supplied from the battery unit 60 or an AC / DC adapter (not shown) and converts it into a plurality of stable voltages. The DC / DC converter 51 is divided into a plurality of systems so as to correspond to the power state, and supplies power to each device of the notebook PC 10 including the SSD 30. The MPU 41 acquires data related to the charging state of the battery cell 69 from the MPU 61 through the SM bus, and controls the operation of the charger 58. The charger 58 charges the battery unit 60 with power supplied from the AC / DC adapter.

  The battery unit 60 supplies power to the DC / DC converter 51 when the AC / DC adapter is not connected. The battery unit 60 includes an MPU 61, a protection circuit 63, a ROM 65, a timer 67, a battery cell 69, an input / output circuit 71 serving as a charge / discharge path for the battery cell 69, and the like. The battery unit 60 may be built in the notebook PC 10 or may be installed in the battery bay as a battery pack. The battery unit 60 is connected to the refresh terminal 39 via the side band 38.

  The ROM 65 includes a code that wakes up the EC 40 through the sideband 64 when the remaining time comes in the second refresh method. The ROM 65 includes a code for setting the refresh terminal 39 through the side band 38 when the remaining time comes in the third refresh method. The EC 40 serves as a bus master and periodically communicates with the battery unit 60 to monitor the state of the battery cell 69 such as the voltage, remaining capacity, and cell temperature and set the charging parameters in the charger 58.

[First refresh method]
FIG. 4 is a flowchart for explaining a procedure for the notebook PC 10 to execute the first refresh method. In block 101, the notebook PC 10 has transitioned to the power-on state, and the CPU 11 writes data to the SSD 30. The MPU 33 of the SSD 30 can acquire the time information timed by the RTC 21 at the time of power-on and anytime thereafter from the system and can measure the elapsed time internally and generate the time information while the power is on. The SSD 30 can hold data using a known retention check during the power-on state.

  In block 103, every time any block is erased, the MPU 33 updates the block management table 81 so that the number of times of erasure for the block is increased by one. Block erasure occurs by writing new data, retention check, refresh or wear leveling. The MPU 33 records in the block management table 81 the date and time when data was first written on any page included in the erased block as the write date and time.

  If the MPU 33 can extract the data retention time from the number of erases, the MPU 33 updates the data retention time of the block stored in the block management table 81 as necessary when the erase count of any block is updated. In block 105, a standby event for transitioning to the standby state is generated and notified to the OS 91 by pressing of the power button 53, operation of the lid sensor 55, operation of a keyboard (not shown), or elapse of a set idle time.

  The OS 91 sends a standby event to the running application 93, the refresh manager 95, the device driver, and the EC 40. The EC 40 that has received the standby event in block 107 interrupts the CPU 11 and requests the refresh manager 95 to acquire basic data for calculating the lost time or remaining time stored in the block management table 81 from the SSD 30. To do. When the block management table 81 stores the data holding time, the refresh manager 95 acquires the block number, the writing date / time and the data holding time corresponding to the block number as basic data.

  When the block management table 81 does not store the data holding time, the refresh manager 95 acquires the block number, the number of erasures corresponding to the block number, and the writing date / time as basic data. In block 109, the MPU 41 stores the basic data received from the refresh manager 95 in the flash memory 47 as necessary. The MPU 41 updates the refresh management table 83 by calculating the disappearance time or remaining time from the writing date and time and the data holding time for each block number. When the MPU 41 does not receive the data holding time from the SSD 30, the MPU 41 refers to the refresh management table 85 to calculate the data holding time based on the number of erasures and then calculates the disappearance time or remaining time for each block number.

  At this time, the system power supply is still maintained, but when transitioning to the standby state, the power supply of the CPU 11 and the SSD 30 is stopped, and power is supplied only to the minimum devices corresponding to the respective power states. Since the SSD 30 whose power is stopped cannot measure the elapsed time, the lost time or the remaining time cannot be managed. In order to prevent the data loss of the flash memory 37, the host device needs to manage the remaining time instead of the SSD 30, but it is not preferable that the power consumption increases in the standby state. It is also desirable to minimize hardware changes.

  The MPU 41 extracts the block having the earliest disappearance time (shortest remaining time) in the updated refresh management table 83 and sets the refresh flag. The refresh flag may be set for a plurality of blocks extracted in order of the disappearance time. In block 111, the MPU 41 requests the MPU 61 of the battery unit 60 to time the elapsed time from the current calendar time. Alternatively, the MPU 41 requests to count the remaining time calculated from the current calendar time and disappearance time. Further, the MPU 41 can set a time until the EC 40 wakes up in the timer 57 in order to monitor the remaining time as necessary.

  The EC 40 causes the battery unit 60 to start measuring the elapsed time, sets the timer 57 as necessary, and notifies the OS 91 of the completion of preparation for the standby state. When the OS 91 confirms that all hardware and programs are ready for the transition to the standby state, it instructs the EC 40 in block 113 to stop the power supply of the device according to the power state of the transition destination and wait for the system. Transition to a state.

  The MPU 61 of the battery unit 60 operates the timer 67 to measure the elapsed time since the transition to the standby state. Even in the standby state, the remaining capacity of the battery cell 69 decreases due to spontaneous discharge. Even when the system is in a standby state, the battery unit 60 needs to manage the charge state of the battery cell 69 and request the EC 40 to charge as necessary. Since the battery cell 69 supplies power to the MPU 61 and the protection circuit 63 even in a standby state, the power consumption of the battery unit 60 hardly increases in order to measure the disappearance time.

  The EC 40 needs to be charged by operating the charger 58 when the remaining capacity of the battery cell 69 decreases during the standby state. The timer 57 periodically wakes up the EC 40 by sending a time-up signal so that the MPU 41 can communicate with the MPU 61 and check the remaining capacity of the battery cell 69 in the standby state. When the EC 40 wakes up to check the remaining capacity in block 115, the elapsed time after the transition to the standby state measured by the battery unit 60 in block 117 or the remaining time of the remaining time is checked to refresh. Determine the need. If the fixed period to wake up to confirm the remaining capacity cannot be used as a period to manage the need for refresh, the EC 40 first set the timer 57 in block 111 to confirm the remaining time. It can wake up in operation time.

  In block 117, when the EC 40 determines that the earliest disappearance time for which the refresh flag is set in the refresh management table 83 has not arrived, it sets a new time until wakeup in the timer 57 as necessary. After that, the power supply is stopped and the process returns to block 113. The time until the new wake-up may be set to be shorter as the remaining time decreases, or may be constant. When the EC 40 determines that the disappearance time has come, it controls the DC / DC converter 51 in block 119 to supply power to a predetermined device. At this time, the EC 40 sets a flag for notifying the system firmware that the cause of the reset of the CPU 11 is refresh in the flash memory 47.

  It is desirable to keep the given device within the minimum range necessary for sending a refresh command to the SSD 30. Accordingly, power is supplied to the CPU 11, the system memory 13, the firmware ROM 15, a part of the chip set 20, and the SSD 30, but it is not necessary to supply power to a display, an audio device, and a communication device (not shown). .

  When the power is turned on, the reset CPU 11 loads the system firmware into the system memory 13 and executes it. The system firmware checks the flag indicating the cause of resetting the flash memory 47 after initializing the necessary devices in block 121. The system firmware stops access to the SSD 30 from itself and the firmware application without loading the OS. In block 123, the system firmware sends a refresh command to the SSD 30 via the serial bus 32 and waits for a refresh completion notification from the SSD 30. The refresh command is a unique command defined in the present embodiment.

  Since the system firmware can stop access to the SSD 30 and send a refresh command before the OS boots, the SSD 30 can start refreshing in a short time after the power is turned on. The refresh command may be sent by the refresh manager 95 after the notebook PC 10 has been booted, but access to the SSD 30 cannot be stopped while the OS is booting, and the OS Since it takes a long time to complete the boot, it is beneficial that the refresh command is sent by the system firmware in terms of standby power and time to completion of the refresh.

  The system firmware refers to the refresh management table 83 and sets the block number of the block for which the refresh flag is set in the refresh command parameter. Further, the system firmware may set a parameter to refresh all blocks in which data is written in the refresh command. In block 125, the MPU 33 executes a refresh command to refresh the specified block or all blocks.

  The refreshed SSD 30 updates the block management table 81 and notifies the system firmware of the refresh completion in block 127. The system firmware instructs the EC 40 to return the system to the standby state again without passing the boot process to the OS. In the above procedure, the clocking operation by the timer 57 and the clocking operation by the battery unit 60 hardly increase the power consumption in the standby state.

  Further, the EC 40 can monitor the elapsed time measured by the battery unit 60 through the SM bus 62, and the system firmware can send a refresh command to the SSD 30 through the serial bus 32. Therefore, the hardware needs to be changed. Absent. Furthermore, since the system firmware sends a refresh command, the power consumed by the system for refreshing can be kept to a minimum range. In the block 115, the example in which the elapsed time measured by the battery unit 60 is monitored has been described. However, when the EC 40 wakes up, the calendar time is acquired through the RTC wake circuit 24, and the lost time is determined by referring to the refresh management table 83. The arrival can also be judged.

[Second refresh method]
In the first refresh method, when the EC 40 temporarily wakes up with the timer 57 and confirms the remaining time counted by the battery unit 60 or the calendar time of the RTC wake circuit 24, there is no need for refresh, and the standby state is again entered. There is a lot of back movement. The second refresh method is the same as the first refresh method in that the system firmware sends a refresh command via the serial bus 32. However, the refresh can be performed without causing the timer 40 to wake up the EC 40 in the standby state. Wake up only when necessary.

  In one aspect of the second refresh method, a sideband 64 newly provided between the EC 40 and the battery unit 60 is used. The procedure of the second refresh method is performed instead of the procedure from block 111 to block 117 in FIG. The EC 40 sets the remaining time until the disappearance time in the battery unit 60 and then shifts the system to a standby state and stops the power supply of the EC 40. During the standby state, the EC 40 does not wake up with the timer 57 to confirm the need for refresh.

  When the set remaining time arrives, the MPU 61 sends a wakeup signal to the logic circuit 49 via the sideband 64 to wake up the EC 40. The subsequent steps are the same as the steps after block 119 in FIG. In this case, the standby power does not increase because the EC 40 wakes up unnecessarily. In another aspect of the second refresh method, the EC 40 sets the disappearance time in the RTC memory 23 before transitioning to the standby state. When the set time arrives in the standby state, the RTC wakeup circuit 24 wakes up the EC 40 at the set disappearance time. In this case, even when the RTC wakeup function is disabled, it is necessary to supply power to the RTC wakeup circuit in a standby state, but it is not necessary to change the hardware.

[Third refresh method]
Since both the first refresh method and the second refresh method are refreshed by sending a refresh command to the SSD 30, the SSD 30 can be realized only by changing the firmware. However, when the refresh command is sent, it is necessary to supply power to the CPU 11, the system memory 13, the chip set 20, and the like. In the third refresh method, a refresh signal is sent through the sidebands 34 and 38 instead of the refresh command. The SSD 30 is provided with a refresh terminal 39 that is set by a refresh signal. The procedure of the third refresh method is performed instead of the procedure from block 111 to block 119 in FIG.

  In the third refresh method, the elapsed time or disappearance time is measured while the battery unit 60 or the RTC wake circuit 24 is in the standby state, as in the second refresh method. When the disappearance time comes, the EC 40 is woken up. Unlike the first refresh method and the second refresh method, the EC 40 supplies power only to the SSD 30 by operating the DC / DC converter 51. Subsequently, the battery unit 60 or the RTC wake circuit 24 sends a refresh signal via the side band 38 or the side band 34 to set the refresh terminal 39. The MPU 33 refers to the refresh terminal 39 and executes the refresh of the SSD 30 that is powered on.

  So far, the method for refreshing the flash memory 37 mounted on the SSD has been described. However, the present invention is applied to other flash memories in which the elapsed time from the write time cannot be measured when the system is in a standby state. You can also. As an example, the present invention can be applied to an HDD cache memory. In HDD write-back caching, data exists only in the flash memory when writing is completed.

  Data stored in the flash memory is written to the HDD at a timing based on a predetermined algorithm when the system is in an idle state. When write-back caching is used for flash memory that has deteriorated, the loss time tends to elapse when data stored in the flash memory is written to the flash memory and then transitions to the standby state. It is effective to refresh the cache before data is lost by applying the present invention.

  The cache memory in this case may be built in the HDD or provided outside. When the cache memory is provided outside the HDD and connected to the chip set 20 through an independent interface, the cache controller built in the chip set 20 can perform refreshing. Further, the NAND type flash memory has been described as an example, but the present invention can also be applied to a NOR type flash memory. Further, the present invention can be applied to a general nonvolatile memory such as an EPROM or a ferroelectric memory that needs to be refreshed in order to hold data of a cell whose deterioration has progressed. Furthermore, the present invention can be applied not only to a computer but also to all host devices that are connected to a flash memory and transition to a standby state.

  Although the present invention has been described with the specific embodiments shown in the drawings, the present invention is not limited to the embodiments shown in the drawings, and is known so far as long as the effects of the present invention are achieved. It goes without saying that any configuration can be adopted.

10 Notebook PC
30 Solid State Drive (SSD)
40 Embedded Controller (EC)
60 Battery unit 34, 38, 64 Side band 39 Refresh terminal 37 Flash memory 81 Block management table (stored in SSD)
83, 85 Refresh management table (stored in EC)

Claims (17)

A computer capable of transitioning to a standby state,
An interface capable of connecting a storage device including a nonvolatile memory and a controller that receives a refresh command and refreshes the nonvolatile memory; and
A timing unit that counts the elapsed time from the transition to the standby state in which the power of the storage device is stopped to the disappearance time at which the data stored in the nonvolatile memory is lost;
A power supply controller that monitors the elapsed time during the standby state and determines that the disappearance time has arrived, and powers on the storage device and a circuit necessary for sending the refresh command; ,
A computer having a command sending unit for sending the refresh command to the storage device through the interface before the operating system is loaded after the power is turned on;   The computer of claim 1, wherein the storage device is a solid state drive that stores an operating system.   The computer of claim 1, wherein the non-volatile memory is a hard disk drive cache. A computer capable of transitioning to a standby state,
An interface capable of connecting a storage device including a nonvolatile memory and a controller that receives a refresh command and refreshes the nonvolatile memory; and
A timing unit that counts the elapsed time from the transition to the standby state in which the power of the storage device is stopped to the disappearance time at which the data stored in the nonvolatile memory is lost;
When it is determined that the disappearance time has arrived by monitoring the elapsed time measured by the timing unit by wakeup at a predetermined timing during the standby state when the power is turned off A power control unit for turning on power to the storage device and a circuit necessary for sending the refresh command;
A computer having a command sending unit for sending the refresh command to the storage device through the interface; A computer capable of transitioning to a standby state,
An interface capable of connecting a storage device including a nonvolatile memory and a controller that receives a refresh command and refreshes the nonvolatile memory; and
Controls charging / discharging of the battery that supplies power to the computer so as to measure the elapsed time from the transition to the standby state in which the power of the storage device is stopped to the disappearance time at which the data stored in the nonvolatile memory is lost A time measuring unit configured by a control unit of the battery unit
A power supply controller that monitors the elapsed time during the standby state and determines that the disappearance time has arrived, and powers on the storage device and a circuit necessary for sending the refresh command; ,
A computer having a command sending unit for sending the refresh command to the storage device through the interface;   The power supply control unit sets an elapsed time until the disappearance time before the power supply stops when the power supply control unit transitions to the standby state, and the battery unit turns the power supply control unit when the disappearance time arrives. The computer according to claim 5, which is waked up. A computer capable of transitioning to a standby state,
An interface capable of connecting a storage device including a nonvolatile memory and a controller that receives a refresh command and refreshes the nonvolatile memory; and
A real time clock that generates system time information so as to measure the elapsed time from the transition to a standby state in which the power of the storage device is stopped until the data stored in the nonvolatile memory is lost. A timekeeping section composed of a wake-up circuit including
A power supply controller that monitors the elapsed time during the standby state and determines that the disappearance time has arrived, and powers on the storage device and a circuit necessary for sending the refresh command; ,
A computer having a command sending unit for sending the refresh command to the storage device through the interface;   The power supply control unit sets the disappearance time in the wakeup circuit before the power supply is stopped due to transition to the standby state, and the wakeup circuit wakes up the power supply control unit when the disappearance time arrives The computer according to claim 7. A computer capable of transitioning to a standby state,
An interface capable of connecting a storage device including a nonvolatile memory, a refresh terminal, and a controller for refreshing the nonvolatile memory with reference to the refresh terminal;
A timing unit that counts the remaining time from the transition to the standby state in which the power of the storage device is stopped until the data stored in the nonvolatile memory is lost;
A power control unit for turning on the power to the storage device in response to the passage of the remaining time;
A setting unit configured to set the refresh terminal in response to elapse of the remaining time.   The computer according to claim 9, wherein the setting unit sets the refresh terminal via a sideband that does not use the interface.   The computer according to claim 9, wherein the clock unit and the setting unit are configured by a battery unit that supplies power to the computer.   The computer according to claim 9, wherein the clock unit and the setting unit are configured by a wakeup circuit including a real time clock for generating system time information. A computer to which a disk drive including a nonvolatile memory is connected is a method for preventing loss of data stored in the nonvolatile memory,
Transitioning to a standby state in which the computer is powered off in response to a standby event;
Measuring the elapsed time from the transition of the computer to the standby state to the disappearance time at which the data stored in the nonvolatile memory is lost;
In response to the arrival of the disappearance time, turning on power to the circuit and the disk drive necessary for the computer to send a refresh command;
Sending the refresh command to the disk drive after being powered on and before the operating system is loaded;
The disk drive refreshing the non-volatile memory in response to the refresh command.   14. The method of claim 13, wherein the computer obtains information about a write date and time and a data retention time for calculating the disappearance time from the disk drive in response to the standby event. A computer to which a disk drive including a nonvolatile memory and a refresh terminal is connected is a method for preventing the loss of data stored in the nonvolatile memory,
Transitioning to a standby state in which the computer is powered off by the computer;
Measuring the remaining time from the transition of the computer to the standby state until the data stored in the nonvolatile memory is lost;
In response to elapse of the remaining time, turning on the disk drive and setting the refresh terminal;
The disk drive refreshing the non-volatile memory with reference to the refresh terminal. A host device to which a disk drive having a non-volatile memory is connected,
A lost time acquisition unit for acquiring a lost time of data stored in the nonvolatile memory in a power-on state;
A timekeeping unit for measuring the elapsed time since the power to the disk drive was stopped by transitioning to the standby state;
A power supply controller that supplies power to the disk drive when it is determined that the disappearance time has arrived based on the elapsed time;
A host device having an instruction unit for instructing the disk drive to which power is supplied to refresh before the operating system is loaded; A host device to which a disk drive equipped with a nonvolatile memory is connected is a method for preventing the loss of data stored in the nonvolatile memory,
Obtaining a data erasure time stored in the nonvolatile memory when the host device is in a power-on state;
The host device transitions to a standby state to stop the power of the disk drive;
Measuring the elapsed time since the host device stopped powering the disk drive;
Instructing refresh before the operating system is loaded by supplying power to the disk drive when the host device determines that the disappearance time has arrived based on the elapsed time;
And wherein the powered disk drive refreshes the non-volatile memory based on the instructions.

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