JP2002099502A - Computer system and control method for data transfer - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a computer system and a control method for data transfer capable of practicing data transfer with a hard disk drive and speeding up the reconversion from boot processing/hibernation. SOLUTION: A disk driver (INT 13 h) of BIOS checks the operation mode of a CPU 11 on which upper program was operating and judges as if it is virtual address mode or real mode (STEP S101, S102). In case of virtual address mode (V86 mode), BIOS practices data transfer with HDD by PIO transfer mode (STEP S103). And, in case of real mode, BOIS calculates physical memory address with a segment that is set in a CPU register and offset, and sets it as transfer address to a by master IDE controller 16, and practices data transfer with HDD by in a DMA transfer mode (STEP S104).

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a computer system and a data transfer control method used in the computer system, and more particularly to a computer system and a data transfer control improved so that data transfer with a disk device can be efficiently performed. About the method.

[0002]

2. Description of the Related Art In recent years, various portable personal computers of notebook type or sub-note type, and pocket computers such as portable information terminals have been developed.

Such a portable computer is provided with various power save modes for saving the power of the computer system in order to extend the time during which the battery can be driven. The suspend mode is one of the power save modes that consumes the least power. That is, when the computer system is in the suspend mode, most other devices in the system are powered off, except for the main memory in which system data necessary for restarting such as the operating system and user programs is stored.

The system data saved in the main memory is the status of the CPU and the status of various peripheral LSIs immediately before the computer system is set to the suspend mode. The main memory also stores the execution state of the operating system and application programs and user data created by the application programs. The information saved in the main memory is used to restore the work state immediately before the suspend mode.

The saving of the system data is performed by the system BI
It is executed by a suspend routine incorporated in an OS (basic input / output program). The system BIOS is for controlling hardware in the system according to a request from the operating system, and includes a device driver group for controlling various hardware devices in the system. The suspend routine of the system BIOS is started when the power of the system is turned off.
After saving the status of the CPU registers and various peripheral LSIs in the memory, the system is powered off.

[0006] Power to the main memory is maintained by a battery throughout the period when the system is powered off. Therefore, the system can be returned to the work state before the suspension at a high speed without losing the status and user data of the system.

However, if the battery capacity is reduced to a low battery state when the system is in the suspend mode, data in the main memory is lost. In this case, not only cannot the system be returned to the state before the suspension, but also the user data developed in the main memory is lost.

Accordingly, hibernation has recently begun to be used as a new power save mode instead of the suspend mode. Hibernation is a mode in which the status of the CPU and various peripheral LSIs, the contents of the main memory, etc. are saved to the hard disk when the system power is turned off, and then almost all devices in the system including the main memory are powered down. Power consumption can be reduced. Further, even if the battery capacity decreases, the information saved on the hard disk is not lost, so that the system state can be restored to the state immediately before the hibernation process. Therefore, many portable computers that are frequently used on the go, where the AC adapter cannot be used, implement hibernation as a power save mode.

[0009] With the recent improvement in the functions of operating systems and application programs, the memory capacity of a portable computer as a main memory is constantly increasing. As the storage capacity of the main memory increases, the time required to save the contents of the main memory to the hard disk and the time required to restore the contents of the hard disk to the main memory also increase. For this reason, in a system that uses the hibernation mode, the time required for the hibernation process, that is, the time required from the time the user turns off the power switch to the time the system is actually turned off, and the time required after the user turns on the power switch. The time required for the system state to be restored is becoming very large.

Conventionally, a data input / output operation with a hard disk drive via a BIOS is always performed by a PIO.
(Programmed Input / Output) mode.

That is, in a portable computer, ATA (Enhanced IDE) is used as an interface used to connect a hard disk drive. A typical transfer mode used in the Enhanced IDE is the above-described PIO mode. In ATA, PIO modes 0 to 4 are defined, and the maximum transfer rates are different from each other. The PIO mode is a transfer mode using handshaking between the CPU and the hard disk drive, and the CPU transfers data by repeatedly accessing the I / O port of the hard disk drive directly. Therefore, the transfer rate is not high, but this transfer method is sufficient in consideration of the data transfer capability of the hard disk drive itself that requires mechanical operations such as seek operation and spindle rotation.

However, in recent years, the density of hard disks has been rapidly increasing, and the data transfer capability of the hard disks themselves has been greatly improved.
In addition to the current DMA mode, and UltraD
Those having a disk interface compatible with the MA mode have become mainstream. Therefore, the conventional BIOS data transfer method of always performing data input / output with the disk device using only the PIO mode has a problem in that the performance of the disk device cannot be sufficiently brought out.

[0013]

However, if the data transfer is always performed by using the DMA transfer when the disk access routine (INT13h) of the BIOS is called from the host program such as the operating system, the CPU of the CPU at that time is required. Depending on the operating mode, there is a risk of causing a serious error.

That is, when performing a DMA transfer (DMA mode or UltraDMA), the BIOS itself calculates a physical memory address to be a transfer destination / transfer source instead of using the address conversion mechanism of the CPU, and executes the calculation. The bus master I as the source / destination memory address
It is necessary to set in the DMA control logic such as the DE controller. This is because, in the DMA transfer, the memory access is executed not by the CPU but by the DMA control logic such as the bus master IDE controller. However, the physical memory address calculation method is actually CP
U operation mode (real mode, virtual address mode)
Depends on

That is, in the real mode, the segment and the offset are converted into the physical address by the calculation of segment × 16 + offset = physical memory address. In the virtual address mode such as the V86 mode or the protect mode, the descriptor table and the address are converted. It is necessary to refer to the so-called virtual address translation table. A privilege level is required to refer to the descriptor table, and normally, programs (including the BIOS) other than the operating system cannot access it.

Therefore, if the BIOS always performs the segment × 16 + offset = regardless of the operation mode of the CPU.
When the physical memory address is calculated by the calculation of the physical memory address and the process for the DMA transfer is started using the calculated physical memory address, the CPU sets the virtual address mode (for example, V
86 mode), an incorrect physical memory address is calculated, resulting in a malfunction.

SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and enables the execution conditions of the DMA transfer mode to be determined in consideration of the operation mode of the CPU. It is an object of the present invention to provide a computer system and a data transfer control method capable of improving the data transfer efficiency between the computer system and the system.

[0018]

In order to solve the above-mentioned problems, the present invention provides a first operation mode for calculating a physical memory address from a segment and an offset, and a virtual address and virtual address conversion table including the segment and the offset. In a computer system having a CPU having a second operation mode for calculating a physical memory address by using a CPU, when an upper program requests access to a disk device provided in the computer system, Operating mode determining means for determining whether the operating mode is the first operating mode or the second operating mode; and determining that the current operating mode of the CPU is the first operating mode by the operating mode determining means. If determined, the CP
A physical memory address is calculated from the segment and offset set in the U register, and a request is issued from the higher-level program using the calculated physical memory address and the disk address set in another register of the CPU. Disk access control means for executing data transfer to and from the disk device by DMA transfer.

In this computer system, when an access to the disk device is requested from a host program, an operation mode of the CPU at that time is determined, and a first operation mode in which a physical memory address can be directly calculated from a segment and an offset. Is performed, a process for the DMA transfer is executed. Therefore, it is possible to efficiently execute the data transfer between the disk device and the memory without causing a trouble such as calculation of an erroneous physical memory address. It is possible to speed up the bootstrap processing and the recovery processing from hibernation.

The disk access control means, if the current operation mode of the CPU is determined to be the second operation mode by the operation mode determination means,
It is preferable that a data transfer to and from the disk device requested by the host program is executed by a PIO transfer mode in which the CPU repeatedly executes access to the disk device. This makes it possible to selectively execute the DMA transfer mode and the PIO transfer mode according to the current operation mode of the CPU, and to always use the optimum transfer mode.

[0021]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows a configuration of a computer system according to an embodiment of the present invention. This computer system is a portable personal computer of a notebook type or a sub-note type, and is composed of a computer main body and an LCD panel unit which is openably and closably attached to the computer main body. This computer has a built-in battery, and is configured to be operable with power from the built-in battery. Further, power can be supplied from an external power supply such as an AC commercial power supply via an AC adapter. When power is supplied from an external power source, the power from the external power source is used as an operating power source for the computer system. At this time, the built-in battery is automatically charged by the power from the external power supply. When the AC adapter is removed or the breaker of the AC commercial power supply is turned off, the power from the built-in battery is used as the operation power supply of the computer system.

Also, a hard disk drive (HD) having an IDE interface is provided in the computer main body.
D) 17 is detachably mounted. This HDD
Reference numeral 17 is used as secondary storage of a computer.

On the system board of the computer, a CPU 11, a host-PCI bridge 12, a main memory 13, a VGA controller 14,
A PCI-ISA bridge 15, a bus master IDE controller 16, a BIOS-ROM 18, an embedded controller (EC) 20, a power supply controller (PSC) 21, and the like are provided.

The CPU 11 controls the operation of the entire system and executes data processing. The CPU 11 supports a memory segmentation mechanism and a virtual addressing mechanism, such as a microprocessor “Pen” manufactured and sold by Intel Corporation.
for example. In this case, the CPU 11
Has the following operation.

That is, the CPU 11 operates as a real mode, a protect mode, and a virtual 8086 mode (V8) as operation modes for executing programs such as an application program and an operating system (OS).
6 modes). The real mode is a real address mode using memory segmentation, and the protect mode and the virtual 86 mode are virtual address modes.

That is, the real mode is a mode in which a memory space of a maximum of 1 Mbyte can be accessed, and the conversion from the logical address to the physical address is determined by the offset value from the base address represented by the segment register. This is done according to the address calculation format. In other words, as shown in FIG.
A 16-bit value (sometimes referred to as a selector) that virtually represents a segment. The physical memory address is a base address obtained by shifting the value of the segment to the left by 4 bits (16 times), and the 16-bit value. It is calculated by adding the represented offset value.

On the other hand, the protect mode is a mode in which a memory space of a maximum of 4 GB can be accessed per task, and a linear address is determined using a virtual address conversion table called a descriptor table. This linear address is finally converted to a physical address by paging. That is, as shown in FIG. 3, the segment value is used as a pointer for referring to the descriptor table, the value obtained from the descriptor table is used as the base address, and the offset value represented by 16 bits is used as the base address. The linear address is calculated by the addition. The V86 mode is an operation mode for emulating the real mode in a protected mode environment, and uses the same virtual address calculation method as the protected mode.

The operation mode at the time of initialization of the CPU 11 is a real mode, and is switched to a protect mode and a V86 mode under software control of an operating system or the like.

The host-PCI bridge 12 is a bridge for connecting the CPU bus 1 and the PCI bus 2 in two directions.
Here, a memory controller for controlling the main memory 13 is also incorporated. The main memory 13 is used as a main memory of the system, that is, a system memory, and stores an operating system, an application program to be processed, user data created by the application program, and the like. The main memory 13 is realized by a semiconductor memory such as a DRAM.

The BIOS-ROM 18 stores a system BIOS.
This is for storing S (Basic I / O System), and is constituted by a flash memory so that a program can be rewritten. System BI
The OS is a systematized function execution routine for accessing various hardware in the system, and is configured to operate in a real mode. The system BIOS includes a processing routine for bootstrapping the operating system when the system is powered on, and a group of BIOS drivers for controlling various hardware. Each BIOS driver includes a plurality of function execution routine groups corresponding to the functions for providing a plurality of functions for hardware control to an operating system or an application program. When the upper program calls INT13h, the hard disk driver of the BIOS is executed. This driver (INT13
h) includes a function for performing data transfer with the HDD 17 by DMA transfer and a function for performing data transfer by PIO transfer.

The EC 20 is a controller for controlling additional functions of the system. The EC 20 has a heat control function for controlling the rotation of a cooling fan according to the temperature around the CPU and the like. It has an LED / beep sound control function for notifying a user with a beep sound, a power supply sequence control function for controlling on / off of the system power supply in cooperation with the power supply controller 21, a power supply status notification function, and the like.
Even in the hibernation state, the operating power is supplied to the EC 20 and the power controller 21, and the on / off of the power switch 22 and the panel switch 23 is monitored.

Hibernation occurs when a transition event to the power save mode such as system power off occurs.
In this mode, almost all devices in the system including the main memory 17 are powered down after the status of the U11 and various peripheral LSIs, the contents of the main memory 13, and the like are saved in the hard disk 17. When a wake-up event such as a system power-off occurs in the hibernation state, the memory image saved on the hard disk 17 is restored to the main memory 13, and the work state before the hibernation is restored.
The control of hibernation execution and return processing is ACP
It is executed under the management of an OS compatible with I (Advanced Configuration and Power Interface).

The VGA controller 14 controls an LCD and an external CRT used as a display monitor of the system, and displays screen data drawn on the VRAM on one or both of the LCD and the external CRT.

The bus master IDE controller 16 controls an IDE device (here, the HDD 17) mounted on the computer main body.
It has a bus master function (DMA controller) capable of executing DMA transfer between the device and the main memory 13. This bus master function performs a bus cycle (DMA) for data transfer by itself in response to a command from the CPU 11.
Transfer), and the CP is higher than in the PIO mode.
With the U load reduced, the IDE device and main memory 1
3 can be performed at high speed.

Next, the disk access operation of the BIOS will be described with reference to FIG.

In this case, a host computer such as an operating system sends a BIOS disk driver (I
NT13h) is assumed to be called. INT1
The BIOS call of 3h is realized by using a software interrupt function of the CPU 11. In this case, the upper level program sends the BIOS disk driver (INT13
h), the following I / O through the register of the CPU 11
The parameter is notified.

R / W Function: Number of transfer sectors indicating disk read or disk write: Number of sectors to transfer data to / from disk device Segment: 16-bit segment value described above Offset: 16-bit offset value described above HDD Address: Start address at which disk access is to be performed Drive number: Drive number of the disk device to be accessed The upper program includes these R / W functions, number of transfer sectors, segments, offset, HDD address
Set the drive numbers to the AH register and A
L register, ES register, BX register, CX / DH
After setting to the register, DL register, etc., INT
Call 13h. As a result, control is transferred to the BIOS disk driver (INT13h).

The BIOS disk driver (INT13
h) First, the CPU 1 on which the host program was running
1 is checked, that is, the current operation mode of the CPU 11 is determined, and it is determined whether the operation mode is the virtual address mode or the real mode (steps S101 and S10).
2). As described above, the BIOS is configured to operate in the real mode.
IOS calls are made in real mode or V86 mode. Therefore, by checking whether or not the V86 flag of the status register in the CPU 11 is on, it is possible to determine whether the mode is the virtual address mode or the real mode.

In the virtual address mode, that is, in the V86 mode, the BIOS disk driver (INT13
h) shows the case in which the CPU 11 repeatedly accesses the HDD 17 by using the PIO transfer mode.
Data transfer with D17 is executed (step S10).
3).

On the other hand, if the mode is the real mode, the BIOS disk driver (INT13h) executes data transfer with the HDD 17 in the DMA transfer mode (step S104). In this case, the BIOS disk driver (INT13h) first calculates the physical memory address from the value of the offset of the BX register and the segment of the ES register (segment × 16 + offset =
Physical memory address), and calculate the physical memory address. Then, the BIOS disk driver (I
NT13h) has its physical memory address and CX / D
The HDD address set to H is set to the bus master IDE controller 16 as the initial value of the transfer source / destination address, and the number of transfer sectors of the AL register is set to the bus master IDE controller 16 as the data transfer width. Thereby, the bus master ID
The E controller 16 starts the DMA transfer. For example, in the case of a disk read from the disk to the main memory 13, the bus master IDE controller 16 reads data in order from the sector data at the position specified by the HDD address, and specifies the read data by the physical memory address. A bus cycle for writing data from the memory addresses of the main memory 13 is sequentially executed.

FIG. 5 shows an example of processing when the data transfer mode is determined in consideration of not only the virtual address mode but also the transfer mode supported by the HDD 17.

That is, the BIOS disk driver (IN
T13h) First, C in which the upper-level program was operating
The operation mode of the PU 11, that is, the current operation mode of the CPU 11 is checked, and it is determined whether the operation mode is the virtual address mode or the real mode (steps S101 and S101).
102). Up to this point, it is the same as FIG.

In the virtual address mode, that is, the V86 mode, the BIOS disk driver (INT13
h) indicates that the HDD 17 reads / writes based on the drive parameter information read from the HDD 17.
It is determined whether a Multiple command is supported (step S201), and based on the result,
The data transfer using the Read / Write Multiple command or the Read / Write Sector command is executed (step S202). Re
ad / Write Multiple is a command that can collectively specify read / write for a plurality of sectors.
If the Read / Write Multiple command is not supported, the Read / Write command specifying read / write in a single sector unit is used for HDD access.
A data transfer mode using a Write Sector command is used. Read / Write Multi
iple and Read / Write Sector
Are the PIO transfer modes.

In the real mode, the disk driver (INT 13 h) of the BIOS reads the HDD 17 based on the drive parameter information read from the HDD 17.
It is determined whether or not 17 supports DMA (step S204). H if not supported
For DD access, the aforementioned Read / Write Mul
Use the tiple command. If DMA is supported, it is next determined whether Ultra DMA is supported (step S205). If not supported, DMA access
Use the read / write command (step S2)
07). If supported, Ultra DMA
A Read / Write command is used (step S208). DMA Read / Write command,
Both the Ultra DMA Read / Write command and the Ultra DMA Read / Write command are commands for the aforementioned DMA transfer.

Many HDDs are Read / Write M
multiple and UltraDMA Read / W
support write, the number of transfer sectors is 2
Above, actually, in virtual address mode, Re
P by ad / Write Multiple command
IO transfer is executed, and in real mode, UltraDM
A DMA transfer using the A Read / Write command is executed.

The data transfer rate is Ultra DMA
Read / Write is highest, then DMA
Read / Write, Read / Write Mul
type, then Read / Write Sector.

Next, referring to FIG.
That is, the operation when bootstrapping the operating system (OS) will be described.

When the system is powered on by turning on the power switch 22, the BIOS uses the disk driver (INT 13h) to read the contents of the MBR (Master Boot Record) of the HDD 17 into the main memory 13. Perform disk access. The MBR includes a master boot code for reading a boot code (OS loader) from the active partition, and control is passed to the master boot code.
The master boot code stores the OS in a register of the CPU 11.
After setting the parameters required for loading the loader,
Call the disk driver (INT13h) of the IOS. The disk driver (INT13h) executes the disk read specified from the master boot code, and
The OS loader is read into the main memory 13. Thereafter, control is passed to the OS loader. The OS loader sets parameters necessary for reading the kernel in the register of the CPU 11, and then calls the disk driver (INT13h) of the BIOS.

The disk driver (INT13h)
The disk read specified by the S loader is executed to read the kernel into the main memory 13. Thereafter, control is passed from the OS loader to the kernel. The kernel reads the various drivers by using the BIOS disk driver (INT1).
3h), the switching from the real mode to the protect mode is performed in the middle. When calling the disk driver (INT13h) of the BIOS, the V86 mode is used. Disk driver (I
NT13h) is called from real mode to V
Until switching to the 86 mode, all data transfer between the disk device and the memory by the disk driver (INT13h) is performed by DMA transfer. After switching to the V86 mode, disk access in the PIO mode is performed. This makes it possible to speed up the bootstrap sequence of the OS as compared with the case where the disk driver (INT13h) always accesses the disk in the PIO mode.

Next, with reference to FIG. 7, an operation when returning from the hibernation state will be described.

When a wake-up event such as turning on of the power switch 22 occurs, the BIOS uses the disk driver (INT 13h) to execute the MBR operation of the HDD 17.
A disk access for reading the contents of (Master Boot Record) into the main memory 13 is performed. The MBR includes a master boot code for reading a boot code (OS loader) from the active partition, and control is passed to the master boot code. The master boot code sets parameters necessary for reading the OS loader in the register of the CPU 11, and then calls the BIOS disk driver (INT13h). The disk driver (INT13h) reads the OS loader into the main memory 13 by executing a disk read specified by the master boot code. Thereafter, control is passed to the OS loader. The OS loader determines whether the process is a return from hibernation or a normal bootstrap. This determination can be made, for example, by storing a flag indicating the shift to the hibernation state in the OS or a register of the EC 20 and referring to the flag when executing the OS loader.

In the case of returning from hibernation, the OS loader stores the HDD 1 in the register of the CPU 11.
After setting the parameters necessary for reading the memory image saved in step 7, the disk driver (INT13h) of the BIOS is called. The disk driver (INT13h) reads the memory image into the main memory 13 by executing the disk read specified by the OS loader. At this time, since the CPU 11 is still in the real mode, the transfer of the memory image from the HDD 17 to the main memory 13 is executed at high speed by DMA transfer. Thereafter, the OS executes processing necessary for restoring the state of each main device, thereby restoring the work environment before the transition to hibernation.

As described above, according to the present embodiment, when the disk I / O operation is requested from the higher-level program, C
By selectively switching and executing the DMA transfer and the PIO transfer according to the operation mode of the PU 11, the data transfer between the disk device and the memory can be efficiently performed without causing a trouble such as calculation of an incorrect physical memory address. It is possible to execute well. In particular, when returning from hibernation, by using the Ultra DMA Read / Write command capable of transferring a large amount of memory image data at high speed, compared with the case using PIO,
The time required to read the memory image data can be greatly reduced.

[0054]

As described above, according to the present invention,
It is possible to sufficiently improve the data transfer efficiency with the disk device without impairing the reliability of the operation.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of a computer system according to an embodiment of the present invention.

FIG. 2 is an exemplary view for explaining a physical address calculation method when the CPU is in a real mode in the embodiment.

FIG. 3 is an exemplary view for explaining a physical address calculation method when the CPU is in a protect mode in the embodiment;

FIG. 4 is an exemplary flowchart for explaining a disk access operation executed in the embodiment.

FIG. 5 is an exemplary flowchart for explaining a second example of the disk access operation executed in the embodiment;

FIG. 6 is an exemplary flowchart for explaining a bootstrap operation of the operating system in the embodiment.

FIG. 7 is an exemplary flowchart for explaining a return operation from hibernation in the embodiment.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 11 ... CPU 12 ... Host-PCI bridge 13 ... Main memory 16 ... Bus master IDE controller 17 ... HDD 18 ... BIOS-ROM

Claims (9)

[Claims] 1. A first operation mode for calculating a physical memory address from a segment and an offset, and a second operation mode for calculating a physical memory address using a virtual address including the segment and an offset and a virtual address conversion table. In a computer system having a CPU having, when access to a disk device provided in the computer system is requested from a higher-level program,
Operating mode determining means for determining whether the current operating mode of the CPU is the first operating mode or the second operating mode; and determining whether the current operating mode of the CPU is the first operating mode by the operating mode determining means. When it is determined that the operation mode is set, the physical memory address is calculated from the segment and the offset set in the register of the CPU, and the calculated physical memory address and the CPU are calculated.
Disk access control means for executing, by DMA transfer, data transfer to and from the disk device requested by the higher-level program using a disk address set in another register of Computer system. 2. The disk access control means, when the operation mode determination means determines that the current operation mode of the CPU is the second operation mode, repeatedly executes the access to the disk device by the CPU. 2. The computer system according to claim 1, further comprising means for executing data transfer to and from said disk device requested by said higher-level program according to the PIO transfer mode to be performed. 3. The system according to claim 1, further comprising a DMA transfer unit for performing a DMA transfer between the disk device and a memory of the computer system, wherein the disk access control unit is configured to calculate the physical memory address and another of the CPU. The method according to claim 1, wherein a disk address set in a register is set in the DMA transfer means, thereby causing the DMA transfer means to execute data transfer with the disk device requested by the upper-level program. 2. The computer system according to 1. 4. The DMA transfer means is a disk control device having a bus master function, and a DMA transfer between the disk device and the memory via the disk control device.
The computer system according to claim 3, wherein the transfer is performed. 5. The disk drive according to claim 1, wherein the host program is an operating system, and the operating system switches the operation mode of the CPU from the first operation mode to the second operation mode during the bootstrap sequence. The access control means executes, by DMA transfer, data transfer for reading a group of files constituting the operating system from the disk device in response to a request from the operating system during the bootstrap sequence. The computer system of claim 1, wherein 6. The contents of the main memory of the computer system are saved in a disk device of the system in the power save mode, and the memory image saved in the disk device is written in the main memory at the time of waking up from the power save mode. In a computer system having a hibernation function for restoring, a first operation mode for calculating a physical memory address from a segment and an offset, and a second operation mode for calculating a physical memory address using a virtual address and a virtual address conversion table including the segment and the offset. A CPU having two operation modes, and when a higher-level program requests restoration of the memory image, which of the first operation mode and the second operation mode is the current operation mode of the CPU? Operating mode determining means for determining, and when the current operating mode of the CPU is determined to be the first operating mode by the operating mode determining means, a physical value is obtained from the segment and offset set in a register of the CPU. Calculating a memory address, and calculating the calculated physical memory address and the CPU
And a disk access control means for executing a restore of the memory image requested by the upper-level program by DMA transfer using a disk address set in another register of the computer system. 7. The system according to claim 1, further comprising a DMA transfer unit configured to execute a DMA transfer between the disk device and a memory of the computer system, wherein the disk access control unit is configured to determine the calculated physical memory address and another of the CPU. 7. The computer according to claim 6, wherein a disk address set in a register is set in said DMA transfer means, thereby causing said DMA transfer means to execute restoration of said memory image requested by said higher-level program. system. 8. A first operation mode for calculating a physical memory address from a segment and an offset, and a second operation mode for calculating a physical memory address using a virtual address including the segment and an offset and a virtual address conversion table. A data transfer control method applied to a computer system having a CPU having the above method, wherein an access to a disk device provided in the computer system is requested from a higher-level program,
An operation mode determining step of determining whether the current operation mode of the CPU is the first operation mode or the second operation mode; and the operation mode determination step determines that the current operation mode of the CPU is the first operation mode. When it is determined that the operation mode is set, the physical memory address is calculated from the segment and the offset set in the register of the CPU, and the calculated physical memory address and the CP are calculated.
U using the disk address set in another register of U to transfer data to and from the disk device
Executing the data transfer by A-transfer. 9. A first operation mode for calculating a physical memory address from a segment and an offset, and a second operation mode for calculating a physical memory address using a virtual address including the segment and an offset and a virtual address conversion table. A data transfer control method for restoring the contents of the main memory saved in the disk device during the power save mode from the disk device to the main memory when waking up from the power save mode, comprising: When a higher-level program requests restoration of a memory image saved in a disk device, the CPU
An operation mode determining step of determining whether a current operation mode of the CPU is the first operation mode or the second operation mode; and the current operation mode of the CPU is determined to be the first operation mode by the operation mode determination step. Is determined, a physical memory address is calculated from the segment and the offset set in the register of the CPU, and the calculated physical memory address and the CP are calculated.
Using the disk address set in another register of U to restore the memory image requested by the host program by DMA transfer.