CN104808769B

CN104808769B - A kind of low-power consumption FPGA device

Info

Publication number: CN104808769B
Application number: CN201510192294.7A
Authority: CN
Inventors: 朱璟辉
Original assignee: Guangdong High Cloud Semiconductor Technologies Ltd Co
Current assignee: Guangdong High Cloud Semiconductor Technologies Ltd Co
Priority date: 2015-04-21
Filing date: 2015-04-21
Publication date: 2017-11-17
Anticipated expiration: 2035-04-21
Also published as: CN104808769A

Abstract

The present invention discloses a kind of low-power consumption FPGA device, including user-defined programmed logical module and SRAM memory, programmed logical module is provided with core power pin, SRAM memory is provided with SRAM power pins, power supervisor is powered by SRAM power pins to SRAM memory, and power supervisor is powered by core power pin to programmed logical module.SRAM memory is powered using independent power supply, when device enters holding state, power supervisor includes powering to SRAM memory, not to other module for power supply such as programmed logical module, it may be implemented in that not influence device high performance simultaneously, reduce power consumption and save the time.Because SRAM memory power supply is uninterrupted so that user program data flow is saved, and user logic will not be lost.When holding state terminates, after restoring electricity, device can immediately enter working condition, without reloading data streaming file, save time and loading power consumption.

Description

A kind of low-power consumption FPGA device

Technical field

The present invention relates to integrated circuit fields, more particularly, to a kind of extremely low FPGA devices of power consumption in the standby state Part.

Background technology

As increasing electronic application becomes particularly important to low-power consumption or battery powered demand, energy-conservation.Now Some applications must power consumption it is very low.

In past ten years, IC techniques are from 130nm fast development to 65nm and then enter quickly currently 16nm nodes, the progressive each time of technology all cause power management to become even more important.In 130nm nodes, IC productions Business begins to notice the current leakage problem of transistor, and under idle mode, there is also due to current leakage for transistor And the power consumption brought.Into the nanometer technology epoch, IC operating voltage further declines, but current leakage problem is tighter Weight, occupies sizable proportion in the total power consumption of device.Traditionally the product design of FPGA suppliers is towards in extensive range Using device includes substantial amounts of high speed transistor, therefore the power consumption of FPGA device can not look down upon.Most advanced technique is used with other The IC being designed is the same, and FPGA also uses the larger transistor design of current leakage.

The power consumption of FPGA device mainly has two classes：Quiescent dissipation and dynamic power consumption.Quiescent dissipation is due to transistor Leakage caused by, because even transistor still has current leakage when not working.Dynamic power consumption is then that device is performing The power consumed during task --- it is relevant with switch node quantity and electricity, frequency and electric capacity etc..In current technique node, especially It is that low-power consumption FPGA product quiescent dissipation turns into principal focal point.The power consumption of it and product holding state is directly now closed.

The major design method of low-power consumption FPGA is to use low-power consumption technique and low energy-consumption electronic device at present, reduces whole device Power consumption.And it is using sacrifice device performance as cost to use low energy-consumption electronic device, low performance is exchanged for low-power consumption, this is answered some It is feasible to use.But for high performance application, just unable to do what one wishes, the physical characteristic of device has the limit.At present The technique that major fab develops has been to optimize very much, it is impossible to improves performance simultaneously again and reduces power consumption, therefore one As designer one can only be selected between power consumption and performance.

The content of the invention

The present invention is to overcome at least one defect described in above-mentioned prior art（Deficiency）, there is provided one kind is in the standby state The extremely low FPGA device of power consumption, the FPGA device with it is high performance simultaneously, there is the characteristics of low-power consumption.

A kind of low-power consumption FPGA device, including user-defined programmed logical module and SRAM memory, it is described to compile Journey logic module is provided with core power pin, and SRAM memory is provided with SRAM power pins, and power supervisor passes through SRAM power supplys Pin is powered to SRAM memory, and power supervisor is powered by core power pin to programmed logical module.

SRAM memory in the FPGA device uses independent power pin, when device system enters holding state, Power supervisor includes powering to SRAM memory, not to other module for power supply such as programmed logical module, then may be implemented in not It is high performance simultaneously to influence device, reduces power consumption.

It is uninterrupted additionally, due to SRAM memory power supply so that all user program data flows are saved, and user logic is not It can lose.Therefore when holding state terminates, after restoring electricity, device can immediately enter working condition, without reloading data Stream file, save time and loading power consumption.

This programme makes PLD（FPGA）Middle SRAM memory（Programmed logic message part）Individually power supply, it is right Whole PLD（FPGA）User logic power-off.

Above-mentioned low-power consumption FPGA device also includes being used for the detection module for detecting SRAM memory data streaming file.Standby When state terminates, after restoring electricity, using whether there is data streaming file in detection module detection SRAM memory, if do not had Enter working condition after then reloading data streaming file, otherwise need not reload data streaming file, be directly entered work shape State, time and loading power consumption are saved, improves convenience.

Above-mentioned programmed logical module comprises at least register, and the register is provided with power pin, and power supervisor leads to Power pin is crossed to power to register.Register is powered using independent power pin, when system enters holding state, user Data are retained when entering holding state in register.

Above-mentioned low-power consumption FPGA device be from power supply construction for electricity, on the premise of FPGA device performance is not reduced, The holding state of one extremely low power dissipation of user is provided, FPGA can be made to enter new low-power consumption application field such as from traditional application The fields such as portable equipment, wearable device.

Compared with prior art, the beneficial effect of technical solution of the present invention is：SRAM memory is using independent in the present invention Power supply power supply, when device system enters holding state, power supervisor include to SRAM memory power, not to may be programmed Other module for power supply such as logic module, then may be implemented in that not influence device high performance simultaneously, reduces power consumption and saves the time.Separately Outside because SRAM memory power supply is uninterrupted so that all user program data flows are saved, and user logic will not be lost.Therefore When holding state terminates, after restoring electricity, device can immediately enter working condition, without reloading data streaming file, save Time and loading power consumption.

Brief description of the drawings

Fig. 1 is distribution schematic diagram of the power supply in overall architecture in existing fpga chip.

Fig. 2 is a typical fpga logic array composition.

Fig. 3 is a typical fpga logic array composition.

Fig. 4 is electric flow chart on traditional FPGA.

Fig. 5 is electric flow chart on FPGA of the present invention.

Embodiment

Accompanying drawing being given for example only property explanation, it is impossible to be interpreted as the limitation to this patent；

In order to more preferably illustrate the present embodiment, some parts of accompanying drawing have omission, zoomed in or out, and do not represent actual product Size；

To those skilled in the art, it is to be appreciated that some known features and its explanation, which may be omitted, in accompanying drawing 's.

Technical scheme is described further with reference to the accompanying drawings and examples.

Embodiment 1

Fig. 1 is a typical programming device, including a user-defined programmed logical module and one SRAM memory.SRAM array in SRAM memory is for storing programming data and programmed logical module being carried out real-time Control, defines logic to form it into user, realizes the function of user.The distribution of power pin is illustrated in Fig. 1.

Due to including substantial amounts of high speed transistor in FPGA, quiescent dissipation caused by leakage current is mainly in core logic and defeated Enter in output circuit.And SRAM leaks electricity minimum under static state, power consumption is extremely low.

Fig. 2 is that the power supply of SRAM array is independent, uses independent power pin.So can be in system power supply pipe Sleep state more in reason.

Fig. 3 is the example of a system application, is the power management on a system board.FPGA integrates with other Circuit devcie is all under the unified management of Power Management Devices.Because FPGA device has single power pin, therefore work as system During into holding state, Power Management Devices can only retain SRAM power supplies, without being powered to FPGA other power pins, this The power consumption of the whole device of sample becomes extremely low.On the other hand, because SRAM partial powers also exist, all user program data flows also by Preserve, user logic will not be lost.So when holding state termination, after chip restores electricity, working condition is immediately entered.Save The step of reloading data streaming file, save time and loading power consumption.

In programmed logical module（Logic module）In except combinational logic（LUT）Outside, also sequence circuit such as user posts Storage（DFF）Deng in this example by the method further genralrlization of SRAM independent current sources into user register circuit.User posts The power supply of latch circuit uses same method, can cause the data in user register entrance holding state is pre- to protect Stay.

All programming data and user logic register datas are all remained, and uninterrupted systematic difference in logic is carried Strong support is supplied.After going out holding state, system can be continued to run with down with the state before holding state immediately, without Custom system is run from the beginning, can be reduced power consumption and be saved the time.

In practice, SRAM memory includes several, is distributed across in user logic.However, on traditional FPGA Electricity and loading data flow need to change to adapt to this new mode of operation, and Fig. 4 is electric schematic flow sheet on traditional FPGA.

This apparent flow can have the following disadvantages under new mode of operation, when FPGA is electric from holding state, The data streaming file that electrification reset function can store SRAM is removed, and reloads data streaming file, when whole process expends Between and power consumption.It will be made troubles for user.

This method is to add detection module in FPGA programmed logical modules, and whether automatic detection has number in power up According to stream file in sram.If its specific power up as shown in figure 5, detection SRAM in there is no data streaming file, carry out Traditional upper electric current journey；If there is complete data streaming file in SRAM, electrification reset and data flow loading procedure are skipped, directly Tap into working condition.

Same or analogous label corresponds to same or analogous part；

Position relationship is used for being given for example only property explanation described in accompanying drawing, it is impossible to is interpreted as the limitation to this patent；

Obviously, the above embodiment of the present invention is only intended to clearly illustrate example of the present invention, and is not pair The restriction of embodiments of the present invention.For those of ordinary skill in the field, may be used also on the basis of the above description To make other changes in different forms.There is no necessity and possibility to exhaust all the enbodiments.It is all this All any modification, equivalent and improvement made within the spirit and principle of invention etc., should be included in the claims in the present invention Protection domain within.

Claims

1. a kind of low-power consumption FPGA device, including user-defined programmed logical module and SRAM memories, its feature exist In the programmed logical module is provided with core power pin, and SRAM memories are provided with SRAM power pins, power supervisor Powered by SRAM power pins to SRAM memories, power supervisor is by core power pin to programmed logical module Power supply；

SRAM partial powers also exist when FPGA device is in holding state, and all user program data flows are also saved, and user patrols Collecting to lose；

When FPGA device is in holding state, Power Management Devices retain SRAM power supplies, without to FPGA other power supply pipes Pin is powered, and holding state terminates, and after FPGA device restores electricity, immediately enters working condition；

FPGA device terminates in holding state, after FPGA device restores electricity, can detect and whether there is data in SRAM, if in the presence of Data, FPGA device immediately enter working condition；If data are not present, after FPGA device can re-download data, into work State；

When FPGA device is in holding state, Power Management Devices retain SRAM power supplies and required register is powered, without to FPGA other power pins power supply, after holding state terminates, data maintain the number before holding state in SRAM and register According to system can be continued to run with down with the state before holding state immediately, and FPGA is run from the beginning without custom system Device, power consumption can be reduced and save the time.

2. the low-power consumption FPGA device according to claim 1, it is characterised in that also include being used to detect SRAM storages The detection module of device data streaming file.

3. in FPGA device according to claim 1, can also include register, the register is provided with power pin, Power supervisor is powered by power pin to register.