CN106066970A - A kind of Low dark curient dual processors nuclear safety chip architecture - Google Patents
A kind of Low dark curient dual processors nuclear safety chip architecture Download PDFInfo
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- CN106066970A CN106066970A CN201610352610.7A CN201610352610A CN106066970A CN 106066970 A CN106066970 A CN 106066970A CN 201610352610 A CN201610352610 A CN 201610352610A CN 106066970 A CN106066970 A CN 106066970A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
- G06F21/70—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer
- G06F21/71—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information
- G06F21/76—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information in application-specific integrated circuits [ASIC] or field-programmable devices, e.g. field-programmable gate arrays [FPGA] or programmable logic devices [PLD]
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/26—Power supply means, e.g. regulation thereof
- G06F1/32—Means for saving power
- G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
- G06F1/3234—Power saving characterised by the action undertaken
- G06F1/3243—Power saving in microcontroller unit
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Abstract
The present invention proposes a kind of Low dark curient dual processors nuclear safety chip architecture, and this framework can realize minimizing of secured physical isolation and quiescent dissipation.This framework have employed two cpu subsystems, and a CPU is low performance low-power consumption low logic door number, is used for processing the non-security application such as communication interface；Another one CPU is the high safe CPU of high-performance, is used for providing the high performance cryptographic calculations of high complexity and sensitive information to process contour safety applications.High-performance cpu system logical complexity is higher, and its power supply is gated shutoff to reduce chip entirety electricity leakage power dissipation when chip enters Standby state.
Description
Technical field
The present invention proposes a kind of safety chip framework and method for designing that can keep Low dark curient in Standby state, is suitable for
In security chip design field.
Background technology
The power consumption of CMOS integrated circuit includes dynamic power consumption and quiescent dissipation, after dynamic power consumption is because N pipe or the unlatching of P pipe
The discharge and recharge of load capacitance is caused by power supply.Quiescent dissipation, also known as electricity leakage power dissipation, is that power supply is managed by the N closed or P manages
The electricity leakage power dissipation that ground produces.Before chip manufacture technique enters deep submicron process, it is overall that the dynamic power consumption of chip accounts for chip
The major part of power consumption, after chip technology enters deep-submicron and Super deep submicron process, chip quiescent dissipation is in overall merit
In consumption, proportion gradually rises.According to statistics, in 90nm technique, the dynamic power consumption such as fruit chip unit are is 1, at 65nm
Under technique, the dynamic power consumption of unit are reaches 1.4, is up to 2 under 45nm technique；Under 90nm technique, such as fruit chip list
It is 1 that plane amasss quiescent dissipation, and under 65nm technique, the quiescent dissipation of unit are is up to 2.5, and will reach under 45nm technique
To 6.5.As can be seen here, along with the lifting of integrated circuit design process level, quiescent dissipation will increasingly become low power dissipation design
Pay close attention to object.
In safety chip, especially in the safety applications chip such as intelligent card chip of sensitive power consumption, often use such as
Chip architecture shown in accompanying drawing 1.Chip includes voltage commutation VR (110), clock oscillator OSC (120), safety sensor
(130), randomizer (140) and CPU and crypto-operation system (150) a few major part.External power supply passes through voltage commutation
Module provides core voltage for full chip.In accompanying drawing 1 and accompanying drawing 2, heavy black line all represents power line.CPU and crypto-operation system
Should process the complicated bigger crypto-operation of computing, communication and instruction that complexity to be processed is minimum resolve.Work as safety chip
When completing communication and crypto-operation, needing to enter standby (Standby) state, now chip main power consumption is quiescent dissipation.?
When safety chip processing technique level is 90nm, quiescent dissipation does not the most become the obstacle of chip low-power consumption application.And current safety
Chip manufacture technique just migrates toward 65nm, 55nm even 40nm, and quiescent dissipation is very important, needs to use new method for designing
Ensure safety chip power consumption levels under Standby state.Additionally, safety applications and non-security application are by single CPU
Complete, need software system to do the extra security isolation design overall security with guarantee chip, to software design increase
Difficulty.
Summary of the invention
The present invention proposes a kind of new dual processors Kernel security chip system framework, as shown in Figure 2.
In the present invention, first the function of safety chip is classified.By crypto-operation service, sensitive information access and
The function that the safety requirements such as process are high, computational complexity is big is divided into a class；By low to Communication processing, the instruction safety requirements such as parsing,
The function that computational complexity is little is divided into an other class.Two different cpu subsystems are used to realize two class computing and places respectively
Reason.Two CPU can only access respective memory resource and register resources.The cpu subsystem of the high complexity of high safety is permissible
Targetedly bus system, crypto-operation unit, accumulator system are done special safe design such as mask, encryption, redundancy
Inject Deng the anti-leak and fail-safe to ensure safety information and anti-physics intrusive mood is attacked.And the low operation strength of low complex degree
Cpu subsystem need not do special safe design.High complexity CPU of high safety and the thorough physics of lower security low complex degree CPU
Isolation also ensure that the access rights differentiation of secure resources and minimizes design.
In the present invention, in order to ensure that the safety chip quiescent dissipation when Standby reaches minimum, set at safety chip
In meter, have employed power gating technology, the electricity of broken height complexity cpu subsystem can be closed when safety chip enters Standby
Source, it is ensured that the source-drain power consumption of this part is 0, such that it is able to be minimized chip entirety electricity leakage power dissipation.And chip is entering
During the external communication of row, high complexity cpu system remains powered off or the low power consumpting state of electric power starting, it is ensured that chip when communication
Overall power level relatively low to meet the communication merit of special communication power consumption requirements chip such as 14443 non-contact interface safety chip
Can be normal.Chip is when carrying out crypto-operation and sensitive information processes, and high complexity cpu subsystem power supply is unlocked, low complexity
It is overall to reduce chip that degree cpu subsystem now can decide whether to enter low power consumpting state according to chip power-consumption design level
Power consumption.
Accompanying drawing explanation
Fig. 1 is conventional security chip system framework
Fig. 2 is the dual processors nuclear safety chip system framework that the present invention proposes
Detailed description of the invention
As in figure 2 it is shown, in safety chip, have two cpu subsystems, one is CPU_1 subsystem (200), and one is
CPU_2 subsystem (300).CPU_1 subsystem completes communication interface and processes and instruction parsing, and CPU_2 subsystem provides password fortune
Calculate service and sensitive information processes.CPU_1 subsystem and CPU_2 subsystem have the memory resource of respective physical separation, pass through
Special data channel (270) interaction data.
CPU_1 (222) can use the non-security CPU core of the low logic low operational capabilities of door number such as standard 8051, for reality
Existing Communication processing and instruction resolve, and are integrated with memory cell _ 1 (221), communication interface unit by single system bus
(223) and system control unit (224), memory cell _ 1 includes properly functioning required RAM and ROM of CPU_1.Due to function
Relatively simple, this partial memory size, far below the memorizer of CPU_2 system, the most also has less electricity leakage power dissipation.CPU_2
(313) SC000 or SC300 of the safe CPU core such as ARM with stronger operational capability can be used.For realizing crypto-operation
Function, memory cell _ 2 (314), algorithm coprocessor (312) and secure processing units (311) by security system bus and
CPU_2 is integrated to form CPU_2 subsystem.CPU_2 secure subsystem is due to CPU and complicated security coprocessor and safe place
Reason, logic gate number is typically the several times of CPU_1 Subsystem logical door number to decades of times, after this partial power gates, will make entirety
The part that electricity leakage power dissipation is reduced under non-gate is to 1/tens.
For realizing the power remove of CPU_2 subsystem, chip have employed two voltage rectifying circuit VR_1 (210) and
VR_2 (340), VR_1 need the circuit keeping power supply normally opened to provide power supply electricity for CPU_1 subsystem and power gating controller etc.
Pressure, and the input of the voltage of VR_2 comes from power gating circuit, provides supply voltage for whole CPU_2 subsystem.
Power gating control unit turns off or on the voltage of VR_2 according to chip status switching control power gating circuit
Input.Concrete control method is, when chip needs to enter Standby, produces control signal, turns off the voltage input of VR_2；
When chip is waken up from Standby, produces control signal, open switch, again provide voltage input for VR_2.
For ensureing that CPU_2 subsystem will not have when not having voltage inactive level to be input to CPU_1 subsystem and cause function
Mistake or new electric leakage, be input to data path isolated location to be had (260) of CPU_1 subsystem from CPU_2 subsystem, it is ensured that
The level signal that CPU_1 subsystem receives is fixing high level or low level.
In CPU_2 subsystem, for reducing extra electrifying startup time overhead, system clock derives from system OSC
(250), therefore should increase extra clock detection in secure processing units prevents clock from being disturbed by direct fault location or physics is invaded
Enter to attack amendment.
The specific works mode of safety chip is: when safety chip is in Standby state, and CPU_1 subsystem keeps
Electric power starting, enters low power consumpting state；CPU_2 subsystem power supply is gated shutoff, to ensure the electricity leakage power dissipation of chip Standby
It is preferably minimized.When safety chip is in communication state, CPU_1 subsystem exits low power consumpting state, carries out communication receiving/transmission and instruction
Dissection process.CPU_2 subsystem remains turned-off or electric power starting, but is in low power consumpting state.When safety chip needs to carry out close
Code computing or carry out sensitive information when processing, CPU_2 subsystem power supply is unlocked, and carries out crypto-operation or sensitive data and processes.
The above, the only one of the present invention realizes example, is not intended to limit protection scope of the present invention.All
Within the spirit and principles in the present invention, any modification, equivalent substitution and improvement etc. done, should be included in the guarantor of the present invention
Within the scope of protecting.
Claims (7)
1. the double CUP nuclear safety chip architecture of Low dark curient, it is characterised in that: safety chip includes two cpu system subsystems,
Two CPU can only access respective memorizer and register resources, it is achieved the thorough physics of safety applications and non-security application every
From.Two cpu subsystems the most at least can provide low-power consumption and two kinds of duties of normal work.
Framework the most according to claim 1 a, it is characterised in that cpu subsystem is responsible for relatively low the leading to of computational complexity
Communication interface and command analysis；Another one cpu subsystem is responsible for the higher crypto-operation service of computational complexity and sensitive information
Process.
Framework the most according to claim 2, it is characterised in that the cpu subsystem tool that described responsible computational complexity is relatively low
There are data storage and program storage and more weak computing energy that the most described responsible computational complexity height cpu subsystem is less
The CPU element of power.
Framework the most according to claim 2, it is characterised in that the cpu subsystem tool that described responsible computational complexity is higher
There are data storage and program storage that the most described relatively low cpu subsystem of responsible computational complexity is bigger, and possess relatively
The CPU element of strong operational capability.
5. according to the framework described in claim 1 and claim 2, it is characterised in that described safety chip is in Standby shape
During state, it is responsible for the relatively low cpu subsystem of computational complexity and keeps electric power starting, enter low power consumpting state；It is responsible for computational complexity
Higher cpu subsystem power supply is gated shutoff, to ensure that the electricity leakage power dissipation of chip Standby is preferably minimized.
6. according to the framework described in claim 1 and claim 2, it is characterised in that described safety chip is in communication state
Time, the cpu subsystem being responsible for computational complexity relatively low exits low power consumpting state, carries out communication receiving/transmission and instruction dissection process.Negative
The duty higher cpu subsystem of computational complexity remains turned-off or electric power starting, but is in low power consumpting state.
7. according to the framework described in claim 1 and claim 2, it is characterised in that described safety chip needs to carry out password
Computing or carry out sensitive information process time, the cpu subsystem power supply that responsible computational complexity is higher is unlocked, and carries out crypto-operation
Or sensitive data processes.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201610352610.7A CN106066970A (en) | 2016-05-26 | 2016-05-26 | A kind of Low dark curient dual processors nuclear safety chip architecture |
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| CN201610352610.7A CN106066970A (en) | 2016-05-26 | 2016-05-26 | A kind of Low dark curient dual processors nuclear safety chip architecture |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112597724A (en) * | 2021-03-04 | 2021-04-02 | 长沙海格北斗信息技术有限公司 | RISC-V based chip design method, navigation chip and receiver |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101276384A (en) * | 2007-03-30 | 2008-10-01 | 成都方程式电子有限公司 | Security control chip and implementing method thereof |
| CN104808769A (en) * | 2015-04-21 | 2015-07-29 | 广东高云半导体科技股份有限公司 | Low-power-consumption FPGA (Field Programmable Gate Array) device |
| CN104954941A (en) * | 2015-06-10 | 2015-09-30 | 福州瑞芯微电子有限公司 | High-performance and low-power HIFI (high fidelity) decoding system |
-
2016
- 2016-05-26 CN CN201610352610.7A patent/CN106066970A/en not_active Withdrawn
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101276384A (en) * | 2007-03-30 | 2008-10-01 | 成都方程式电子有限公司 | Security control chip and implementing method thereof |
| CN104808769A (en) * | 2015-04-21 | 2015-07-29 | 广东高云半导体科技股份有限公司 | Low-power-consumption FPGA (Field Programmable Gate Array) device |
| CN104954941A (en) * | 2015-06-10 | 2015-09-30 | 福州瑞芯微电子有限公司 | High-performance and low-power HIFI (high fidelity) decoding system |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112597724A (en) * | 2021-03-04 | 2021-04-02 | 长沙海格北斗信息技术有限公司 | RISC-V based chip design method, navigation chip and receiver |
| CN112597724B (en) * | 2021-03-04 | 2021-05-25 | 长沙海格北斗信息技术有限公司 | RISC-V based chip design method, navigation chip and receiver |
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Application publication date: 20161102 |