CN104808769A

CN104808769A - Low-power-consumption FPGA (Field Programmable Gate Array) device

Info

Publication number: CN104808769A
Application number: CN201510192294.7A
Authority: CN
Inventors: 朱璟辉
Original assignee: Guangdong High Cloud Semiconductor Technologies Ltd Co
Current assignee: Guangdong High Cloud Semiconductor Technologies Ltd Co; Gowin Semiconductor Corp
Priority date: 2015-04-21
Filing date: 2015-04-21
Publication date: 2015-07-29
Anticipated expiration: 2035-04-21
Also published as: CN104808769B

Abstract

The invention discloses a low-power-consumption FPGA (Field Programmable Gate Array) device. The low-power-consumption FPGA device comprises a user-defined programmable logical module and an SRAM (Static Random Access Memory), wherein the programmable logical module is provided with a core power supply pin; the SRAM is provided with an SRAM power supply pin; a power supply manager supplies power to the SRAM through the SRAM power supply pin, and supplies power to the programmable logical module through the core power supply pin. The SRAM is powered by adopting an independent power supply; when the device enters a standby state, the power supply manager supplies power to the SRAM and does not supply power to the logical programmable module and other modules, so that the high performance of the device is not influenced, power consumption is reduced, and time is saved. The power is supplied to the SRAM uninterruptedly, so that the user programmable data flow is saved; user logic cannot lose. When the standby state is terminated, and the power supply is recovered, the device can enter a working state immediately; a data flow file is not required to be reloaded; the time is saved; loading power consumption is reduced.

Description

A kind of low-power consumption FPGA device

Technical field

The present invention relates to integrated circuit fields, more specifically, relate to the FPGA device that a kind of power consumption is in the standby state extremely low.

Background technology

Along with increasing electronic application is to low-power consumption or battery powered demand, energy-conservationly become particularly important.The current necessary power consumption of some application is very low.

In ten years in the past, IC technique also enters current 16nm node from 130nm is fast-developing subsequently very soon to 65nm, and the progressive each time of technology all makes power management become even more important.When 130nm node, IC manufacturer just starts the current leakage problem noticing transistor, even if under idle mode, transistor also exists the power consumption brought due to current leakage.Enter the nanometer technology epoch, the operating voltage of IC declines further, but current leakage problem is more serious, in the total power consumption of device, occupy sizable proportion.The product design of FPGA supplier is towards far-ranging application traditionally, and device comprises a large amount of high speed transistors, and therefore the power consumption of FPGA device can not look down upon.The same with the IC that other adopts most advanced technique to carry out designing, FPGA also uses the larger transistor design of current leakage.

The power consumption of FPGA device mainly contains two classes: quiescent dissipation and dynamic power consumption.Quiescent dissipation causes, even if because transistor still exists current leakage when not working due to the leakage of transistor.Dynamic power consumption is then the power that device consumes when executing the task---relevant with switch junctions point quantity and electricity, frequency and electric capacity etc.At current technique node, particularly low-power consumption FPGA product quiescent dissipation becomes principal focal point.The power consumption of it and product holding state is directly now closed.

The major design method of current low-power consumption FPGA adopts low-power consumption technique and low energy-consumption electronic device, reduces the power consumption of whole device.And adopt low energy-consumption electronic device to take sacrifice device performance as cost, exchange low performance for low-power consumption, this is feasible in some application.But for high performance application, just unable to do what one wishes, the physical characteristics of device has the limit.The technique that current Ge great wafer factory develops has been optimize very much, can not improve performance more simultaneously and reduce power consumption, therefore general designer can only select one between power consumption and performance.

Summary of the invention

The present invention is for overcoming at least one defect (deficiency) described in above-mentioned prior art, and provide the FPGA device that a kind of power consumption is in the standby state extremely low, this FPGA device, having high performance while, has the feature of low-power consumption.

A kind of low-power consumption FPGA device, comprise user-defined programmed logical module and SRAM memory, described programmed logical module is provided with core power pin, SRAM memory is provided with SRAM power pin, power supervisor is powered to SRAM memory by SRAM power pin, and power supervisor is powered to programmed logical module by core power pin.

SRAM memory in this FPGA device uses independently power pin, when device system enters holding state, power supervisor comprises powers to SRAM memory, not to other module for power supply such as programmed logical module, then can realize do not affect device high performance while, reduce power consumption.

In addition because SRAM memory is powered uninterruptedly, all user program data stream are saved, and user logic can not be lost.Therefore when holding state stops, after restoring electricity, device can enter duty at once, without the need to reloading data streaming file, saving the time and loading power consumption.

This programme makes SRAM memory (programmed logic message part) in programmable logic device (PLD) (FPGA) power separately, to the user logic power-off of whole programmable logic device (PLD) (FPGA).

Above-mentioned low-power consumption FPGA device also comprises the detection module for detecting SRAM memory data streaming file.When holding state stops, after restoring electricity, detection module is adopted to detect in SRAM memory whether there is data streaming file, if enter duty after, not reloading data streaming file, otherwise without the need to reloading data streaming file, directly enter duty, save the time and load power consumption, improving convenience.

Above-mentioned programmed logical module at least comprises register, and described register is provided with power pin, and power supervisor is powered to register by power pin.Register adopts independently power pin to power, and when system enters holding state, in user register, data are retained when entering holding state.

Above-mentioned low-power consumption FPGA device is from Power supply framework, under the prerequisite not reducing FPGA device performance, user is provided the holding state of an extremely low power dissipation, FPGA can be made to enter into new low-power consumption application as portable equipment from traditional application, the fields such as wearable device.

Compared with prior art, the beneficial effect of technical solution of the present invention is: in the present invention, SRAM memory adopts independently Power supply, when device system enters holding state, power supervisor comprises powers to SRAM memory, not to other module for power supply such as programmed logical module, then can realize do not affect device high performance while, reduce power consumption and saving time.In addition because SRAM memory is powered uninterruptedly, all user program data stream are saved, and user logic can not be lost.Therefore when holding state stops, after restoring electricity, device can enter duty at once, without the need to reloading data streaming file, saving the time and loading power consumption.

Accompanying drawing explanation

Fig. 1 is the distribution schematic diagram of power supply in overall architecture in existing fpga chip.

Fig. 2 is a typical fpga logic array composition.

Fig. 3 is a typical fpga logic array composition.

Fig. 4 is that traditional F PGA powers on process flow diagram.

Fig. 5 is that FPGA of the present invention powers on process flow diagram.

Embodiment

Accompanying drawing, only for exemplary illustration, can not be interpreted as the restriction to this patent;

In order to better the present embodiment is described, some parts of accompanying drawing have omission, zoom in or out, and do not represent the size of actual product;

To those skilled in the art, in accompanying drawing, some known features and explanation thereof may be omitted is understandable.

Below in conjunction with drawings and Examples, technical scheme of the present invention is described further.

Embodiment 1

Fig. 1 is a typical programming device, comprising a user-defined programmed logical module and a SRAM memory.SRAM array in SRAM memory is used to store both program data and controls in real time programmed logical module, forms user and defines logic, realize the function of user to make it.Illustrate in Fig. 1 power pin distribution.

Owing to comprising a large amount of high speed transistors in FPGA, the quiescent dissipation that leakage current causes is mainly in core logic and imput output circuit.And SRAM leaks electricity minimum under static state, power consumption is extremely low.

Fig. 2 is by independent for the power supply of SRAM array, uses independently power pin.Like this can on power supply managing many sleep states.

Fig. 3 is the example of a system application, is the power management on a system board.FPGA and other integrated circuit (IC)-components are all under the unified management of Power Management Devices.Because FPGA device has independent power pin, therefore when system enters holding state, Power Management Devices can only retain SRAM and power, and does not power to other power pin of FPGA, and the power consumption of whole like this device becomes extremely low.On the other hand, because SRAM partial power also exists, all user program data stream are also saved, and user logic can not be lost.Like this when holding state stops, after chip restores electricity, enter duty at once.Eliminate the step reloading data streaming file, save the time and load power consumption.

In programmed logical module (logic module) except combinational logic (LUT), also have sequential circuit as user register (DFF) etc., in this example by the method further genralrlization of SRAM independent current source in user register circuit.The power acquisition of user register circuit uses the same method, and the data in user register can be made to be in advance to retain entering holding state.

All programming datas and user logic register data all remain, and provide strong support to uninterrupted systematic difference in logic.After going out holding state, system can continue operation with the state before holding state immediately and go down, and does not need custom system to start anew to run, and can reduce power consumption and save time.

In practice, SRAM memory comprises several, is distributed in user logic.But traditional FPGA powers on and loads data flow to be needed to change and adapts to this new mode of operation, and Fig. 4 is that traditional FPGA powers on schematic flow sheet.

Clearly this flow process can have the following disadvantages under new mode of operation, and when FPGA powers on from holding state, the data streaming file that SRAM can store by electrification reset function is removed, and reloads data streaming file, whole process consumes time and power consumption.To make troubles for user.

This method adds detection module in FPGA programmed logical module, and in power up, whether automatic detection has data streaming file in sram.Its concrete power up as shown in Figure 5, does not have data streaming file if detected in SRAM, then carries out traditional flow process that powers on; If there is complete data streaming file in SRAM, then skips electrification reset and data stream loading procedure, directly enter duty.

The corresponding same or analogous parts of same or analogous label;

Describe in accompanying drawing position relationship for only for exemplary illustration, the restriction to this patent can not be interpreted as;

Obviously, the above embodiment of the present invention is only for example of the present invention is clearly described, and is not the restriction to embodiments of the present invention.For those of ordinary skill in the field, can also make other changes in different forms on the basis of the above description.Here exhaustive without the need to also giving all embodiments.All any amendments done within the spirit and principles in the present invention, equivalent to replace and improvement etc., within the protection domain that all should be included in the claims in the present invention.

Claims

1. a low-power consumption FPGA device, comprise user-defined programmed logical module and SRAM memory, it is characterized in that, described programmed logical module is provided with core power pin, SRAM memory is provided with SRAM power pin, power supervisor is powered to SRAM memory by SRAM power pin, and power supervisor is powered to programmed logical module by core power pin.

2. low-power consumption FPGA device according to claim 1, is characterized in that, also comprises the detection module for detecting SRAM memory data streaming file.

3. low-power consumption FPGA device according to claim 1 and 2, is characterized in that, described programmed logical module at least comprises register, and described register is provided with power pin, and power supervisor is powered to register by power pin.