CN102545574B

CN102545574B - Low-power consumption power network designing method for system on chip (SOC) chip

Info

Publication number: CN102545574B
Application number: CN201010622316.6A
Authority: CN
Inventors: 周卓; 刘鹏; 赵彦光
Original assignee: Beijing CEC Huada Electronic Design Co Ltd
Current assignee: Beijing CEC Huada Electronic Design Co Ltd
Priority date: 2010-12-27
Filing date: 2010-12-27
Publication date: 2014-05-07
Anticipated expiration: 2030-12-27
Also published as: CN102545574A

Abstract

The invention discloses a low-power consumption power network designing method for a system on chip (SOC) chip. A power device is controlled to control the power-on and power-off of different power networks, so that chip resetting current is effectively reduced, and the normal operation power consumption of the chip is optimized. By the low-power consumption designing method for a hard module, system power network design is facilitated, and power control in the normal operation and test processes of the chip is simplified.

Description

A kind of low-power dissipation power supply network design method of SOC chip

Technical field

The present invention relates to power network design method and the implementation structure of low-power dissipation SOC chip.

Background technology

In current consumer SOC chip design, power consumption becomes successfully the criterion of chip just gradually, and the stand-by time of system is also becoming one of deciding factor concerning product success or failure gradually.

Along with integrated circuit is produced to the striding forward of deep submicron process, the ratio of the shared chip total power consumption of leakage power increases gradually, and this also makes the increasing design mode of power cutoff network reduce leakage power.For this situation, a kind of low-power dissipation power supply network design method and structure have been proposed herein, by this method for designing, effectively reduce chip leakage power, and improve design efficiency.

Summary of the invention

The present invention proposes a kind of SOC low-power dissipation power supply network design structure, this structure adopts a PMU module in chip handoff procedure, by controlling LDO, enables to control the mode of opening and turn-offing each electric power network, reduces the leakage power of SOC chip.

In chip, PMU is used an electric power network power supply of often opening, and except PMU, other core power supply is all used LDO power supply in sheet, and IO voltage is from the normal switch power supply of chip exterior, and LDO input power is from the outer DC-DC output of sheet.Chip is divided into multiple power domain according to different LDO supply networks.PMU enables to control by LDOO in control strip and opens and turn-off each electric power network.

Under chip testing pattern, in order to facilitate various tests to carry out smoothly, in sheet, each LDO, in opening, all opens the electric power network of each power domain, completes chip testing.These tests comprise testing scanning chain, memory BIST test, analog circuit BIST test etc.

Under chip operation pattern, during chip reset, in chip, all LDO are in off state, the power supply of all power domain electric power networks except PMU is all turned off, by chip pin, close the DC-DC output outside sheet simultaneously, close LDO input power, to guarantee that chip has extremely low leakage power when resetting.After reset is released, PMU progressively enables the LDO of an electric power network, is the unlatching power supply of other power domain electric power network, and chip is switched to and enters normal operating conditions.

In the course of work, PMU configures according to software, switches chip operation state, and the LDO that simultaneously controls other electric power network enables, and turn-offs the circuit power that does not need work, opens and needs the circuit power of work, thereby reach the object of optimizing SOC chip power-consumption.The core power supply that is now turned off the IO unit of power domain is also closed, but PMU can not close the I/O power supply of IO unit, therefore needs to use special IO unit to avoid occurring in this case large crowbar electric current.

PMU is when controlling each power domain electric power network shutoff, attention provides isolation enable signal for the power domain module input not being turned off, when existing power cutoff territory signal to be input to the digital signal in power cutoff territory not, the isolation enable signal in power cutoff territory is not set to effectively.

In order to make complicated comprising after the hard module integration of multi-power domain submodule, can control its different electrical power territory submodule by PMU turn-offs respectively, each submodule is carried out isolation to its supplied with digital signal, and isolation enables control end and draws from module top layer, and finally by PMU, is controlled.

Accompanying drawing explanation

Fig. 1 is chip power network diagram.

Fig. 2 is a circuit diagram that exists the die piece inside circuit of multi-power domain to realize isolation.

Embodiment

Take a WLAN (wireless local area network) SOC chip low-power dissipation power supply network design structure as example, the inventive method and structure are described below.It is chip I/O and analog module power supply that 3.3V voltage is often opened in chip exterior input, it is separately PMU power supply that 1.2V voltage is often opened in input, DC-DC output 1.5V voltage is chip internal LDO power supply, and when all LDO enable to be set to when invalid, this 1.5V voltage is also turned off to reduce LDO electric leakage.Chip internal LDO output 1.2V power supply is the electric power network power supply of other power domain except PMU.

Chip power territory is divided

According to the difference of LDO power supply, chip is divided into 4 power domain (seeing Fig. 1), and each several part is respectively described below:

PMU power domain (PD1): normal switch power supply territory, comprises Power Management Unit module.In this power domain power work, be held open always, and according to different operating states, can control opening and shutting off of other power domain electric power network at work.

HOST_IF power domain (PD2): can turn-off digital power territory, comprise Host Interface and Clock Gating Control module;

BBP power domain (PD3): can turn-off digital power territory, comprise Processor and Baseband Subsystem module;

RF power domain (PD4): can turn-off analog power territory, comprise RF & AD/DA subsystem module.

For RF & AD/DA subsystem module, its design complexities is higher, and inside exists multiple power domain, uses respectively different LDO power supplies.In design, as a die piece, be integrated in SOC chip.In the different operating state of chip, module corresponding to the inner each power domain of RF do not need to work simultaneously, and therefore PMU can control whether open respective modules electric power network by the LDO of the each power domain of control switch, reduces chip operation power consumption.

The processing of interface signal between different electrical power territory

When certain power domain power remove, its output digit signals can, in floating dummy status, if this signal is input to any power-on territory, can produce larger electric leakage in power-on territory, therefore should do in this power-on territory signal isolation, isolation enable signal is provided by PMU.

For fear of between the submodule of RF & AD/DA subsystem inside modules different electrical power territory when the power remove the influencing each other of floating spacing wave, use following mode to process the signal (as Fig. 2) between submodule:

If there is output signal to submodule B in submodule A, suppose to exist a-power supply to turn-off, the state that B-source is opened is isolated the signal of inputting from A in B, and this isolation enable signal will be subject to the control of B port signal; Vice versa.When integrated, due to the Already in top layer of module of isolation signals, therefore PMU can, when controlling unlatching and turn-offing A or B modular power source, control and whether need to enable isolation signals.

Electric power network design when chip is normally worked

Under chip operation pattern, during chip reset, in chip, all LDO are in off state, and the power supply of all power domain electric power networks except PMU is all turned off.For guaranteeing that chip has low leakage power when resetting, further by output control terminal mouth, close the 1.5V power supply input outside sheet, to eliminate the electric leakage of LDO under this state.The outer 1.5V power supply of sheet is from the output of DC-DC power supply apparatus, and under reset case, chip, by controlling this DC-DC Enable Pin, is closed the input of 1.5V power supply.After reset is released, PMU progressively opens LDO in sheet, is the unlatching power supply of other power domain electric power network, and chip enters normal mode of operation.

PMU, according to the residing operating state of chip, selects closed portion LDO, reduces power consumption.The core power supply that is now turned off the IO unit of power domain is also closed, but PMU can not close the IO power supply (3.3V power supply) of IO unit, therefore need to use special IO unit, avoid this IO unit at core power-off, in the situation of IO electric power starting, occur large crowbar electric current.

Electric power network design in chip testing process

In chip testing process, guarantee tested circuit in power opening state to complete smoothly test, therefore when test enable signal is effective, the LDO enable signal of PMU output is set to effectively, it is invalid that the isolation signals between power domain is set to.

Disclosed is above only a specific embodiment of the present invention, but protection scope of the present invention is not limited to this, and the changes that any person skilled in the art can think of all should drop in protection scope of the present invention.

Claims

1. a SOC chip low-power dissipation power supply network design method, chip is divided into multiple power domain, it is characterized in that, each power domain is by the low pressure difference linear voltage regulator LDO power supply in chip, by power management module PMU, the switch of directly controlling LDO carrys out opening and shutting off except all other power domain power supplys of PMU power domain in control chip; The input power of LDO is from the output of the outer DC-DC of sheet, under chip normal operating conditions, reset when effective, in chip, all LDO are in off state, the power supply of all power domain electric power networks except PMU is all turned off, by chip pin, close the DC-DC output outside sheet simultaneously, close LDO input power, further reduce chip reset electric current; PMU is when controlling other power domain electric power starting or shutoff, when existing power cutoff territory signal to be input to the digital signal in power cutoff territory not, the isolation enable signal in power cutoff territory is not set to effectively, the die piece of multiple power domain of opening and turn-offing when different for existence, the power supply of its submodule enables all from module top layer, to draw with isolating enable signal, by PMU, has unified control.

2. a kind of SOC chip low-power dissipation power supply network design method as claimed in claim 1, it is characterized in that, in other power domain except PMU, the precharge power supply of IO unit is used the LDO power supply that can turn-off, use is with the IO unit of upper electric control, avoid this IO unit at precharge power-off, in the situation of IO electric power starting, occur large leakage current.

3. a kind of SOC chip low-power dissipation power supply network design method as claimed in claim 1, it is characterized in that, under chip testing pattern, after chip reset, interior each LDO of chip is in opening, directly open all electric power networks that test needs, avoid the power domain of test circuit under test reset state to be turned off, complete chip testing, in chip testing process, guarantee tested circuit in power opening state to complete smoothly test, therefore when test enable signal is effective, the LDO enable signal of PMU output is set to effectively, it is invalid that isolation signals between power domain is set to.