CN219574672U

CN219574672U - Low-power consumption system, microcontroller and chip

Info

Publication number: CN219574672U
Application number: CN202321322088.XU
Authority: CN
Inventors: 屠庆东; 高挺挺
Original assignee: Xinsiyuan Microelectronics Co ltd
Current assignee: Xinsiyuan Microelectronics Co ltd
Priority date: 2023-05-24
Filing date: 2023-05-24
Publication date: 2023-08-22
Anticipated expiration: 2033-05-24

Abstract

The utility model provides a low-power consumption system, a microcontroller and a chip, comprising: the power supply comprises a first switch module, a normally open GPIO module, a shutoff GPIO module, a power converter, a second switch module, a normally open functional module and a shutoff functional module; the first switch module is arranged between the external power supply and the turn-off GPIO module, and controls the turn-off GPIO module to be powered on or powered off based on a first switch control signal; the normally open GPIO module and the power converter are connected with an external power supply; the second switch module is arranged between the power converter and the turn-off functional module, and is used for controlling the turn-off functional module to be powered on or powered off based on a second switch control signal; the normally open functional module is connected with the power converter and generates a first switch control signal and a second switch control signal. According to different functions of the power consumption device, the utility model distinguishes a circuit which can be turned off from a circuit which is required to be turned on, so that the turn-off circuit is selectively turned off, and the system power consumption is maintained at 3 uA-4 uA at 25 ℃.

Description

Low-power consumption system, microcontroller and chip

Technical Field

The present utility model relates to the field of microcontrollers, and in particular, to a low power system, a microcontroller, and a chip.

Background

Modern microcontroller units (MCUs) are often required to implement low power designs in different application scenarios for a number of reasons, including: (1) battery life: many application scenarios require an MCU to be used with a battery, so a long battery life is very important for users. By realizing low-power consumption design, the service life of the battery can be prolonged, and the frequency of charging and replacing the battery can be reduced; (2) thermal management: the MCU design typically generates a significant amount of heat that needs to be effectively managed, which can otherwise lead to reduced circuit performance. The low-power consumption design is realized, so that the heat generation can be reduced, and the stability and the reliability of the circuit are improved; (3) cost reduction: by implementing a low power design, the number of devices required by the circuit can be reduced, reducing overall cost. Meanwhile, the low-power consumption design can also reduce the use of a radiator and a cooler, so that the cost is further reduced; (4) environmental protection: the low-power design can reduce energy consumption, reduce the influence on the environment and improve the sustainability. In some environment-friendly application scenarios, such as the fields of smart home, industrial automation and the like, low-power design has become one of the factors that must be considered in design.

Therefore, implementing a low power design has become a very important ring in modern MCU designs. By employing low power technology and an optimized design, more efficient, reliable and economical circuitry can be achieved.

Based on the above, the utility model provides a low-power-consumption system, a microcontroller and a chip, which are used for solving the problems of high cost and high power consumption of low-power-consumption MCU design in the prior art. It should be noted that the foregoing description of the background art is only for the purpose of providing a clear and complete description of the technical solution of the present utility model and is presented for the convenience of understanding by those skilled in the art. The above-described solutions are not considered to be known to the person skilled in the art simply because they are set forth in the background of the utility model section.

Disclosure of Invention

In view of the above drawbacks of the prior art, an object of the present utility model is to provide a low power system, a microcontroller and a chip for solving the problems of high cost and high power consumption in the prior art for designing an MCU with low power consumption.

To achieve the above and other related objects, the present utility model provides a low power consumption system comprising:

the power supply comprises a first switch module, a normally open GPIO module, a turn-off GPIO module, a power converter, a second switch module, a normally open functional module and a turn-off functional module;

the first end of the first switch module is connected with an external power supply, the second end of the first switch module is connected with the turn-off GPIO module, and the turn-off GPIO module is controlled to be powered on or powered off based on a first switch control signal;

the input end of the normally open GPIO module is connected with the external power supply, and electric energy is directly obtained from the external power supply;

the input end of the power converter is connected with the external power supply, and the voltage output by the external power supply is converted into a preset voltage;

the first end of the second switch module is connected with the power converter, the second end of the second switch module is connected with the turn-off functional module, and the turn-off functional module is controlled to be powered on or powered off based on a second switch control signal;

the input end of the normally open functional module is connected with the output end of the power converter, and electric energy is directly obtained from the power converter and used for generating the first switch control signal and the second switch control signal.

Optionally, the power converter is set to DCDC or LDO.

Optionally, the first switch module and the second switch module are both set as LDOs.

Optionally, the first switch module 111 and the second switch module 122 are both set as LDOs.

Optionally, the shutdown functional module includes an SRAM cell, K MTCMOS switches, and K functional units; k is an integer greater than or equal to 1; the first end of each MTCMOS switch is connected with the second end of the second switch module, the second end of each MTCMOS switch is connected with a corresponding functional unit, and the corresponding functional unit is controlled to be powered on or powered off based on an MTCMOS control signal output by the normally-open functional module; and the input end of the SRAM unit is connected with the output end of the second switch module, and the SRAM unit is controlled to be powered on or powered off based on the second switch control signal.

Optionally, the turn-off functional module further includes an MTCMOS switch connected between the SRAM cell and the second switch module, the SRAM cell being controlled to be powered on or off based on the MTCMOS control signal.

Optionally, each functional unit is a security unit, a CPU unit or a peripheral unit, respectively.

Optionally, the normally open functional module includes a power management unit; the power management unit generates a first switch control signal and a second switch control signal to further control the first switch module and the second switch module to be conducted or closed respectively.

Optionally, the normally open functional module further includes an internal wake-up source, an external wake-up source, and a power-on reset signal generating circuit; the internal awakening source and the external awakening source are respectively connected with the input end of the power management unit and control the power management unit to work; the power-on reset signal generating circuit is connected with the input end of the power management unit and is used for resetting the power management unit.

To achieve the above and other related objects, the present utility model provides a microcontroller comprising: the low power consumption system is described above.

To achieve the above and other related objects, the present utility model provides a chip comprising: the low power consumption system is described above.

To achieve the above and other related objects, the present utility model provides a low power consumption control method based on the above low power consumption system, including:

powering the normally open GPIO module based on an output voltage of the external power supply;

powering the normally open function module based on an output voltage of the power converter;

the normally open function module is used for controlling the first switch module to be turned on or off, so as to control the turn-off GPIO module to be powered on or off;

and controlling the second switch module to be turned on or turned off based on the normally open functional module, and further controlling the turn-off functional module to be powered on or powered off.

Optionally, when the first switch control signal controls the first switch module to be turned on, power is supplied to the off GPIO module based on an output signal of the external power supply; when the first switch control signal controls the first switch module to be closed, the turn-off GPIO module is powered off; when the second switch control signal controls the second switch module to be conducted, power is supplied to the turn-off functional module based on the output signal of the power converter; and when the second switch control signal controls the second switch module to be closed, the shutdown functional module is powered off.

The low-power consumption system, the microcontroller and the chip have the following beneficial effects:

1. the low-power-consumption system, the microcontroller and the chip distinguish a circuit which can be turned off from a circuit which is required to be normally opened according to different functions of power-consumption devices, and further selectively disconnect the turn-off module, so that the power consumption of the system is further reduced, and the power consumption of the system is maintained at 3 uA-4 uA at 25 ℃.

2. The low-power consumption system, the microcontroller and the chip are provided with different types of switches so as to realize the low-power consumption application with various switchable modes according to different requirements of users.

3. The low-power consumption system, the microcontroller and the chip have simple structures, and the low-power consumption control method is simple and convenient and can be effectively applied to the field of microcontrollers.

Drawings

Fig. 1 is a schematic diagram of a low power system according to the present utility model.

FIG. 2 is a diagram showing the internal framework of a microcontroller

Fig. 3 shows an internal structure diagram of the power management unit.

Fig. 4 shows a timing diagram for the MTCMOS switch turn-on and turn-off process.

Description of element reference numerals

0. External power supply

1. Low power consumption system

11. First power domain

111. First switch module

112. Normally open GPIO module

113. GPIO module capable of being turned off

12. Second power domain

121. Power converter

122. Second switch module

123. Normally open functional module

124. Functional module capable of being turned off

124a MTCMOS switch

124b CPU unit

124c security element

124d peripheral unit

124e SRAM cell

Detailed Description

Other advantages and effects of the present utility model will become apparent to those skilled in the art from the following disclosure, which describes the embodiments of the present utility model with reference to specific examples. The utility model may be practiced or carried out in other embodiments that depart from the specific details, and the details of the present description may be modified or varied from the spirit and scope of the present utility model.

Please refer to fig. 1-4. It should be noted that, the illustrations provided in the present embodiment merely illustrate the basic concept of the present utility model by way of illustration, and only the components related to the present utility model are shown in the drawings and are not drawn according to the number, shape and size of the components in actual implementation, and the form, number and proportion of the components in actual implementation may be arbitrarily changed, and the layout of the components may be more complex.

Methods for reducing power consumption of chip systems are various, and are specifically classified into the following categories:

(1) Clock Gating (Clock Gating): the clock signal of the circuit module not requiring the clock signal is turned off to reduce power consumption.

(2) Power Gating (Power Gating): the power supply of the circuit module which is not needed to be used is turned off to reduce the power consumption.

(3) Logic gate bank optimization technique (Library Optimization): appropriate logic gate banks are used to optimize power consumption and performance of the circuit.

(4) Dynamic Voltage Frequency Scaling (DVFS): the chip is divided into a plurality of voltage domains and clock driving with various frequencies is provided for the circuit, and the CPU automatically adjusts the voltage and the frequency in the work of the chip so as to achieve the purpose of reducing the power consumption.

(5) Multiprocessor architecture design (Multi-Processor Architecture Design): the multiprocessor architecture is used to balance the load, thereby achieving the effect of reducing the power consumption.

However, dynamic Voltage Frequency Scaling (DVFS) and multiprocessor architecture design (Multi-Processor Architecture Design) are mainly applied to large-scale SOC chips due to high cost, and low-Power design is mainly implemented by Clock Gating (Clock Gating), power Gating (Power Gating), and logic gate bank optimization (Library Optimization) for MCU-level SOCs. The logic gate library optimization technology (Library Optimization) is simple, and low-power-consumption devices can be selected by comparing power consumption of devices such as IO, SRAM, STD cell and the like provided by a wafer factory during chip early evaluation, so that the purpose of low power consumption is achieved. The Clock Gating (Clock Gating) needs to be adjusted according to the application, and the overall idea is simpler, namely: when the chip is in a low power consumption state, all clock signals except the circuits which need to be powered are turned off, and the clock frequency is reduced to the minimum, so that the purpose of low power consumption is achieved. However, clock Gating (Clock Gating) and logic gate bank optimization (Library Optimization) can only turn off circuit dynamic power consumption and cannot turn off circuit static power consumption.

Thus, power Gating (Power Gating) is preferred to achieve both static and dynamic Power consumption off. Although the Power Gating technology (Power Gating) has a plurality of implementation methods, the Power consumption of the current large MCU which can be turned off at the temperature of 25 ℃ is generally about 10uA, and some of the Power consumption is even more than 20uA, so that a large optimization space still exists.

Based on the above, the utility model provides a low-power consumption system for providing an ultra-low power consumption design scheme suitable for medium and large-scale MCUs.

Example 1

As shown in fig. 1 and 2, the present embodiment provides a low power consumption system 1, including: a first switch module 111, a normally-on GPIO (General purpose input/output) module 112, a turn-off GPIO module 113, and a power converter 121, a second switch module 122, a normally-on function module 123, and a turn-off function module 124 in the second power domain 12, which are located in the first power domain 11.

As shown in fig. 1, an external power source 0 is used to provide an input voltage. In the present embodiment, the external power supply 0 is disposed outside the low power consumption system 1, and the operation voltage of each GPIO circuit inside the low power consumption system 1 is 3.3V, that is: the first power domain 11 is a 3.3V power domain, and the working voltages of the turn-off GPIO module 113 and the normally-on GPIO module 112 in the first power domain 11 are 3.3V; the supply voltage of other functional modules (such as a CPU unit and an SRAM unit) in the chip is 0.8V, namely: the second power domain 12 is a power domain of 0.8V, and the operating voltages of the turn-off function module 124 and the normally-on function module 123 in the second power domain 12 are both 0.8V.

As shown in fig. 1, the first power domain 11 includes a first switch module 111, a normally-on GPIO module 112, and a turn-off GPIO module 113.

Specifically, the first end of the first switch module 111 is connected to the external power supply 0, the second end is connected to the off GPIO module 113, the control end is connected to the output end of the normally open functional module 123, and the off GPIO module 113 is controlled to be powered on or powered off based on a first switch control signal output by the normally open functional module 123.

More specifically, the first switch module 111 is configured as an LDO, where the LDO can be used as a switch while guaranteeing stability of an output voltage, and the area of a device is smaller than that of DCDC, so that the integration level of the device can be improved on the premise of guaranteeing low power consumption. It should be noted that other power switches having a switching function may be provided, for example: a relay, a MOS transistor, and the like, any power switch capable of implementing switching between the off state and the operating state of the off GPIO module 113 based on the first switch control signal belong to the protection scope of this embodiment.

Specifically, the input terminal of the off GPIO module 113 is connected to the second terminal of the first switch module 111. When the first switch module 111 is turned on, the turn-off GPIO module 113 is converted from the power-off state to the power-on state, so that the system can turn off the turn-off GPIO module 113 when the turn-off GPIO module 113 is not used, thereby ensuring low power consumption of the system.

Specifically, the input end of the normally open GPIO module 112 is connected to the output end of the external power supply 0, and the external power supply 0 directly supplies power to the normally open GPIO module 112, so as to ensure that the normally open GPIO module 112 always maintains an operating state. The normally open GPIO module 112 includes a plurality of GPIO circuits for waking up the off GPIO module and the off function module, and in this embodiment, at least 8 normally open GPIO circuits are maintained.

As shown in fig. 1 and 2, the second power domain 12 includes a power converter 121, a second switching module 122, a normally open function module 123, and a shutdown function module 124.

Specifically, the input end of the power converter 121 is connected to the external power source 0, and the output end of the power converter is respectively connected to the second switch module 122 and the normally open function module 123, so that the voltage output by the external power source 0 is converted into the power supply voltage corresponding to the second switch module 122 and the normally open function module 123. The power converter 121 directly supplies power to the normally-open functional module 123, so that stable operation of the normally-open functional module 123 is ensured.

More specifically, for the purpose of stabilizing the power supply of the subsequent module, the power converter 121 is set to be DCDC or LDO, so that the voltage can be effectively stabilized, and the ripple output interference of the power supply can be effectively filtered. In the present embodiment, the power consumption of the present embodiment can be further saved by setting DCDC as the power converter. The output voltage set by the power converter 121 is 0.8V. The LDO converts 3.3V into 0.8V with only 24% of power conversion rate, whereas the power converter 121 converts 3.3V of the external power source 0 into 0.8V, and the power conversion rate can reach 70%.

It should be noted that, the power converter 121 may be configured as any circuit structure capable of converting the power voltage, so long as the power converter 121 can convert the voltage of the external power source 0 into a suitable voltage and supply power to the subsequent modules, which is a protection scope of the present embodiment.

Specifically, the first end of the second switch module 122 is connected to the power converter 121, the second end is connected to the turn-off functional module 124, the control end is connected to the output end of the normally open functional module 123, and the turn-off functional module 124 is controlled to be powered on or powered off based on a second switch control signal output by the normally open functional module 123.

More specifically, the second switching module 122 is mainly used as a switching device, so the second switching module 122 may be configured as an LDO, DCDC or other power switch having a switching function, such as: relays, MOS transistors, etc., any power switch capable of implementing switching between the off state and the on state of the off-state functional module 124 based on the control signal of the second switch module 122 belongs to the protection scope of the present embodiment. Preferably, in order to further save the area of the device and ensure the stability of the output voltage, an LDO is selected as the second switching module 122 in the present embodiment.

Specifically, the input end of the shutdown function module 124 is connected to the output end of the second switch module 122, so as to ensure that the shutdown function module 124 is powered on or powered off based on the on or off of the second switch module 122.

As an example, as shown in fig. 1, the shutdown function module 124 includes an SRAM (static random access memory) unit, K MTCMOS switches, and K functional units; k is an integer greater than or equal to 1. The first end of each MTCMOS switch is connected to the second end of the second switch module 122, and the second end is connected to a corresponding functional unit, and the corresponding functional unit is controlled to be powered on or powered off based on the MTCMOS control signal output by the normally-on functional module 123.

In the present embodiment, as shown in fig. 1, the off-state functional module 124 includes 3 MTCMOS switches 124a and 3 functional units. Each functional unit is respectively configured as a CPU (central processing unit) unit 124b, a security unit 124c, and a peripheral unit 124d, and is powered on or off through a corresponding MTCMOS switch, so as to control each functional unit to be turned on or off to meet the requirements of different devices on functions.

In this embodiment, in order to ensure quick start of the system in some application scenarios, an input end of the SRAM cell 124e is connected to an output end of the second switch module 122, and the SRAM cell 124e is controlled to be powered on or powered off based on the second switch control signal. The SARM unit 124e is directly connected to the output of the second switch module 122, so that when the CPU unit 124b is turned off by the MTCMOS switch, instructions and data are stored in the SARM unit 124e without power failure, and when the CPU unit 124b is driven again to operate, the CPU unit 124b can directly obtain the instructions and data stored in the SARM unit 124e with power failure.

As another example, the turn-off functional module 124 further includes an MTCMOS switch connected between the SRAM cell 124e and the second switch module 122, which controls the SRAM cell 124e to be powered on or off based on the MTCMOS control signal. Namely: the turn-off functional block 124 includes an SRAM cell 124e, k+1 MTCMOS switches, and K functional units. K is an integer greater than or equal to 1. The first to kth MTCMOS switches have first ends connected to the second ends of the second switch module 122, and second ends connected to corresponding functional units. A first terminal of the (k+1) th MTCMOS switch is connected to the second terminal of the second switch module 122, and a second terminal is connected to the SRAM cell 124e. Each functional unit and SRAM cell 124e is powered on or off through a corresponding MTCMOS switch.

It should be noted that, the SRAM cell and each functional unit in the shutdown functional module 124 may not be provided with a corresponding MTCMOS switch, but may be directly connected to the second switch module 122, so that all the cells (SRAM cell and each functional unit) in the shutdown functional module 124 are powered on or off at the same time based on the on or off of the second switch module 122.

Specifically, the normally open functional module 123 is directly connected to the output terminal of the power converter 121, and is powered by the power converter 121, so that the operating state is always maintained. In order to further reduce the power consumption of the system, the circuits in the normally open functional module 123 should be relatively simplified on the basis that each of the shutdown functional modules 124 of the system is guaranteed to be awakened. In this embodiment, as shown in fig. 2, the normally open function module 123 is configured to at least include a power management unit PMU, and the power management unit PMU generates a first switch control signal and a second switch control signal, so as to control the first switch module 111 and the second switch module 122 to be turned on or off respectively.

More specifically, in the present embodiment, as shown in fig. 3, the power management unit PMU includes a register module pmu_cfg, a counter module pmu_cnt, and a state machine pmu_fsm. The register module PMU_CFG is used for configuring parameter settings of the power management unit PMU through APB interface, such as calculator step length of the counter module PMU_CNT, parameters of LDO and signals controlled by the CPU unit, and power-on and power-off time sequences are generated in a software mode. The counter module PMU_CNT counts after receiving the corresponding control signals, and the control time sequence of power-on and power-off is marked according to the step length and the number of the counts; the state machine PMU_FSM is used for receiving various switch control signals and outputting control signals (namely a first switch control signal and a second switch control signal) corresponding to power on or power off in cooperation with the counter module PMU_CNT; the counter module PMU_CNT and the state machine PMU_FSM cooperate to generate power-on and power-off time sequences in a hardware mode.

More specifically, as shown in fig. 2 and 3, in the present embodiment, the normally open function module 123 further includes an internal wake-up source, an external wake-up source, and a power-on reset signal generation circuit POR. The power management unit PMU takes signals of the external awakening source and the internal awakening source as input and takes a first switch control signal and a second switch control signal as output, so that the universality of a low-power-consumption system is ensured, and an ultra-low power consumption scheme is further realized.

As an example, the internal wake-up source is connected to the input end of the power management unit PMU and controls the power management unit PMU to work; in this embodiment, the internal wake-up source is set as the clock control signal generating module, and is used for generating the clock control signal as a wake-up source of the power management unit PMU, so as to drive the power management unit PMU to generate the first switch control signal and the second switch control signal. The internal wake-up source frequency is low, such as 20KHz-45KHz, preferably 32KHz, which reduces the dynamic power consumption of the circuit. In this embodiment, when the internal wake-up source is a high level signal and is input to the power management unit PMU, the power management unit PMU generates a first switch control signal and a second switch control signal to control the first switch module 111 and the second switch module 122 to be turned on respectively; when the internal wake-up source is a low level signal and is input into the power management unit PMU, the power management unit PMU generates a first switch control signal and a second switch control signal to control the first switch module 111 and the second switch module 122 to turn off, respectively

As an example, the external wake-up source is connected to the input terminal of the power management unit PMU, and the external wake-up source drives the power management unit PMU to generate the first switch control signal and the second switch control signal as an externally input signal. In this embodiment, the modes of the external wake-up source and the internal wake-up source driving the power management unit PMU are basically the same, and will not be described in detail here.

As an example, the power-on reset signal generating circuit POR is connected to an input terminal of the power management unit PMU, and is used for resetting the power management unit PMU.

As an example, the normally-on function module 123 further includes a clock signal generating circuit for generating a clock timing, and inputting the clock timing to the power management unit PMU, so as to facilitate the subsequent operations of turning on and off the first switch module 111 and the second switch module 121, and turning on and off the MTCMOS switch based on the clock timing.

The circuit configuration of the normally open functional module 123 may be set according to the actual situation. In this embodiment, the normally-on function module 123 also generates an MTCMOS switch control signal for controlling the matched MTCMOS switch, and further controlling the matched MTCMOS switch in the turn-off module.

The present embodiment provides an expression for calculating power consumption as follows:

I _Total ＝I _DCDC +I _LDO1 + I _GPIO +I _LDO2 + I _POR +I _RTC +I _PMU (1)

wherein I is _Total I is the total power consumption of the low power consumption system of the embodiment _DCDC I is the static power consumption of the power converter 121 _LDO1 I _LDO2 Static power consumption of the first switch module 111 and the second switch module 122 under the working voltage respectively, I _POR Generating static power consumption of the circuit POR at the working voltage for the power-on reset signal, I _RTC Static power consumption of the clock signal generating circuit under the working voltage; i _GPIO Is the total power consumption of the normally open GPIO module 112 (the sum of the power consumption of 8 normally open GPIO circuits in the embodiment) in static power consumption under the input voltage, I _PMU For static power consumption at the power management unit PMU operating voltage.

Generally, the static power consumption of DCDC is about 1uA at the corresponding input voltage, and the power consumption of 8 normally-open GPIO circuits in the normally-open GPIO module 112 is about nA level, but the bias voltage generating circuit therein generates about 1uA static power consumption for controlling the power-on sequence of each normally-open GPIO circuit. The static power consumption of the LDO and the power-on reset signal generating circuit POR is about 1uA, the static power consumption of the clock signal generating circuit RTC is about 0.5uA, and the static power consumption of the power management unit PMU is about 0.5 uA. Under the condition that 3.3V is converted into 0.8V by the power converter 121 and then is supplied to the normally-open functional module 123 and the second switch module 122 according to the present design, assuming that the DCDC conversion rate is 80%, the power consumption of the four modules, i.e. the second switch module 122, the power-on reset signal generating circuit POR, the clock signal generating circuit RTC, and the power management unit PMU, is:

the power consumption of the first switch module 111 and the normally open GPIO module 112 operating at 3.3V voltage is about 1uA, then the final calculation result of equation (1) is:

I _Total ＝1uA+1uA+1uA+0.91uA＝3.91uA。

based on this, the present embodiment flexibly applies DCDC, LDO, MTCMOS switch and Power Gating technology (Power Gating) technologies by subdividing the functional requirements of the MCU when the MCU can be turned off, so as to achieve the ultra-low Power design that the low Power system maintains 3-4 uA in the turn-off mode, which is generally lower than the turn-off Power consumption of the main stream MCU in the current market. In addition, the user can switch the switch of the LDO and the MTCMOS according to different requirements, so that low-power consumption application of multiple modes is realized.

Since each of the functional units and the normally-open functional module 123 requires a supply voltage of 0.8V, the embodiment includes at least one second power domain 12 for supplying each of the functional units and the normally-open functional module 123 with 0.8V. In practice, other power domains with different voltages can be set according to the power supply requirements of different functional units, and corresponding settings can be performed according to the settings and connection relations of the modules in the second power domain. For example, if other functional units in the low power consumption system still need a supply voltage of 1.2V, the third power domain is set to a voltage of 1.2V, and accordingly, the third power domain is substantially the same as the second power domain 12 in this embodiment (all the power converters 121, the second switch module 122, the normally open functional module 123, and the normally open functional module 124 are disposed and the connection relationship between each module and the second power domain is also substantially the same), which will not be described herein.

As shown in fig. 1, the present embodiment further provides a microcontroller, including: the low power consumption system 1 of the present embodiment.

As shown in fig. 1, this embodiment further provides a chip, including: the low power consumption system 1 of the present embodiment.

As shown in fig. 1, this embodiment further provides a low power consumption control method, which is implemented based on the low power consumption system 1, and includes:

the normally open GPIO module 112 is powered based on the output voltage of the external power source, so that the normally open GPIO module 112 is always in an operating state. The normally-open function module 123 is powered based on the output voltage of the power converter 121, so that the normally-open function module 123 is always in an operating state. The normally open function module 123 controls the first switch module 111 to be turned on or turned off, so as to control the turn-off GPIO module 113 to be powered on or off, so that the turn-off GPIO module 113 is ensured to be turned off when not in use, the system power consumption is saved, and the power is obtained when in use, so that the system is ensured to work normally; based on the normally open function module 123, the second switch module 122 is controlled to be turned on or turned off, so that the turn-off function module 124 is controlled to be powered on or off, and the turn-off function module 124 is ensured to be turned off when not in use, so that the system power consumption is saved, and the power is obtained when in use, so that the normal operation of the system is ensured.

More specifically, when the first switch control signal controls the first switch module 111 to be turned on, the power is supplied to the off GPIO module 113 based on the output signal of the external power supply 0; when the first switch control signal controls the first switch module 111 to be turned off, the turn-off GPIO module 113 is powered off; when the second switch control signal controls the second switch module 122 to be turned on, the power supply to the turn-off functional module 124 is provided based on the output signal of the power converter 121; the turn-off function module 124 is powered off when the second switch control signal controls the second switch module 122 to be turned off.

The following analysis is made of the process of the normally open function module 123 controlling the switch:

in this embodiment, the DCDC and LDO are relatively simple to power up and power down, and control can be accomplished by only writing a control level through the power management unit PMU and inputting the level to the DCDC and LDO. Therefore, the normally open function module 123 is provided with a power management unit PMU, and the first switch control signal and the second switch control signal are generated based on the power management unit PMU, so as to respectively control the first switch module 111 and the second switch module 122 to be turned on or off.

Meanwhile, in this embodiment, as shown in fig. 1, the shutdown functional module 124 includes 3 functional units and corresponding MCTMOS switches. The power management unit PMU is used for controlling the on or off of the MTCMOS switch, so that the on or off of each functional unit can be ensured according to different conditions. The timing chart of the switch control of each MTCMOS switch in the turn-off functional module 124 is shown in fig. 4, wherein t1 to t5 are the power management unit PMU controlling the turn-off process of the MTCMOS switch; t6 to t10 are the power management unit PMU controlling the conduction process of the MTCMOS switch.

At time t1, the clock enable signal clk_en in the MTCMOS switch is switched to the low level (valid when the clock enable signal clk_en is at the high level), and therefore the clock enable signal in the MTCMOS switch is disabled; at time t2, the isolation signal isolation_n in the MTCMOS switch is switched to be low level (effective), and the output signal is isolated, so that normal power off in the power off process is ensured; at time t3, the reset signal reset_n is set to low level (active), resetting the MTCMOS switch; at time t4, the power management unit PMU switches the control signal power_switch_en of the MTCMOS switch to a high level signal, so that the MTCMOS switch is turned off; at time t5, the MTCMOS switch feeds back the shutdown completion signal pdn_seq_done, and the shutdown completion signal pdn_seq_done is pulled high indicating that the MTCMOS switch is shutdown.

At time t6, the power management unit PMU switches the control signal power_switch_en of the MTCMOS switch to a low level signal, so that the MTCMOS switch is turned on; at time t7, switching the isolation signal isolation_n in the MTCMOS switch to a high level so as to release the isolation; at time t8, the clock enable signal clk_en in the MTCMOS switch is switched to high level (active); at time t9, the reset of the MTCMOS is released by setting the reset signal reset_n to high level; at time t10, the MTCMOS switch feeds back a conduction completion signal pup_seq_done, and when the conduction completion signal pup_seq_done is pulled high, the MTCMOS switch is turned on.

In summary, the present utility model provides a low power system, a microcontroller and a chip, including: the power supply comprises a first switch module, a normally open GPIO module, a shutoff GPIO module, a power converter, a second switch module, a normally open functional module and a shutoff functional module; the first switch module is arranged between the external power supply and the turn-off GPIO module, and controls the turn-off GPIO module to be powered on or powered off based on a first switch control signal; the normally open GPIO module and the power converter are connected with an external power supply; the second switch module is arranged between the power converter and the turn-off functional module, and is used for controlling the turn-off functional module to be powered on or powered off based on a second switch control signal; the normally open functional module is connected with the power converter and generates a first switch control signal and a second switch control signal. According to different functions of the power consumption device, the utility model distinguishes a circuit which can be turned off from a circuit which is required to be turned on, so that the turn-off circuit is selectively turned off, and the system power consumption is maintained at 3 uA-4 uA at 25 ℃. Therefore, the utility model effectively overcomes various defects in the prior art and has high industrial utilization value.

The above embodiments are merely illustrative of the principles of the present utility model and its effectiveness, and are not intended to limit the utility model. Modifications and variations may be made to the above-described embodiments by those skilled in the art without departing from the spirit and scope of the utility model. Accordingly, it is intended that all equivalent modifications and variations of the utility model be covered by the claims, which are within the ordinary skill of the art, be within the spirit and scope of the present disclosure.

Claims

1. A low power system, the low power system comprising at least: the power supply comprises a first switch module, a normally open GPIO module, a turn-off GPIO module, a power converter, a second switch module, a normally open functional module and a turn-off functional module;

2. The low power system of claim 1, wherein: the power converter is set to DCDC or LDO.

3. The low power system of claim 1, wherein: the first switch module and the second switch module are both set as LDOs.

4. The low power system of claim 1, wherein: the turn-off functional module comprises an SRAM unit, K MTCMOS switches and K functional units; k is an integer greater than or equal to 1;

the first end of each MTCMOS switch is connected with the second end of the second switch module, the second end of each MTCMOS switch is connected with a corresponding functional unit, and the corresponding functional unit is controlled to be powered on or powered off based on an MTCMOS control signal output by the normally-open functional module;

and the input end of the SRAM unit is connected with the output end of the second switch module, and the SRAM unit is controlled to be powered on or powered off based on the second switch control signal.

5. The low power system of claim 4, wherein: the turn-off functional module further includes an MTCMOS switch connected between the SRAM cell and the second switch module, and the SRAM cell is controlled to be powered on or powered off based on the MTCMOS control signal.

6. The low power system of claim 4 or 5, wherein: each functional unit is a security unit, a CPU unit or a peripheral unit respectively.

7. The low power system of claim 1, wherein: the normally open functional module comprises a power management unit;

the power management unit generates a first switch control signal and a second switch control signal to further control the first switch module and the second switch module to be conducted or closed respectively.

8. The low power system of claim 7, wherein: the normally open functional module further comprises an internal awakening source, an external awakening source and a power-on reset signal generating circuit;

the internal awakening source and the external awakening source are respectively connected with the input end of the power management unit and control the power management unit to work;

the power-on reset signal generating circuit is connected with the input end of the power management unit and is used for resetting the power management unit.

9. A microcontroller, the microcontroller comprising at least: a low power system as claimed in any one of claims 1 to 8.

10. A chip, the chip comprising at least: a low power system as claimed in any one of claims 1 to 8.