CN112083791B - Chip power consumption optimization method and device, computer equipment and storage medium - Google Patents
Chip power consumption optimization method and device, computer equipment and storage medium Download PDFInfo
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- G06F1/32—Means for saving power
- G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
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- G06F1/3287—Power saving characterised by the action undertaken by switching off individual functional units in the computer system
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Abstract
The application relates to a chip power consumption optimization method, a chip power consumption optimization device, computer equipment and a storage medium. By the method and the device, the automatic management process of chip power consumption optimization can be completed, and power consumption can be further saved. The method comprises the following steps: the method comprises the steps that an awakening mode instruction and a power-down mode instruction are respectively stored in an awakening mode register and a power-down mode register, a power-down enabling register is triggered to start a power-down process in response to the power-down mode instruction, and a power domain specified by the power-down mode instruction is controlled to enter a low-power-consumption mode in the power-down process; receiving a wake-up signal generated by a wake-up source corresponding to the wake-up source information; and if the wake-up signal is a valid wake-up signal, controlling the power domain specified by the wake-up mode command to enter the power switch mode.
Description
Technical Field
The present application relates to the field of battery technologies, and in particular, to a method and an apparatus for optimizing chip power consumption, a computer device, and a storage medium.
Background
Along with the development of the internet of things technology, people improve the demand of wearable electronic products, have further requirements on the battery endurance capacity of the wearable electronic products, and are limited by the development of the battery capacity, and the optimization of the power consumption of the chip is more and more emphasized.
There are many techniques for optimizing the power consumption of a chip, and a multi-power domain technique is an effective and widely used technique. The multi-power domain technology divides a chip architecture into a plurality of power domains for supplying power respectively, each power domain can use different voltages for supplying power according to needs, and when a certain power domain does not need to work, the power of the power domain can be turned off, so that the purpose of reducing the power consumption of the chip is achieved.
The current multi-power domain technology is not enough to reduce power consumption when the chip is in some modes, and cannot meet the requirement of people on the cruising ability of the chip at present.
Disclosure of Invention
In view of the foregoing, it is desirable to provide a chip power consumption optimization method, apparatus, computer device and storage medium.
A method for optimizing chip power consumption, the method comprising:
storing the wake mode instruction in a wake mode register; the awakening mode instruction carries awakening source information and a power switch mode which is entered by the chip system after the chip system is awakened;
storing the power down mode instruction in a power down mode register;
responding to the power-down mode instruction, triggering a power-down enabling register to start a power-down process and controlling a power domain specified by the power-down mode instruction to enter a low-power-consumption mode in the power-down process;
receiving a wake-up signal generated by a wake-up source corresponding to the wake-up source information;
and if the wake-up signal is an effective wake-up signal, controlling a power domain specified by the wake-up mode instruction to enter the power switch mode.
In one embodiment, the system on a chip comprises a plurality of power domains; level converters or isolation units are arranged between every two power domains; wherein the content of the first and second substances,
the absolute value of the difference value of the respective power supply voltages of the two power domains is larger than a preset value, and the level converter is arranged between the two power domains under the condition that digital signal communication exists between the two power domains;
digital signal communication is arranged between the two power domains, and the isolation unit is arranged between the two power domains under the condition that one power domain is powered down and the other power domain is not powered down.
In one embodiment, the triggering, in response to the power down mode instruction, a power down enable register to start a power down process and control a power domain specified by the power down mode instruction to enter a low power consumption mode in the power down process includes:
triggering the power-down enabling register to send a power-down enabling signal to a power domain specified by the power-down mode instruction according to the power-down mode instruction, so that a clock signal of the power domain specified by the power-down mode instruction is turned off;
triggering power domain reset designated by the power down mode instruction in response to the clock signal being turned off;
enabling the isolation unit corresponding to the reset power domain appointed by the power down mode instruction, and closing the voltage controller corresponding to the reset power domain appointed by the power down mode instruction.
In one embodiment, the controlling the power domain specified by the wake mode instruction to enter the power switch mode includes:
according to the effective wake-up signal, a voltage controller corresponding to the power domain specified by the wake-up mode instruction is turned on, and the power domain specified by the wake-up mode instruction is reset;
disabling the isolation unit corresponding to the power domain specified by the wake mode instruction after the reset is released;
restarting the clock signal corresponding to the power domain specified by the wake-up mode instruction.
In one embodiment, the chip system comprises a normally-on power domain and a trigger; the method further comprises the following steps:
and under the condition that the awakening source information is invalid, if the power-down mode instruction comprises one of a deep sleep mode or a static memory retention mode, triggering the clock signal of the normally-open power domain to be closed through the trigger.
In one embodiment, after the clock signal triggering the normally-open power domain through the flip-flop is turned off, the method further comprises:
and under the condition that the awakening source information is that the internal awakening signal is invalid and the external awakening signal is valid, the triggered and reset trigger generates a clock enabling signal and sends the clock enabling signal to the normally open power domain so as to enable the normally open power domain to restart the clock signal.
In one embodiment, the chip system comprises a software wake-up register; the method further comprises the following steps:
when the low power consumption mode is one of a flash memory closing mode, a Bluetooth closing mode or a flash memory and Bluetooth simultaneous closing mode, taking the effective wake-up signal as a software wake-up instruction and storing the effective wake-up instruction in the software wake-up register;
according to the software awakening instruction, a voltage controller corresponding to a power domain specified by the software awakening instruction is turned on; the power domain designated by the software awakening instruction is a flash memory power domain or a Bluetooth power domain;
resetting a power domain specified by the software wake-up instruction;
enabling the isolation unit corresponding to the power domain appointed by the software awakening instruction after the software awakening instruction is reset;
and restarting a clock signal corresponding to the power domain specified by the software wake-up instruction.
An apparatus for optimizing chip power consumption, the apparatus comprising:
the wake-up mode instruction storage module is used for storing the wake-up mode instruction in a wake-up mode register; the awakening mode instruction carries awakening source information and a power switch mode which is entered by the chip system after the chip system is awakened;
the power-down mode instruction storage module is used for storing the power-down mode instruction in a power-down mode register;
the power domain power-down module is used for responding to the power-down mode instruction, triggering a power-down enabling register to start a power-down flow and controlling a power domain specified by the power-down mode instruction to enter a low-power-consumption mode in the power-down flow;
the wake-up signal receiving module is used for receiving wake-up signals generated by a wake-up source corresponding to the wake-up source information;
and the power domain awakening module is used for controlling the power domain appointed by the awakening mode instruction to enter the power switch mode if the awakening signal is an effective awakening signal.
A computer device comprising a memory and a processor, the memory storing a computer program, the processor implementing the steps of any of the above chip power consumption optimization methods when executing the computer program.
A computer-readable storage medium, having stored thereon a computer program which, when executed by a processor, implements the steps of any of the above-described chip power consumption optimization methods.
According to the chip power consumption optimization method, the chip power consumption optimization device, the computer equipment and the storage medium, the wake-up mode instruction and the power-down mode instruction are respectively stored in the wake-up mode register and the power-down mode register, the power-down enabling register is triggered to start a power-down process in response to the power-down mode instruction, and a power domain specified by the power-down mode instruction is controlled to enter a low power consumption mode in the power-down process; receiving a wake-up signal generated by a wake-up source corresponding to the wake-up source information; and if the wake-up signal is a valid wake-up signal, controlling the power domain specified by the wake-up mode command to enter the power switch mode. The chip power consumption optimization method includes the steps that corresponding awakening mode instructions or power-down mode instructions are stored in a preset register in advance, the chip power consumption optimization method enters a corresponding low power consumption mode under the trigger of the power-down mode instructions, and enters a corresponding power switch mode under the trigger of specified awakening signals and the awakening mode instructions, so that the automatic management process of chip power consumption optimization is completed, and the chip power consumption can be further saved.
Drawings
FIG. 1 is a diagram of a power domain architecture of a chip according to an embodiment of a method for optimizing power consumption of the chip;
FIG. 2 is a flow diagram illustrating a method for optimizing power consumption of a chip according to an embodiment;
FIG. 3 is a schematic diagram of an embodiment of a flip-flop;
FIG. 4 is a flow chart illustrating a method for optimizing chip power consumption according to another embodiment;
FIG. 5 is a block diagram showing the structure of a chip power consumption optimizing apparatus according to an embodiment;
FIG. 6 is a diagram illustrating an internal structure of a computer device according to an embodiment.
Detailed Description
In order to make the objects, technical solutions and advantages of the present application more apparent, the present application is described in further detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the present application and are not intended to limit the present application.
The chip power consumption optimization method provided by the application can be applied to a chip power domain architecture as shown in fig. 1. The whole chip system is divided into 5 power domains, namely a power domain 1(Always-on domain, normally open power domain), a power domain 2 (latency SRAM domain, static memory power domain), a power domain 3(CORE domain, CORE power domain), a power domain 4(BLE domain, bluetooth power domain), and a power domain 5(FLASH domain, FLASH power domain), wherein each power domain adopts respective voltage to supply power, as shown in fig. 1.
The power domain 1(Always-on domain) is powered by an external power supply VCC, and the power supply voltage is 1.8V-3.6V. The power supply of power domain 1 is normally on. The power domain 1 comprises a Power Management Unit (PMU) and also a controller (AON) of the power management unit. The power management unit PMU mainly includes a voltage controller of power domain 2 (LPLDO _ SRAM), a voltage controller of power domain 3 (MLDO _ CORE), a voltage controller of power domain 4 (MLDO _ RF), and a voltage controller of power domain 5 (LPLDO _ FLASH). Wherein the voltage controller LPLDO _ SRAM of the power domain 2 outputs 1.2V voltage to the power domain 2, the voltage controller MLDO _ CORE of the power domain 3 outputs 1.2V voltage to the power domain 3, the voltage controller MLDO _ RF of the power domain 4 outputs 1.3V voltage to the power domain 4, and LPLDO _ FLASH outputs 1.2V voltage to the power domain 5.
In an embodiment, as shown in fig. 2, a flowchart of a method for optimizing chip power consumption is provided, which is described by taking an example of applying the method to a power domain 3(CORE domain) in fig. 1, and includes the following steps:
step S201, storing the wake-up mode command in a wake-up mode register (WUR); the wake-up mode command carries wake-up source information and a power switch mode that the chip system enters after the chip system is woken up.
Wherein, a CPU (central processing unit) in the Power domain 3(CORE domain) is provided with different registers, including a Wake Up mode Register (WUR), a Power down mode Register (POFFR, Power Off Register) and a Power down Enable Register (POER); the wake-up mode instruction refers to an instruction for converting a designated power domain from a low power consumption state to a normal operating state; the power-down mode instruction is an instruction for converting a normal working state into a low power consumption state; the power switch mode is a power domain switch mode combination mode generated on the premise of following a certain principle aiming at the whole chip system.
In this embodiment, taking the chip system shown in fig. 1 as an example, the following principles are followed to enable the 5 power domains shown in fig. 1 to be powered down and powered up:
1. the power supply of the power domain 1 is normally open and cannot be powered down;
2. when the power domain 3 is not powered down, the power domain 2 cannot be powered down;
3. when the power domain 3 is not powered down, the power domain 4 and the power domain 5 can independently select power down or power off;
4. when the power domain 3 is powered down, the power domain 2 can select power down or not;
5. when power domain 3 is powered down, power domain 4 and power domain 5 must be powered down.
According to the principle described above, there are six power switch modes after the system is connected to the power supply, which are:
1. a normal operating mode (SYSTEM ON), that is, all power domains are in a normal operating state, and no power domain is powered down;
2. a FLASH OFF mode (FLASH OFF), namely only the power domain 5 is powered OFF, and other power domains work normally;
3. a Bluetooth shutdown mode (BLE OFF), namely, only the power domain 4 is powered down, and other power domains work normally;
4. a FLASH & Bluetooth closing mode (FLASH & BLE OFF), namely a power domain 4 and a power domain 5 are powered OFF, and the other power domains work normally;
5. a deep sleep mode (DEEP SLEEP) in which power domain 2, power domain 3, power domain 4, and power domain 5 are powered down and only power domain 1 is operating;
6. the SRAM RETENTION mode (SRAM RETENTION), when power domain 3, power domain 4, and power domain 5 are powered down, power domain 1 and power domain 2 operate.
In one power-on or power-off process, the conversion relationship between each two power switch modes is shown as the following table:
TABLE 1 Power switch mode conversion relationship
As shown in the above table (table 1), the switching relationships between each two switching modes of the power supply have 26 kinds (the number of √ points in the table) and can be simplified into the following 13 switching relationships:
1、SYSTEM ON<-->BLE OFF；
2、SYSTEM ON<-->FLASH OFF；
3、SYSTEM ON<-->FLASH&BLE OFF；
4、SYSTEM ON<-->DEEP SLEEP；
5、SYSTEM ON<-->SRAM RETENTION；
6、BLE OFF<-->FLASH&BLE OFF；
7、BLE OFF<-->DEEP SLEEP；
8、BLE OFF<-->SRAM RETENTION；
9、FLASH OFF<-->FLASH&BLE OFF；
10、FLASH OFF<-->DEEP SLEEP；
11、FLASH OFF<-->SRAM RETENTION；
12、FLASH&BLE OFF<-->DEEP SLEEP；
13、FLASH&BLE OFF<-->SRAM RETENTION。
in addition, the chip power consumption optimization method can also preset wake-up source information, wherein the wake-up source information comprises an internal wake-up signal and an external wake-up signal, the internal wake-up signal can be a clock signal set at regular time, and the external wake-up signal can be a chip wake-up operation caused by an external event, such as an external key set by a user triggering a chip system.
In this step, the CPU receives a wake-up mode instruction preset by a user and stores the wake-up mode instruction in a wake-up mode register (WUR), for example, if a power switch mode entered by a preset wake-up SYSTEM is SYSTEM ON and is external wake-up valid, the instruction corresponding to the mode is stored in the wake-up mode register (WUR).
Step S202, storing the power down mode instruction in a power down mode register (POFFR).
Specifically, for example, the preset power down mode command is to start power down after a preset time period or start power down under the action of a signal triggered by a user, and enter a BLE OFF mode, and then the command is stored in a power down mode register (POFFR).
Step S203, responding to the power down mode instruction, triggering a power down enabling register (POER) to start a power down process and controlling a power domain appointed by the power down mode instruction to enter a low power consumption mode in the power down process.
Specifically, when a preset clock signal comes or under the action of a user trigger key, the power down enable register is triggered, the chip system starts a power down process, and controls the corresponding power domain to enter the low power consumption mode according to the power down mode instruction in the power down process, for example, the power domain 4, namely the bluetooth power domain, is controlled to enter the low power consumption mode according to a BLE OFF mode in the power down mode instruction, namely, the power domain 4 is turned OFF.
Step S204, receiving a wake-up signal generated by a wake-up source corresponding to the wake-up source information;
specifically, the chip receives a wake-up signal specified by the wake-up source information, such as an external wake-up signal or an internal wake-up signal specified by the wake-up source information, where the internal wake-up signal may be a clock signal set at a fixed time, and the external wake-up signal may be a chip wake-up operation caused by an external event, such as a user triggering an external key set by the chip system.
In step S205, if the wake-up signal is an active wake-up signal, the power domain specified by the wake-up mode command is controlled to enter the power switch mode.
Specifically, whether a current wake-up signal is a valid wake-up signal is judged according to wake-up source information preset by a wake-up mode instruction, if the current wake-up signal is the valid wake-up signal, the chip SYSTEM is controlled to enter a specified power switch mode according to a wake-up mode instruction prestored in a wake-up mode register (WUR), and for example, if the pre-specified power switch mode is SYSTEM ON, the chip SYSTEM is awakened from the BLE OFF mode to the SYSTEM ON mode under the triggering of the valid wake-up signal.
In the embodiment, the wake-up mode instruction and the power-down mode instruction are respectively stored in the wake-up mode register and the power-down mode register, the power-down enabling register is triggered to start the power-down process and control the power domain specified by the power-down mode instruction to enter the low-power mode in the power-down process in response to the power-down mode instruction; receiving a wake-up signal generated by a wake-up source corresponding to the wake-up source information; and if the wake-up signal is a valid wake-up signal, controlling the power domain specified by the wake-up mode command to enter the power switch mode. The chip power consumption optimization method includes the steps that corresponding awakening mode instructions or power-down mode instructions are stored in a preset register in advance, the chip power consumption optimization method enters a corresponding low power consumption mode under the trigger of the power-down mode instructions, and enters a corresponding power switch mode under the trigger of specified awakening signals and the awakening mode instructions, so that the automatic management process of chip power consumption optimization is completed, the chip power consumption is reduced, and power resources are saved.
In one embodiment, a system-on-a-chip includes a plurality of power domains; level converters or isolation units are arranged between every two power domains; the absolute value of the difference value of the respective power supply voltages of the two power domains is larger than a preset value, and a level converter is arranged between the two power domains under the condition that digital signals are communicated between the two power domains; digital signal communication is arranged between the two power domains, and an isolation unit is arranged between the two power domains under the condition that one power domain is powered down and the other power domain is not powered down.
Specifically, a chip system includes a plurality of power domains, for example, the chip system shown in fig. 1 has 5 power domains, and since there is a significant difference in supply voltage between some power domains, there are signal connections between them, and there may be a case where one of the two power domains having the signal connections is powered down and the other is not powered down, a Level Shifter (Level Shifter) and an Isolation unit (Isolation Cell) need to be used between the power domains. The principle followed to insert Level Shifter and Isolation cells is: assuming that two power domains with signal connection are a power domain A and a power domain B, if the power supply voltages of the power domain A and the power domain B have obvious difference, a Level Shifter needs to be inserted between the two power domains for signals connected between the power domains A and B; if power domain A is powered down and power domain B is not powered down, then the signal output by power domain A to power domain B will insert the Isolation Cell between the two power domains, and vice versa.
As shown in fig. 1, according to the principle of inserting Level Shifter and Isolation Cell described above, since the supply voltage of power domain 1 is significantly higher than those of the other three power domains, and power domain 1 has only signal connection with power domain 3, the signal connecting power domain 1 and power domain 3 needs to insert a Level Shifter (Level Shifter) between the two power domains; in addition, power domain 1 is normally open, so that there is a case that power domain 3 is powered down and power domain 1 normally operates, so that an Isolation Cell (Isolation Cell) needs to be inserted between the two power domains for signals output by power domain 3 to power domain 1, and an Isolation Cell does not need to be inserted for signals output by power domain 1 to power domain 3. The power supply voltages of the power domains 2, 3, 4 and 5 are the same or similar, so that Level Shifter is not required for signal transmission among the three power domains. According to the six power switch modes, the power domain 2 is only in signal connection with the power domain 3, and the power domain 2 is not in power failure (SRAM RETENTION), so that the signal output by the power domain 3 to the power domain 2 normally needs to be inserted into the Isolation Cell, but before the SRAM RETENTION is entered, the CPU sets the SRAM in the power domain 2 to be in a preservation mode (Retention mode), after the system enters the SRAM RETENTION, only the SRAM in the power domain 2 is supplied with power, other logic circuits are not supplied with power, the signal output by the power domain 3 to the power domain 2 is only connected to the logic circuit and is not connected to the SRAM, and therefore the signal output by the power domain 3 to the power domain 2 does not need to be inserted into the Isolation Cell; since there is no power down of power domain 2 but no power down of power domain 3, the signal output by power domain 2 to power domain 3 does not need to be inserted into the Isolation Cell either. The power domain 4 is only in signal connection with the power domain 3, and according to the six power switch modes, the power domain 4 is powered down and the power domain 3 is not powered down, so that the signal output by the power domain 4 to the power domain 3 needs to insert an Isolation Cell between the two power domains; since there is no power down of power domain 3 but no power down of power domain 4, the signal output by power domain 3 to power domain 4 does not need to be inserted into the Isolation Cell. Power domain 5, as in the case of power domain 4, also requires that the Isolation Cell be inserted between power domain 5 and power domain 3 for the signals output by power domain 5.
In the embodiment, a certain principle is set to insert the level shifter or the isolation unit between the corresponding power domains, so that the cooperative work among different power domains is ensured, and the situation that one power domain is powered off and the other associated power domain cannot work normally is avoided.
In an embodiment, the step S203 includes: according to the power-down mode instruction, triggering a power-down enabling register (POER) to send a power-down enabling signal to a power domain specified by the power-down mode instruction so as to close a clock signal of the power domain specified by the power-down mode instruction; triggering power domain reset designated by the power down mode instruction in response to the clock signal being turned off; enabling the isolation unit corresponding to the reset power domain appointed by the power down mode instruction, and closing the voltage controller corresponding to the reset power domain appointed by the power down mode instruction.
Specifically, according to the power switch mode entered after the power down set in step S202, the CPU firstly turns off the clock of the power domains requiring power down, secondly resets the power domains, secondly enables the Isolation cells associated therewith, and finally turns off the voltage controllers in the power domains 1 corresponding to the power domains, so as to turn off the power domains requiring power down.
According to the embodiment, the power-down process of the power domain is orderly completed by sequentially controlling the clock of the power domain needing power down, the power domain reset, the isolation unit enable and the voltage controller to be turned off in the power-down process, so that the power consumption of a chip is reduced, and the normal work of other power domains is ensured.
In an embodiment, the step S205 includes: according to the effective wake-up signal, a voltage controller corresponding to the power domain specified by the wake-up mode instruction is opened, and the power domain specified by the wake-up mode instruction is reset; disabling the isolation unit corresponding to the power domain specified by the wake-up mode instruction after the reset is released; and restarting a clock signal corresponding to the power domain specified by the wake-up mode instruction.
Specifically, when the required wake-up signal is valid, the CPU, according to the power switch mode entered by the system after wake-up set in step S201, first turns on the voltage controller in the power domain 1 corresponding to the power domain to be powered on, then disables the Isolation cell associated with the power domain, then resets the power domains, and finally turns on the clock of the power domain to be powered on, so that the power domain to be powered on returns to normal operation.
In the embodiment, the voltage controller of the power domain to be powered on, the related isolation unit disabling, the power domain reset and the clock opening are sequentially turned on in the wake-up process, so that the wake-up process of the power domain is completed, and meanwhile, the normal work of other power domains is ensured.
In one embodiment, as shown in FIG. 3, a system-on-chip includes a normally-on power domain and a flip-flop; the chip power consumption optimization method further comprises the following steps:
and under the condition that the awakening source information is invalid due to the internal awakening signal, if the power-down mode instruction comprises one of a deep sleep mode or a static memory reserved mode, triggering the clock signal of the normally-open power domain to be closed through a trigger.
Specifically, in order to turn off the clock of the power domain 1 when the system is in the deep sleep mode DEEP SLEEP or the static memory RETENTION mode SRAM RETENTION, and turn on the clock of the power domain 1 when the external wake-up is active, a D flip-flop with an asynchronous reset terminal is used, as shown in fig. 3. The D end of the D trigger is connected with logic 1; CLK connected (! int _ wu _ en & & system _ off _ flag); the Q end is connected with an inverter, and the inverted signal is an enable signal aon _ clk _ en of aon _ clk; the RESET terminal is connected with an external wake-up signal ext _ wake _ up. Wherein int _ wu _ en is an internal wake-up enable signal, which is 1 when internal wake-up is enabled; system _ off _ flag is a pulse signal. When the system enters DEEP SLEEP or SRAM reset, the system _ off _ flag signal will generate a pulse, if the internal wakeup is not enabled at this time, i.e. int _ wu _ en is 0, the CLK terminal of the D flip-flop receives a pulse, the value of the Q terminal becomes 1, after passing through the inverter, the generated aon _ CLK _ en becomes 0, the enable signal of aon _ CLK becomes 0, and aon _ CLK is turned off.
In the embodiment, the D flip-flop controls the clock signal of the power domain 1 (normally open power domain), and when the chip system is in the deep sleep mode DEEP SLEEP or the static memory RETENTION mode SRAM RETENTION, the clock of the power domain 1 is turned off, so that the system power consumption is further saved.
In an embodiment, after the clock signal triggering the normally-on power domain through the flip-flop is turned off, the chip power consumption optimization method further includes:
and under the condition that the awakening source information is that the internal awakening signal is invalid and the external awakening signal is valid, the triggered and reset trigger generates a clock enabling signal and sends the clock enabling signal to the normally open power domain so as to restart the clock signal of the normally open power domain.
Specifically, after the clock signal of the normally-open power domain, i.e., power domain 1, is turned off, when the external wake-up signal (ext _ wake _ up) is asserted, the D flip-flop is reset, the value output by the Q terminal becomes 0, after passing through the inverter, the generated aon _ clk _ en becomes 1, aon _ clk is enabled, and normal operation is resumed.
In the above embodiment, the D flip-flop is triggered to reset by the external wake-up signal, so that the clock signal of the power domain 1 is turned on, and the chip system resumes normal operation, so that the chip system is conveniently woken up by the external wake-up signal in the deep sleep mode DEEP SLEEP or the static memory RETENTION mode SRAM RETENTION.
In one embodiment, the system-on-chip includes a Software Wake Up Register (SWUR); the chip power consumption optimization method further comprises the following steps:
when the low power consumption mode is one of a flash memory closing mode, a Bluetooth closing mode or a flash memory and Bluetooth closing mode at the same time, taking an effective wake-up signal as a software wake-up instruction and storing the effective wake-up instruction in a software wake-up register (SWUR); according to the software awakening instruction, a voltage controller corresponding to a power domain specified by the software awakening instruction is turned on; the power domain designated by the software awakening instruction is a flash memory power domain or a Bluetooth power domain; resetting a power domain specified by the software wake-up instruction; enabling the isolation unit corresponding to the power domain appointed by the software awakening instruction after the reset is released; and restarting the clock signal corresponding to the power domain specified by the software wake-up instruction.
Specifically, when one or more power domains are in a powered down state, the system waits for the arrival of a wake-up signal. If internal wake-up is to be used, the CPU needs to set the target count value of the wake-up counter in addition to enabling internal wake-up. When internal wake-up is enabled and the system enters a low power switch mode (one of three power switch modes of BLE OFF, DEEP SLEEP and SRAM RETENTION), the wake-up counter starts counting from 0, when the count value of the wake-up counter reaches a set target count value, an internal wake-up signal is generated, and a certain power domain or certain power domains of the system in a power-down state can be woken up to enter a set wake-up power switch mode. If external awakening is needed, after the system enters a low power switch mode, the state machine AON _ FSM waits for an awakening signal input by an external pin, and when the external awakening signal is effective, a certain power domain or certain power domains of the system in a power-down state can be awakened to enter a set awakened power switch mode. If the system is awakened from a BLE OFF state, a FLASH OFF state or a FLASH & BLE OFF state, because the CPU works normally at the moment, a software awakening mode can be used, specifically, the CPU configures a software awakening register (SWUR) to be a valid value, and then a software awakening signal can be generated to awaken the power domain 4 or the power domain 5. In the awakening process, firstly, the voltage controllers in the power domain 1 corresponding to the power domain needing to be powered on are turned on, then the power domains are reset, and finally the related Isolation cells are disabled, so that the power domain needing to be powered on can recover to work normally.
In the embodiment, the software wake-up register is set, so that a software wake-up mode can be used when the system is woken up from a BLE OFF state, a FLASH OFF state or a FLASH & BLE OFF state, and the method is simpler and more efficient.
As shown in fig. 4, fig. 4 is a schematic diagram of a power-down flow and a power-up flow in an embodiment:
the power down and power up processes of each power domain are controlled by a state machine (AON _ FSM) in the AON in power domain 1, which is located in AON Logic in fig. 1. The control flow is shown in fig. 2.
When the chip is not connected with the power supply, the state machine is in a reset state and waits for power-on. When the chip is powered on for the first time, firstly, the state machine opens a power domain 2 voltage controller, a power domain 3 voltage controller, a power domain 4 voltage controller and a power domain 5 voltage controller in a power domain 1 to respectively supply power to the four power domains;
secondly, the state machine releases reset signals of the power domain 2, the power domain 3, the power domain 4 and the power domain 5;
then, the state machine disables the Isolation Cell between the power domains (the Isolation Cell is in an enabled state when the power is not on);
finally, the SYSTEM enters a normal operating mode (SYSTEM ON).
When some power domains do not need to work, the power supply of the power domains can be switched off. The CPU sets a wake-up source and a power switch mode entered by the system after wake-up in advance through a configuration wake-up mode register (WUR). The wake-up source may select an internal wake-up and an external wake-up. If external wake up is enabled but internal wake up is not enabled, the power domain 1 clock (aon _ clk) is turned off when the system is at DEEP SLEEP or SRAM RETENTION; if internal wake up is enabled, the system needs to wake up internally via wake _ counter in power domain 1, so aon _ clk cannot be turned off. The CPU may configure a power down mode register (POFFR) to select a power switch mode to enter after power down. The CPU starts a power-down process by configuring a power-down enabling register (POER).
In the power down flow, the clock of the power domain to be powered down is first turned off,
second the power domain to be powered down is reset,
the associated Isolation Cell is then enabled,
and finally, closing the voltage controller in the power domain 1 corresponding to the power domain to be powered down.
In a specific scenario, for example, when it is desired to complete the power switch mode transition of SYSTEM ON- > BLE OFF- > SYSTEM ON and use external wake-up, the operation steps are as follows:
step one, a CPU configures a wakeup mode register (WUR), sets a wakeup source as an external wakeup source, and sets a power switch mode entered by a SYSTEM after wakeup as SYSTEM ON;
step two, configuring a power failure mode register (POFFR) by the CPU, and selecting a power switch mode entering after power failure as BLE OFF;
step three, the CPU starts a power-down process by configuring a power-down enabling register (POER);
step four, the hardware closes the clock of the power domain 4, then resets the power domain 4, then enables the Isolation cell between the power domain 4 and the power domain 3, and finally closes the voltage controller in the power domain 1 corresponding to the power domain 4 to power down the power domain 4;
fifthly, the hardware waits for the arrival of an external wake-up signal;
and step six, when the external wake-up signal is effective, the voltage controller in the power domain 1 corresponding to the hardware power domain 4 is turned on, the Isolation cell is de-energized, the power domain 4 is reset, and finally the clock of the power domain 4 is turned on, so that the power domain 4 is restored to normal work.
According to the chip power consumption optimization method in the embodiment, the corresponding wake-up mode instruction or power-down mode instruction is prestored through the preset register, the corresponding low power consumption mode is entered under the trigger of the power-down mode instruction, and the corresponding power switch mode is entered under the trigger of the appointed wake-up signal and the wake-up mode instruction, so that the automatic management process of chip power consumption optimization is completed, the chip power consumption is reduced, and the power source resource is saved.
It should be understood that although the various steps in the flow charts of fig. 1-4 are shown in order as indicated by the arrows, the steps are not necessarily performed in order as indicated by the arrows. The steps are not performed in the exact order shown and described, and may be performed in other orders, unless explicitly stated otherwise. Moreover, at least some of the steps in fig. 1-4 may include multiple steps or multiple stages, which are not necessarily performed at the same time, but may be performed at different times, which are not necessarily performed in sequence, but may be performed in turn or alternately with other steps or at least some of the other steps.
In one embodiment, as shown in fig. 5, there is provided a chip power consumption optimizing apparatus 500, including: an awakening mode instruction storage module 501, a power down mode instruction storage module 502, a power down module 503 of a power domain, an awakening signal receiving module 504 and a power domain awakening module 505, wherein:
an awake mode instruction storage module 501, configured to store an awake mode instruction in an awake mode register; the wake-up mode instruction carries wake-up source information and a power switch mode which the chip system enters after the chip system is awakened.
A power down mode instruction storage module 502, configured to store a power down mode instruction in a power down mode register;
a power domain power down module 503, configured to trigger a power down enable register to start a power down process in response to the power down mode instruction, and control a power domain specified by the power down mode instruction to enter a low power consumption mode in the power down process;
a wake-up signal receiving module 504, configured to receive a wake-up signal generated by a wake-up source corresponding to the wake-up source information;
a power domain wake-up module 505, configured to control the power domain specified by the wake-up mode instruction to enter the power switch mode if the wake-up signal is an effective wake-up signal.
In one embodiment, the system-on-chip includes a plurality of power domains; level converters or isolation units are arranged between every two power domains; wherein the content of the first and second substances,
the absolute value of the difference value of the respective power supply voltages of the two power domains is larger than a preset value, and the level converter is arranged between the two power domains under the condition that digital signal communication exists between the two power domains;
digital signal communication is arranged between the two power domains, and the isolation unit is arranged between the two power domains under the condition that one power domain is powered down and the other power domain is not powered down.
In one embodiment, the power domain power down module 503 is further configured to:
triggering the power-down enabling register (POER) to send a power-down enabling signal to a power domain appointed by the power-down mode instruction according to the power-down mode instruction so as to close a clock signal of the power domain appointed by the power-down mode instruction;
triggering power domain reset designated by the power down mode instruction in response to the clock signal being turned off;
enabling the isolation unit corresponding to the reset power domain appointed by the power down mode instruction, and closing the voltage controller corresponding to the reset power domain appointed by the power down mode instruction.
In an embodiment, the power domain wake module 505 is further configured to:
according to the effective wake-up signal, a voltage controller corresponding to the power domain specified by the wake-up mode instruction is turned on, and the power domain specified by the wake-up mode instruction is reset;
disabling the isolation unit corresponding to the power domain specified by the wake mode instruction after the reset is released;
restarting the clock signal corresponding to the power domain specified by the wake-up mode instruction.
In one embodiment, the chip system includes a normally-on power domain and a flip-flop; the method further comprises the following steps:
and under the condition that the awakening source information is invalid, if the power-down mode instruction comprises one of a deep sleep mode or a static memory retention mode, triggering the clock signal of the normally-open power domain to be closed through the trigger.
In one embodiment, after the clock signal triggering the normally-open power domain through the flip-flop is turned off, the method further comprises:
and under the condition that the awakening source information is that the internal awakening signal is invalid and the external awakening signal is valid, the triggered and reset trigger generates a clock enabling signal and sends the clock enabling signal to the normally open power domain so as to enable the normally open power domain to restart the clock signal.
In one embodiment, the system-on-chip includes a software wake-up register (SWUR); the method further comprises the following steps:
when the low power consumption mode is one of a flash memory off mode, a bluetooth off mode or a flash memory and bluetooth simultaneous off mode, the effective wake-up signal is used as a software wake-up instruction and stored in the software wake-up register (SWUR);
according to the software awakening instruction, a voltage controller corresponding to a power domain specified by the software awakening instruction is turned on; the power domain designated by the software awakening instruction is a flash memory power domain or a Bluetooth power domain;
resetting a power domain specified by the software wake-up instruction;
enabling the isolation unit corresponding to the power domain appointed by the software awakening instruction after the software awakening instruction is reset;
and restarting a clock signal corresponding to the power domain specified by the software wake-up instruction.
For specific limitations of the chip power consumption optimization device, reference may be made to the above limitations of the chip power consumption optimization method, which are not described herein again. The respective blocks in the chip power consumption optimization apparatus may be wholly or partially implemented by software, hardware, and a combination thereof. The modules can be embedded in a hardware form or independent from a processor in the computer device, and can also be stored in a memory in the computer device in a software form, so that the processor can call and execute operations corresponding to the modules.
In one embodiment, a computer device is provided, the internal structure of which may be as shown in FIG. 6. The computer device includes a processor, a memory, and a network interface connected by a system bus. Wherein the processor of the computer device is configured to provide computing and control capabilities. The memory of the computer device comprises a nonvolatile storage medium and an internal memory. The non-volatile storage medium stores an operating system, a computer program, and a database. The internal memory provides an environment for the operation of an operating system and computer programs in the non-volatile storage medium. The database of the computer device is used for storing the command data of the wake-up mode or the power-down mode. The network interface of the computer device is used for communicating with an external terminal through a network connection. The computer program is executed by a processor to implement a method for optimizing chip power consumption.
Those skilled in the art will appreciate that the architecture shown in fig. 6 is merely a block diagram of some of the structures associated with the disclosed aspects and is not intended to limit the computing devices to which the disclosed aspects apply, as particular computing devices may include more or less components than those shown, or may combine certain components, or have a different arrangement of components.
In one embodiment, a computer device is provided, comprising a memory and a processor, the memory having stored therein a computer program, the processor implementing the steps of the above-described method embodiments when executing the computer program.
In an embodiment, a computer-readable storage medium is provided, on which a computer program is stored, which computer program, when being executed by a processor, carries out the steps of the above-mentioned method embodiments.
It will be understood by those skilled in the art that all or part of the processes of the methods of the embodiments described above can be implemented by hardware instructions of a computer program, which can be stored in a non-volatile computer-readable storage medium, and when executed, can include the processes of the embodiments of the methods described above. Any reference to memory, storage, database or other medium used in the embodiments provided herein can include at least one of non-volatile and volatile memory. Non-volatile Memory may include Read-Only Memory (ROM), magnetic tape, floppy disk, flash Memory, optical storage, or the like. Volatile Memory can include Random Access Memory (RAM) or external cache Memory. By way of illustration and not limitation, RAM can take many forms, such as Static Random Access Memory (SRAM) or Dynamic Random Access Memory (DRAM), among others.
The technical features of the above embodiments can be arbitrarily combined, and for the sake of brevity, all possible combinations of the technical features in the above embodiments are not described, but should be considered as the scope of the present specification as long as there is no contradiction between the combinations of the technical features.
The above-mentioned embodiments only express several embodiments of the present application, and the description thereof is more specific and detailed, but not construed as limiting the scope of the invention. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the concept of the present application, which falls within the scope of protection of the present application. Therefore, the protection scope of the present patent shall be subject to the appended claims.
Claims (10)
1. A method for optimizing chip power consumption, the method comprising:
storing the wake mode instruction in a wake mode register; the awakening mode instruction carries awakening source information and a power switch mode which is entered by the chip system after the chip system is awakened;
storing the power down mode instruction in a power down mode register;
responding to the power-down mode instruction, triggering a power-down enabling register to start a power-down process and controlling a power domain specified by the power-down mode instruction to enter a low-power-consumption mode in the power-down process; the method specifically comprises the following steps: triggering the power-down enabling register to send a power-down enabling signal to a power domain specified by the power-down mode instruction according to the power-down mode instruction, so that a clock signal of the power domain specified by the power-down mode instruction is turned off; triggering power domain reset designated by the power down mode instruction in response to the clock signal being turned off; enabling an isolation unit corresponding to the reset power domain specified by the power down mode instruction, and closing a voltage controller corresponding to the reset power domain specified by the power down mode instruction;
receiving a wake-up signal generated by a wake-up source corresponding to the wake-up source information;
and if the wake-up signal is an effective wake-up signal, controlling a power domain specified by the wake-up mode instruction to enter the power switch mode.
2. The method of claim 1, wherein the system-on-a-chip comprises a plurality of power domains; level converters or isolation units are arranged between every two power domains; wherein the content of the first and second substances,
the absolute value of the difference value of the respective power supply voltages of the two power domains is larger than a preset value, and the level converter is arranged between the two power domains under the condition that digital signal communication exists between the two power domains;
digital signal communication is arranged between the two power domains, and the isolation unit is arranged between the two power domains under the condition that one power domain is powered down and the other power domain is not powered down.
3. The method of claim 2, wherein the plurality of power domains comprises a normally-on power domain, a static memory power domain, a core power domain, a bluetooth power domain, and a flash power domain.
4. The method of claim 2, wherein the controlling the power domain specified by the wake mode instruction to enter the power switch mode comprises:
according to the effective wake-up signal, a voltage controller corresponding to the power domain specified by the wake-up mode instruction is turned on, and the power domain specified by the wake-up mode instruction is reset;
disabling the isolation unit corresponding to the power domain specified by the wake mode instruction after the reset is released;
restarting the clock signal corresponding to the power domain specified by the wake-up mode instruction.
5. The method of claim 1, wherein the system-on-a-chip comprises a normally-on power domain and a flip-flop; the method further comprises the following steps:
and under the condition that the awakening source information is invalid, if the power-down mode instruction comprises one of a deep sleep mode or a static memory retention mode, triggering the clock signal of the normally-open power domain to be closed through the trigger.
6. The method of claim 5, wherein after the clock signal triggering the normally-open power domain by the flip-flop is turned off, the method further comprises:
and under the condition that the awakening source information is that the internal awakening signal is invalid and the external awakening signal is valid, the triggered and reset trigger generates a clock enabling signal and sends the clock enabling signal to the normally open power domain so as to enable the normally open power domain to restart the clock signal.
7. The method of claim 2, wherein the system-on-a-chip comprises a software wake-up register; the method further comprises the following steps:
when the low power consumption mode is one of a flash memory closing mode, a Bluetooth closing mode or a flash memory and Bluetooth simultaneous closing mode, taking the effective wake-up signal as a software wake-up instruction and storing the effective wake-up instruction in the software wake-up register;
according to the software awakening instruction, a voltage controller corresponding to a power domain specified by the software awakening instruction is turned on; the power domain designated by the software awakening instruction is a flash memory power domain or a Bluetooth power domain;
resetting a power domain specified by the software wake-up instruction;
enabling the isolation unit corresponding to the power domain appointed by the software awakening instruction after the software awakening instruction is reset;
and restarting a clock signal corresponding to the power domain specified by the software wake-up instruction.
8. An apparatus for optimizing power consumption of a chip, the apparatus comprising:
the wake-up mode instruction storage module is used for storing the wake-up mode instruction in a wake-up mode register; the awakening mode instruction carries awakening source information and a power switch mode which is entered by the chip system after the chip system is awakened;
the power-down mode instruction storage module is used for storing the power-down mode instruction in a power-down mode register;
the power domain power-down module is used for responding to the power-down mode instruction, triggering a power-down enabling register to start a power-down flow and controlling a power domain specified by the power-down mode instruction to enter a low-power-consumption mode in the power-down flow; the method specifically comprises the following steps: triggering the power-down enabling register to send a power-down enabling signal to a power domain specified by the power-down mode instruction according to the power-down mode instruction, so that a clock signal of the power domain specified by the power-down mode instruction is turned off; triggering power domain reset designated by the power down mode instruction in response to the clock signal being turned off; enabling an isolation unit corresponding to the reset power domain specified by the power down mode instruction, and closing a voltage controller corresponding to the reset power domain specified by the power down mode instruction;
the wake-up signal receiving module is used for receiving wake-up signals generated by a wake-up source corresponding to the wake-up source information;
and the power domain awakening module is used for controlling the power domain appointed by the awakening mode instruction to enter the power switch mode if the awakening signal is an effective awakening signal.
9. A computer device comprising a memory and a processor, the memory storing a computer program, characterized in that the processor, when executing the computer program, implements the steps of the method of any of claims 1 to 7.
10. A computer-readable storage medium, on which a computer program is stored, which, when being executed by a processor, carries out the steps of the method of any one of claims 1 to 7.
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| CN114020139A (en) * | 2021-11-05 | 2022-02-08 | 珠海全志科技股份有限公司 | CPU power consumption management method, computer device and computer readable storage medium |
| CN114327651A (en) * | 2021-12-21 | 2022-04-12 | 上海深聪半导体有限责任公司 | Chip wake-up method, system, electronic device and readable storage medium |
| CN114661133A (en) * | 2022-02-25 | 2022-06-24 | 珠海博雅科技股份有限公司 | Chip and method of nonvolatile memory for reducing power consumption |
| CN114637386A (en) * | 2022-03-24 | 2022-06-17 | 南京英锐创电子科技有限公司 | Processing method of low-power-consumption debugging path, debugging system and electronic equipment |
| CN117093535A (en) * | 2022-05-13 | 2023-11-21 | 华为技术有限公司 | System on chip and power-on recovery method of related system |
| CN115118534B (en) * | 2022-06-07 | 2023-11-17 | 合肥移瑞通信技术有限公司 | Low-power-consumption state control method, device, terminal and storage medium of MBB equipment |
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