CN112235850B - Low-power-consumption system and method of Internet of things chip - Google Patents

Abstract

The invention relates to the technical field of chips of the Internet of things, in particular to a low-power consumption system and a low-power consumption method of the chip of the Internet of things, which comprises a PD _ SOC power domain for realizing the main function of a system on a chip; the PD _ BLE power domain realizes the low-power consumption Bluetooth communication function; the PD-RAM power domain realizes the combination of multiple low-power consumption modes such as integral power on and power off, respective retentions and powerdown of each group, and the like; the PD _ LPM power domain realizes global configuration, global clock reset and power consumption management; and the PD _ AON power domain realizes the global configuration, low-frequency clock and global reset, awakening and power/power consumption management of the always on domain. According to the invention, by using a double power supply switching scheme, the low power consumption characteristic of a low power consumption power supply and the characteristics of higher response speed, precision and power supply capacity of a main power supply are utilized, and under the mutual combination, the chip of the Internet of things realizes two aims of low power consumption and quick response under a low power consumption mode needing quick response, thereby meeting the requirement of people on prolonging the endurance time of electronic products and promoting the wider application of the electronic products.

Description

Low-power-consumption system and method of Internet of things chip

Technical Field

The invention relates to the technical field of Internet of things chips, in particular to a low-power-consumption system and method of an Internet of things chip.

Background

In a low power consumption mode requiring quick response, the traditional method of a single power supply source does not take the power consumption of the power supply source as a research object, and the power consumption brought by the power supply source, so that the chip of the internet of things is considered in two factors of quick response and power consumption control, and the two factors are difficult to be considered.

In a low power consumption mode of the chip of the Internet of things, contradiction exists between the low power consumption level and the response speed, and in the low power consumption mode needing quick response, the scheme can obviously reduce the power consumption.

Disclosure of Invention

Aiming at the defects of the prior art, the invention discloses a low-power consumption system and method of an Internet of things chip, and solves the problem that the power consumption of the chip cannot be reduced enough in a scene needing quick response of the traditional Internet of things chip.

The invention is realized by the following technical scheme:

the invention discloses a low-power consumption system of an Internet of things chip, which comprises two external power supply pins VCC1 and VCC2, DC-DC, LDO-SOC, LDO-AON, MBGP, LPBGP, PSW1, PSW2 and PSW3; the system comprises a PD _ SOC power domain for realizing the main functions of the system on chip; a PD _ BLE power domain for realizing the low-power Bluetooth communication function; the PD-RAM power domain realizes the combination of multiple low-power consumption modes such as integral power on and power off, respective retentions and powerdown of each group, and the like; the PD _ LPM power domain realizes global configuration, global clock reset and power consumption management; and the PD _ AON power domain realizes the global configuration, low-frequency clock and global reset, awakening and power supply/power consumption management of the always on domain.

Further, the PD _ SOC power domain includes components of a system on chip including a CPU, memory, bus, DMA, and peripherals.

Further, the PD _ BLE power domain includes low power bluetooth components including BLE baseband, modem, RF and clock generator.

Further, the PD _ RAM power domain comprises a group of SRAM components with a retention mode and a powerdown mode.

Further, the PD _ LPM power domain includes components including a system control register, a power management unit pmulp, an RC oscillator, and a phase locked loop.

Furthermore, the PD _ AON power domain comprises an APB asynchronous bridge, a system control register, a low-power wake-up timer, a real-time clock RTC, a power management unit PMU _ AON, a low-frequency oscillator clock, a DC-DC, an LDO-SOC, an LDO-AON, a power-on reset POR, power detection and power-down protection PDR/PVD.

Furthermore, the LDO-SOC is a dual-power supply component consisting of two LDOs; the MLDO is used as a power supply source in normal operation, and reference voltage is provided by MBGP; the LPLDO is used for a power supply source in a low power consumption state, and a reference voltage is provided by LPBGP.

Furthermore, the MBGP is a main band gap reference and provides a reference voltage for the MLDO in the LDO-SOC;

the LPBGP is a low-power-consumption band gap reference and provides reference voltage for an LPLDO in the LDO-SOC;

the LDO-AON supplies power to PD _ AON (105) of always-on;

the PSW1, the PSW2 and the PSW3 are powerswitch components, and power supply switches of PD _ SOC, PD _ BLE and PD _ RAM power domains are realized under the digital logic control of the PD _ LPM (104).

In a second aspect, the invention discloses a low power consumption method of an internet of things chip, which uses the low power consumption system of the internet of things chip of the first aspect, and is characterized in that in the method,

when the chip of the Internet of things finishes the current work, before waiting for the next transaction to come, the chip of the Internet of things enters a Hibernate _1 or Hibernate _2 mode to save power consumption;

when the chip of the Internet of things receives the transaction processing request, the chip of the Internet of things sends out an awakening signal under the condition that corresponding awakening enabling is effective according to different transaction types, and the chip of the Internet of things is triggered to exit from a Hibernate _1 or Hibernate _2 mode.

Furthermore, when preparing to enter Hibernate _1, the CPU runs software, writes an instruction string into a PMU _ LP digital logic module of a PD _ LPM power domain after judging that the condition for entering the Hibernate _1 mode is reached, and starts the Hibernate _1 mode to enter a flow;

when entering Hibernate _2, PD _ SOC and PD _ BLE are turned off, and PD _ RAM (103) and PD _ LPM are kept powered on, wherein power supplies DC-DC, MBGP and MLDO are turned off, and a power supply domain PD _ LPM is powered by LPLDO.

The invention has the beneficial effects that:

according to the invention, by using a double power supply switching scheme, the low power consumption characteristic of a low power consumption power supply and the characteristics of higher response speed, precision and power supply capacity of a main power supply are utilized, and under the mutual combination, the chip of the Internet of things can simultaneously realize two aims of low power consumption and quick response in a low power consumption mode requiring quick response, so that the chip of the Internet of things can still use the low power consumption mode in the occasion requiring quick response, and the two requirements of low power consumption and response speed are taken into account, finally, the overall power consumption is reduced in the using process of the product, the requirement of people on prolonging the endurance time of the electronic product is met, and the wider application of the electronic product is promoted.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.

FIG. 1 is a schematic circuit diagram of a low power consumption system of an Internet of things chip;

FIG. 2 is a first illustration of an embodiment of the present invention;

fig. 3 is a second illustration of an embodiment of the present invention.

Detailed Description

In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all, embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

Example 1

The embodiment discloses a low-power consumption architecture of an internet of things chip, and referring to fig. 1, the internet of things chip designed by the architecture includes five power domains, namely a PD _ SOC power domain (101), a PD _ BLE power domain (102), a PD _ RAM power domain (103), a PD _ LPM power domain (104), and a PD _ AON power domain (105). The description of the five power domains is as follows:

PD _ SOC power domain (101): the components of the system on chip including a CPU, a memory, a bus, a DMA and peripheral equipment are parts for realizing the main functions of the system on chip;

PD _ BLE power domain (102): the low-power Bluetooth module comprises a BLE baseband, a modulation and demodulation device, an RF (radio frequency) and a clock generator, and is a part for realizing the low-power Bluetooth communication function;

PD _ RAM power domain (103): the module comprising a group of SRAM with retention and powerdown modes can realize the combination of various low power consumption modes such as integral power-on and power-off, and each group of the SRAM with retention and powerdown modes, and the like, and is a part for flexibly meeting the requirements of different scenes on the memory.

PD _ LPM power domain (104): the components including a system control register, a power management unit PMU _ LP (106), an RC oscillator (113) and a phase-locked loop (114) are parts for realizing global configuration, global clock reset and power management;

PD _ AON power domain (105): the components including an APB asynchronous bridge, a system control register, a low-power wake-up timer, a real-time clock RTC, a power management unit PMU _ AON (107), a low-frequency oscillator clock, a DC-DC (108), an LDO-SOC (109), an LDO-AON (110), a power-on reset POR, power detection and power-down protection PDR/PVD are parts for realizing global configuration, low-frequency clock and global reset, wake-up and power/power management of an always on domain.

Example 2

In the embodiment, a low power consumption architecture of an internet of things chip is disclosed, and according to the above power domain division, different power domains have respective dedicated power supplies, and referring to fig. 2 and fig. 3, components of a power supply network include two external power supply pins VCC1 and VCC2, DC-DC (201), LDO-SOC (202), LDO-AON (203), MBGP (204), LPBGP (205), PSW1 (208), PSW2 (209), and PSW3 (210).

The voltages of two external power supply pins VCC1 and VCC2 are VCC1:3V and VCC2:1.2V respectively;

wherein, the DC-DC (201) is used for reducing the voltage of VCC1 from 3V to 1.5V and then providing the voltage to the MLDO (206) in the LDO-SOC (202);

the LDO-SOC (202) is a dual power supply component consisting of two LDOs, the MLDO (206) is a power supply used in normal operation, and the MBGP (204) provides a reference voltage. The LPLDO (207) is a power supply source used in a low power consumption state, reference voltage is provided by LPBGP (205), and the two power supply sources jointly provide power for PD _ SOC (101), PD _ BLE (102), PD _ RAM (103) and PD _ LPM (104), and 4 power supply domains. According to the use scenes of the two power supply sources, the MLDO (206) and the reference voltage source MBGP (204) thereof are required to have high response speed, high precision and strong power supply capacity, but the MLDO and the reference voltage source MBGP have the problem of large power consumption; the response speed, accuracy and power supply capability to the LPLDO (207) and its reference voltage source LPBGP (205) are low, but they have the advantage of very low power consumption. Under a 55nm process, the self power consumption of the MLDO (206) is 80-100 times that of the LPLDO (206), and the self power consumption of the MBGP (204) is 120-150 times that of the LPBGP (205);

wherein, MBGP (204) is a main bandgap reference, and provides a reference voltage of 0.8V to MLDO (206) in LDO-SOC (202);

wherein the LPBGP (205) is a low power consumption bandgap reference, and provides a reference voltage of 0.8V to the LPLDO (206) in the LDO-SOC (202);

wherein, the LDO-AON (203) is a second power supply component and supplies power to the PD _ AON (105) of always-on;

the PSW1 (208), the PSW2 (209) and the PSW3 (210) are 3 powerswitch components, and under the digital logic control of the PD _ LPM (104), the function of switching power supply of 3 power domains such as the PD _ SOC (101), the PD _ BLE (102) and the PD _ RAM (103) is achieved.

Example 3

The embodiment discloses a low power consumption architecture of an internet of things chip, which has 7 power consumption modes in total, and the working conditions of each power supply under different power consumption modes are shown in the following table:

the low power consumption architecture of the chip of the internet of things disclosed in this embodiment has 7 power consumption modes, and the working conditions of each power domain in different power consumption modes are shown in the following table:

in 7 power consumptions, attention is focused on a Hibernate mode, and the Hibernate mode is a mode which realizes that a low-power-consumption architecture of an internet of things chip has response speed and power consumption in consideration and is specific based on the design of double power supply switching. The Hibernate mode is divided into Hibernate _1 and Hibernate _2 modes.

The principle of operation of Hibernate _1 mode is described as follows. All power domains are powered up, but at this time, 3 power supply sources DC-DC (201), MBGP (204) and MLDO (206) are turned off, and 4 power supply domains PD _ SOC (101), PD _ BLE (102), PD _ RAM (103) and PD _ LPM (104) are powered by LPLDO (206).

First, implementation of the Hibernate _1 mode low power consumption target will be described in detail. The Hibernate _1 mode requires that all main clock components including the RCOSC48M (113) and the PLL (114) are shut down to save the power consumption of the clock components caused by the operation, the clocks of the 4 power domains PD _ SOC (101), PD _ BLE (102), PD _ RAM (103) and PD _ LPM (104) are all stopped to stop all dynamic power consumption, and the PD _ RAM (103) can respectively place internal groups of sram states in a stop mode, a retention mode or a powerdown mode according to the requirements of actual application scenes. In addition, because all dynamic power consumption is stopped, the timing of the digital circuit and the SRAM does not need to be concerned, and lower voltage can be accepted, in the embodiment, the output voltage of the LPLDO (206) can be adjusted from 70% to 100% relative to the output voltage of the MLDO (206) in normal operation, and the default is 90%. Therefore, the architecture design of MLDO (206) and LPLDO (206) dual power supply switching firstly saves the self power consumption of MBGP (204) and MLDO (206) compared to the traditional single power supply scheme, secondly, only has the extremely low static power consumption of the digital logic of 3 power domains PD _ SOC (101), PD _ BLE (102) and PD _ RAM (103), and the extremely low non-read-write power consumption (stop, retention or powerdown) of the SRAM of PD _ LPM (104), thus achieving the goal of low power consumption.

Next, the implementation of Hibernate _1 mode fast response target will be described in detail. In the application of the chip of the internet of things, a plurality of scenes are represented as sudden transactions, and quick response is needed. The Hibernate _1 mode does not shut down any power domain, components including a CPU, a memory, a bus and peripherals are kept in the current state, when a low-power-consumption exit transaction is triggered, only a power supply is switched from an LPLDO (206) to an MBGP (204) and an MLDO (206), and a clock generation component is restarted. Thus, the goal of fast response is achieved.

Example 4

The embodiment discusses a Hibernate _1 mode working process of a low power consumption method of an internet of things chip as follows:

entry of Hibernate _1 mode. When the current work of the Internet of things chip is finished, the Internet of things chip can enter a Hibernate _1 mode to save power consumption before waiting for the next transaction. The CPU runs software, after judging that the power supply enters the Hibernate _1 mode, a command string is written into a PMU _ LP (106) digital logic module of a PD _ LPM (104) power domain, the Hibernate _1 mode entering process is started, as a clock generation component needs to be controlled and a power supply needs to be switched, and the set of process has strict timing requirements, the whole Hibernate _1 mode entering process is automatically completed by a state machine of the PMU _ LP (106) digital logic module, the state machine is driven by a RCOSC32K (119) low-frequency clock, all main clock sources are firstly closed, then the power supply is switched from MBGP (204) and MLDO (206) to LPLDO (206), and the driving of receiving the RCOSC32K (119) low-frequency clock is stopped.

Exit of Hibernate _1 mode. When the chip of the Internet of things receives the transaction processing request, the chip of the Internet of things is triggered to exit from the Hibernate _1 mode under the condition that corresponding awakening enabling is effective according to different transaction types. The wake-up signal will first turn on the state machine of the RCOSC32K (119) low frequency clock driving PMU _ LP (106) digital logic module, the state machine will enter Hibernate _1 mode exit flow, first switch the power supply from LPLDO (206) to MBGP (204) and MLDO (206), and restart the clock generation component, complete the Hibernate _1 mode exit flow.

The operation principle of Hibernate _2 mode is described as follows. Compared with Hibernate _1, the PD _ SOC (101) and the PD _ BLE (102) are turned off, 2 power domains are reserved, only the PD _ RAM (103) and the PD _ LPM (104) are powered on, but at the moment, 3 power supply sources DC-DC (201), MBGP (204) and MLDO (206) are turned off, and the power domain PD _ LPM (104) is powered by the LPLDO (206).

First, implementation of the Hibernate _2 mode low power consumption target will be described in detail. Hibernate _2 mode requires that all master clock components, including the RCOSC48M (113) and PLL (114), be shut down to save power itself from clock component operation, and that the clocks in the power domains PD _ RAM (103) and PD _ LPM (104) be all stopped to stop all dynamic power. And puts the PD _ RAM (103) in a recovery mode in its entirety. Since all dynamic power consumption is stopped, the timing of the digital circuits and SRAM is not concerned and can accept lower voltages, in this embodiment the output voltage of the LPLDO (206) can be adjusted from 70% to 100% relative to the output voltage of the MLDO (206) during normal operation, with a default of 90%. Therefore, the architecture design of MLDO (206) and LPLDO (206) dual power supply switching firstly saves the self power consumption of the MBGP (204) and MLDO (206) compared to the traditional single power supply scheme, and secondly, only has the very low static power consumption of the digital logic of the power domain PD _ LPM (104) and the very low retention power consumption of the PD _ RAM (103). Thus, the further aim of low power consumption on the basis of Hibernate _1 is realized.

Next, implementation of the Hibernate _2 mode fast response target will be described in detail. Compared with a Hibernate _1 mode, the Hibernate _2 mode shuts down components including a CPU, a memory, a bus and peripheral devices, but the retention mode of the PD _ RAM (103) keeps current data, when a low-power-consumption exit transaction is triggered, only a power supply source needs to be switched from the LPLDO (206) to the MBGP (204) and the MLDO (206), and a clock generation component is restarted, so that compared with a traditional power-down wake-up scheme, steps of a load program, recalibration of a sensor and the like are saved. In this way, the goal of fast response next to Hibernate _1 is achieved.

The working process of the Hibernate _2 mode is the same as that of the Hibernate _1 mode, and is not described herein again.

The embodiment provides a low-power architecture of an internet of things chip and two low-power modes Hibernate _1 and Hibernate _2 defined thereby. The architecture and the low power consumption mode defined based on the architecture utilize the switching of two different types of power supplies, and solve the problem that the power consumption of a chip cannot be reduced sufficiently in a scene needing quick response of a traditional Internet of things chip.

In conclusion, the invention utilizes the switching of two different types of power supplies, and solves the problem that the power consumption of the chip cannot be reduced enough in the scene needing quick response of the traditional Internet of things chip. The chip of the Internet of things can still use a low power consumption mode in the occasion of needing quick response, two requirements of low power consumption and response speed are considered, the overall power consumption is reduced in the use process of the product, the requirement of people on prolonging the endurance time of the electronic product is met, and the wider application of the electronic product is promoted.

The above examples are only intended to illustrate the technical solution of the present invention, but not to limit it; although the present invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; and such modifications or substitutions do not depart from the spirit and scope of the corresponding technical solutions of the embodiments of the present invention.

Claims (4)

1. A low-power consumption system of an Internet of things chip comprises two external power supply pins VCC1 and VCC2, DC-DC, LDO-SOC, LDO-AON, MBGP, LPBGP, PSW1, PSW2 and PSW3; the system is characterized by comprising a PD _ SOC power domain for realizing the main functions of the system on chip, wherein the PD _ SOC power domain comprises components of the system on chip, including a CPU, a memory, a bus, a DMA and peripheral equipment;

the PD _ BLE power domain realizes the low-power Bluetooth communication function, and comprises a low-power Bluetooth assembly including a BLE baseband, a modem, an RF and a clock generator;

the PD-RAM power domain realizes the combination of integral power-up and power-down, various groups of low-power consumption modes, and comprises a group of components including SRAM with the power-down and power-down modes;

the PD _ LPM power domain realizes global configuration, global clock reset and power consumption management, and comprises components including a system control register, a power consumption management unit PMU _ LP, an RC oscillator and a phase-locked loop;

the PD _ AON power domain realizes the global configuration, the low-frequency clock and the global reset, the wake-up and the power/power management of the always on domain, and comprises components including an APB asynchronous bridge, a system control register, a low-power wake-up timer, a real-time clock RTC, a power management unit PMU _ AON, a low-frequency oscillator clock, a DC-DC, an LDO-SOC, an LDO-AON, a power-on reset POR, a power detection and a power-down protection PDR/PVD;

the LDO-SOC is a dual power supply component consisting of two LDOs; the MLDO is used as a power supply source during normal operation, and the MBGP provides a reference voltage; the LPLDO is used for a power supply source in a low power consumption state, and a reference voltage is provided by LPBGP.

2. The low power consumption system of the chip of the internet of things of claim 1, wherein the MBGP is a main bandgap reference providing a reference voltage to the MLDO in the LDO-SOC;

the LPBGP is a low-power-consumption band gap reference and provides reference voltage for an LPLDO in the LDO-SOC;

the LDO-AON supplies power to PD _ AON (105) of always-on;

the PSW1, the PSW2 and the PSW3 are powerswitch components, and power supply switches of PD _ SOC, PD _ BLE and PD _ RAM power domains are realized under the digital logic control of the PD _ LPM (104).

3. A low power consumption method of an Internet of things chip, the method uses the low power consumption system of the Internet of things chip as claimed in any one of claims 1-2, wherein in the method,

when the chip of the Internet of things finishes the current work, before waiting for the next transaction to come, the chip of the Internet of things enters a Hibernate _1 or Hibernate _2 mode to save power consumption;

when the chip of the Internet of things receives the transaction processing request, the chip of the Internet of things sends out an awakening signal under the condition that corresponding awakening enabling is effective according to different transaction types, and the chip of the Internet of things is triggered to exit from a Hibernate _1 or Hibernate _2 mode.

4. The low power consumption method of the chip of the internet of things of claim 3, wherein when the chip of the internet of things is ready to enter Hibernate _1, the CPU runs software, and after judging that the condition for entering the Hibernate _1 mode is reached, writes an instruction string into the PMU _ LP digital logic module of the PD _ LPM power domain, and starts the entering process of the Hibernate _1 mode;

when entering Hibernate _2, PD _ SOC and PD _ BLE are turned off, and PD _ RAM (103) and PD _ LPM are kept powered on, wherein power supplies DC-DC, MBGP and MLDO are turned off, and a power supply domain PD _ LPM is powered by LPLDO.

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