CN114326931B - Industrial-grade clock controller, industrial-grade control system, method and electronic device - Google Patents
Industrial-grade clock controller, industrial-grade control system, method and electronic device Download PDFInfo
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- CN114326931B CN114326931B CN202111648484.7A CN202111648484A CN114326931B CN 114326931 B CN114326931 B CN 114326931B CN 202111648484 A CN202111648484 A CN 202111648484A CN 114326931 B CN114326931 B CN 114326931B
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Abstract
The invention belongs to the technical field of clock control, and provides an industrial clock controller, an industrial control system, an industrial control method and an electronic device, wherein the industrial clock controller comprises: a clock circuit for generating real time; a power supply starting control port connected with the clock circuit, and outputting a power-on control signal to the main power supply after a preset time; the first register is used for storing source information of a power-on signal output by the industrial-level clock controller to the main power supply, wherein the source information of the power-on signal comprises main power supply starting signal information input from an external pin of the industrial-level clock controller and main power supply starting signal information associated with the clock circuit; and the isolation circuit is used for isolating the main power side from rewriting the information in the first register in the starting process of the main power. The isolation circuit is added to prevent interference to internal parameters of the RTC module in the starting process of a control system for signals in the register.
Description
Technical Field
The present invention relates to the field of clock control technologies, and in particular, to an industrial clock controller, an industrial control system, an industrial control method, and an electronic device.
Background
In many electronics applications, particularly battery powered applications, low power consumption is a very important technical problem. The Real Time Clock (RTC) module is a commonly used functional module in low power consumption applications of a control System (for example, soC, english full scale System on Chip, on Chip operating System), and in the case of a general low power consumption application, a user application can make the control System set in a Sleep Mode (Sleep Mode) with low power consumption for a long Time as much as possible, and the RTC module generates a wake-up request signal when a set Time is reached through accurate timing of the Real Time Clock module in the control System, so that the control System is waken up from the Sleep Mode, and then the control System performs the next stage of operation.
Taking the SoC as an example of a control system, in the SoC, the RTC uses a function module with a very high frequency. The system can provide accurate real-time for the system, and most RTC modules currently adopt crystal oscillators with higher accuracy as clock sources. Besides being used as a time reference, the RTC module can further work when the main power supply is powered down, and after a preset time, the main power supply is controlled to be powered up, so that the main system can restart to work.
If it is desired that the RTC continues to operate during power down of the main power supply, an independent power supply needs to be provided for the RTC module, i.e. the RTC module and the main system are respectively in different power domains. However, in the prior art, the working mode of the RTC module is controlled by a configuration register (configure register), and the configuration of these registers needs to be completed through read-write operation of the main system, and typically, the main system and the RTC module are interconnected through an APB bus.
The following technical problems exist in the prior art: when the main power supply is powered up again, a system reset will first take place, which will also cause a reset of the RTC module, because when the system reset signal is asserted, it will cause a reset signal in the APB bus to be asserted. Since the reset signal is a reset signal of the RTC configuration register, this will cause the data of the configuration register in the RTC module to be reset to an initial state, so that the working mode of the RTC module is changed, which affects the working behavior of the SoC system, which is obviously not the normal behavior of the system.
Disclosure of Invention
In order to solve the technical problem that an RTC module is abnormally reset in the prior art, the invention provides an industrial-level clock controller, an industrial-level control system, an industrial-level control method and an electronic device, and the interference on internal parameters of the RTC module in the starting process of a control system of signals in a register is prevented by adding an isolation circuit.
A first aspect of the present invention provides an industrial-scale clock controller, comprising:
a clock circuit for generating real time;
a power supply starting control port connected with the clock circuit, and outputting a power-on control signal to a main power supply after a preset time;
the first register is used for storing source information of a power-on signal output by the industrial clock controller to the main power supply, and the source information of the power-on signal comprises main power supply starting signal information input from an external pin of the industrial clock controller and main power supply starting signal information associated with the clock circuit;
and the isolation circuit is used for isolating the main power side from rewriting the information in the first register in the starting process of the main power.
In a preferred embodiment of the present invention, the industrial-level clock controller further includes: a second register configured to be the same address as the first register; and when the write operation is performed on the address, data can be written into the first register and the second register at the same time, and when the read operation is performed on the address, only the configuration information of the first register is read out.
In a further preferred embodiment of the present invention, the second register is communicatively connected to an external power enable pin from the industrial-level clock controller and is used to drive the state of the power enable control port; the state of the second register driving the power-on control port includes: driving the power supply starting control port according to first configuration information in the industrial clock controller to control the external power supply to be powered down; outputting a power-on control signal to a main power supply according to the clock circuit after the preset time, and controlling the external power supply to be powered on; and outputting a power-on control signal to a main power supply according to a power-on signal input by an external power-on pin of the industrial clock controller, and controlling the external power supply to be powered on.
In a further preferred embodiment of the present invention, a power wake-up register is further provided between the second register and the clock circuit, and the power wake-up register and the second register are connected with an external power start pin of the industrial clock controller through a first or gate circuit in a communication manner; when the clock circuit starts to output a high-level signal to the power supply wake-up register from T1 after a preset time, the power supply wake-up register inputs a high level to the OR gate circuit; the power wake-up register also inputs a control signal to the second register through a synchronization circuit such that the second register is configured to input a high level to the first or gate beginning at T2.
In a still further preferred embodiment of the present invention, the isolation circuit includes a first isolation circuit for controlling writing information, the first isolation circuit includes a three and gate circuit and a two and gate circuit, and input ends of the three and gate circuits are respectively connected with an output end of the power wake-up register, an isolation signal input from the outside, and an external power start pin of the industrial clock controller; the input ends of the two AND gates are respectively connected with the output ends of the three AND gates and the externally input write signals, and the output ends of the two AND gates are connected with the first register.
In a preferred embodiment of the present invention, the isolation circuit includes a second isolation circuit for controlling reset information, the second isolation circuit including: the output end of the inverter is respectively connected with the input end of the second OR gate and the input end of the third OR gate, and the second OR gate and the third OR gate respectively receive a first reset signal and a second reset signal which are input from the outside; and the output ends of the second OR gate circuit and the third OR gate circuit are respectively connected with the input end of the first register and the input end of the second register.
The second aspect of the present invention also provides an industrial-level control system, comprising:
the industrial-level clock controller of any one of the first aspects,
peripheral bus, power manager, and connected to the industrial level clock controller
And the main power domain is respectively connected with the peripheral bus and the power manager.
In a preferred embodiment of the present invention, the industrial-level control system further comprises a battery electrically connected to the industrial-level clock controller.
The third aspect of the present invention also provides an electronic device, which is characterized by comprising:
the industrial-level control system as provided in the second aspect above,
a memory, a peripheral circuit;
and the industrial level control system executes read-write and reset operations to registers in an industrial level clock controller in the industrial level clock controller according to the information in the memory and/or the state of the peripheral circuit.
The fourth aspect of the present invention also provides a control method for an industrial-scale clock controller, comprising:
when the industrial clock controller is electrified for the first time, a main power supply starting signal is input to an external pin of the industrial clock controller so as to drive an output pin connected with the output of the main power supply to output a high level;
the high level output by the output pin connected with the output of the main power supply drives the power supply manager to supply power to the main power supply;
when the industrial clock controller is restarted, isolating externally input information through an isolating circuit, wherein the input information is used for rewriting configuration information in a first register in the industrial clock controller; the configuration information in the first register comprises source information of the power-on signal, wherein the source information comprises main power supply starting signal information input from an external pin of the industrial-level clock controller and main power supply starting signal information associated with the clock circuit.
By adopting the technical scheme provided by the invention, the information in the first register is rewritten by the main power side in the starting process of the main power by adding the isolation circuit; therefore, the working mode of the RTC module cannot cause the reset and write operation in the starting process of the control system in the resetting process of the control system, and the error rewriting of the configuration information corresponding to the working mode of the RTC module in the industrial clock controller is caused.
Additional features and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention may be realized and attained by the structure and/or process particularly pointed out in the written description and claims hereof as well as the appended drawings.
Drawings
Fig. 1 is a schematic diagram of connection between an industrial control system and a power supply according to an embodiment of the present invention.
Fig. 2 is a schematic structural diagram of an industrial clock controller according to an embodiment of the present invention.
Fig. 3 is a schematic diagram of another industrial clock controller according to an embodiment of the present invention.
Fig. 4 is a timing diagram of an industrial clock controller according to an embodiment of the present invention.
Fig. 5 is a schematic diagram of a control method for an industrial clock controller according to an embodiment of the invention.
Fig. 6 is a schematic structural diagram of an electronic device according to an embodiment of the invention.
Detailed Description
The following will describe embodiments of the present invention in detail with reference to the drawings and examples, thereby solving the technical problems by applying technical means to the present invention, and realizing the technical effects can be fully understood and implemented accordingly. It should be noted that these specific descriptions are only for easy and clear understanding of the present invention by those skilled in the art, and are not meant to be limiting; and as long as no conflict is formed, each embodiment of the present invention and each feature of each embodiment may be combined with each other, and the formed technical solutions are all within the protection scope of the present invention.
Additionally, the steps illustrated in the flowcharts of the figures may be performed in a control system such as a set of controller-executable instructions, and although a logical order is illustrated in the flowcharts, in some cases the steps illustrated or described may be performed in an order other than that herein.
The following describes the technical scheme of the invention in detail through the attached drawings and specific embodiments:
examples
Fig. 1 is a schematic diagram showing connection between an industrial control System (for example, a System on Chip (SoC) 100) and a power supply, where the SoC100 can be applied to industrial products, and particularly, an industrial ultra-low power consumption mode is implemented. However, the industrial control system provided in this embodiment is not limited to the SoC hardware circuit, and for other hardware circuits, for example, the FPGA control system, if the main controller needs to implement the power-on control of the power supply through the RTC module, the technical scheme provided in this embodiment may also be adopted.
As shown in fig. 1, in the SoC100, the RTC power domain 110 controls power-down/power-up of the main power domain 120, and a specific connection manner is shown in fig. 1, and when the main system has no task to be processed, it passes through the APB bus 130 (the english of APB is all called Advanced Peripheral Bus), and the RTC power domain 110 configures an RTC register internally, including a power wake-up time, an RTC timing enable, a main power-down enable, and so on. When the RTC times out, the pwen_ctl pin 142 of the auto-control SoC outputs a high level, causing the off-chip power manager 300 (e.g., PMIC, english full scale Power Management IC, power management integrated circuit) to re-power the main power domain 120 of the SoC100 via the power pin VDD 143. In this embodiment, in addition to automatically controlling the output of the pw_ctl pin 142 of the SoC to be high, the output of the pw_ctl pin 142 of the SoC to be low may be predefined to implement enabling control of the power manager.
As shown in FIG. 1, the VDD_AO pin 141 is connected to the battery 200 such that the VDD_AO pin 141 is always powered by the always-on power supply, i.e., the RTC power domain 110 (or RTC module) is always in an powered state. It should be noted that, in the present embodiment, the battery 200 and the power manager 300 may be disposed outside the SoC100 as shown in fig. 1, or may be partially or completely disposed inside the SoC 100.
As shown in fig. 1, the pins in the SoC100 provided in this embodiment function as follows: the power supply pin VDD143 is usually a power supply voltage or an internal voltage of the electrode device, and the pin Vss144 and the pin Vss145 are respectively a ground terminal or a power supply negative electrode; the prstn_rtc pin 146 is used for receiving an external power-on signal, for example, a switch in an electronic device in which the SoC100 is installed is turned on or off, thereby triggering the prstn_rtc pin 146 to be at a high level or a low level.
In this embodiment, the main system corresponding to the SoC chip restarts the operation by:
-a first power-up of the electric motor,
the RTC controls the main power domain to power up,
the off-chip pin triggers a power-up, e.g., the prstn _ rtc pin 146,
WDT (English full-scale Watch Dog Timer), watchdog Timer overflow triggers full chip reset,
the controller inside the SoC triggers a full chip reset by software.
The 5 above are common SoC start modes, the first three of which are cold starts and the second two of which are hot starts. Regardless of the mode of start-up, the whole SoC is reset and begins to operate from a particular reset vector. For some SoC systems, there is no built-in power-on reset unit (POR), so when restarting the system in a cold start mode, a power-on reset signal is generated off-chip and sent into the chip via a full-chip reset pin.
In practical applications, it is necessary to know from which state the system is restarted; different restart states determine different software behaviors. Special register bits are typically set to identify whether a restart behavior has occurred. More commonly known as WDT, the designer will typically set a register bit for it, which if 1 indicates that a WDT reset has occurred; if 0, no WDT reset occurs. It should be noted that this register bit will only be set to 1 after a WDT reset has occurred. The 0 may be cleared by software. After the full chip is reset, the initial state is also 0.
Similarly, the RTC, which is a restart mode, may also provide a similar register for determining whether a main system restart of RTC control has occurred. After the restart, the contents of this register are not rewritten, nor are the contents of other RTC registers, including others. Only in this way, it can be judged whether or not the restart of RTC control has occurred.
How to reliably prevent the main system from being rewritten by the RTC register after it is awakened to power up by the RTC, one solution is to isolate the APB bus to an inactive state during power down of the main power supply. When the RTC times, the main power domain is controlled to start to be powered up again, and isolation of the APB bus is finished.
In addition, the inventor also found that in implementing the present invention, the power-up process of the main power domain 120 generates a larger in-rush current (with limiting surge current), which results in not only requiring a setup process before the VDD signal reaches a stable voltage that can operate, but also usually accompanied by a larger noise, depending on factors such as the driving capability of the PMIC and electromagnetic interference on the application board.
If the signals from the power down domain are isolated for electrical characteristics only, it is not necessary to consider that noise may erroneously overwrite the contents of the RTC registers during the period from when the main power supply is powered up to when the voltage stabilizes.
In order to solve the technical problem that an RTC module is abnormally reset in the prior art, the embodiment provides an industrial-level control system, and an industrial-level clock controller in the industrial-level control system prevents interference to internal parameters of the RTC module in a starting process of a control system for signals in a register by adding an isolation circuit.
As shown in fig. 2, the present embodiment provides an industrial-level clock controller 1000, including:
a clock circuit 113 for generating real time;
an output module 112 (e.g., a power-on control port) connected to the clock circuit 113, which outputs a power-on control signal to the main power supply after a preset time;
the first register 111 is configured to store source information of a power-up signal output by the industrial-level clock controller to the main power supply, where the source information of the power-up signal includes: (1) main power supply start signal information input from an external pin of the industrial-level clock controller, (2) main power supply start signal information associated with the clock circuit, for example, the clock circuit is controlled through WDT (what is known as a Watch Dog Timer, english), overflow triggers configuration information corresponding to full-chip reset, and a controller in the SoC triggers configuration information corresponding to full-chip reset through software.
An isolation circuit 115 for isolating the main power side from rewriting the information in the first register during the main power start-up process; the isolation circuit 115 combines the configuration information stored in the first register 111, and in the case of no need of rewriting, combines the logic gate circuit inside the isolation circuit 115 to disable the information input by the input module 116, so that the isolation circuit 115 can isolate the erroneous rewriting information input by the input module 116, including but not limited to a reset signal, a write signal, and the like.
By adopting the above technical solution provided in this embodiment, by adding the isolation circuit 115, in the process of starting the main power supply, the main power supply side is isolated from rewriting the information in the first register; therefore, the working mode of the RTC module cannot cause the reset and write operation in the starting process of the control system in the resetting process of the control system, and the error rewriting of the configuration information corresponding to the working mode of the RTC module in the industrial clock controller is caused.
As shown in fig. 2, the industrial-level clock controller 1000 further includes: a second register 114, the second register 114 and the first register 111 being configured with the same address; the second register 114 is also referred to as a backup register or shadow register of the first register 111. And when a write operation is performed on the address, data is written into the first register 111 and the second register 114 at the same time, and when a read operation is performed on the address, only the configuration information of the first register 111 is read out.
The circuit of the isolation circuit 115 is specifically described below with reference to fig. 3, and the electronic components and signal names in fig. 3 are as follows:
a 1000-prstn_rtc pin, a level signal (also called wake-up source 2) received from the outside; respectively, to and circuit 1010, three and circuits 1140, a first register 1120;
1010-AND gate circuit, one input end is connected with prstn_rtc pin, one input end is connected with presetn_mk signal, and output end is connected with input end of second register;
1020-a second register, identical to the information written in the first register 1120; one input is coupled to the output of and gate 1010, one input is coupled to synchronizer 1150, receives the wk _ ack signal input by synchronizer 1150,
1030-or gate circuit, one input connected to the output of the second register, one input connected to the output of the power wake-up register 1050, and one output connected to the pwen_ctrl output pin, and also connected to the input of a not gate 1070;
1040-the first synchronizer is configured to,
1050-a power wake-up register (english name pwen_ctrl_wk) receiving the rtc_int_pulse wake-up signal (hereinafter referred to as wake-up source 1 for convenience of description) output by the RTC module;
1060-pwen _ ctrl output pin,
1070-NOT circuit, input end is connected with OR circuit 1030, output end is iso_en signal;
1080-OR gate, one end of which receives the reset signal presetn, and one end of which is connected with the NAND gate 1100, and outputs a presetn_mk signal, which is input to the AND gate 1010 and the RTC module as indicated by the arrow on the lower left side of FIG. 3;
1090-or gate, one end of which is connected with the nand gate 1100, and one end of which receives the reset signal rtc_rstn; outputting the rtc_rstn_mk signal to the first register 1120;
1100-NOT circuit, which converts the output signal of the first time register; for example, if the first register outputs a low level, the not circuit outputs a high level; thus, no matter what the reset signal presetn and the reset signal rtc_rstn are, the or gate 1080 and the or gate 1090 output high level, so that the isolation of the reset signal is realized;
1110-an RTC module, which internally includes a first register 1120,
1120-a first register, a second register,
1130-OR gate, one end of which receives the input of the three AND gates 1140, and one end of which receives the pwrite signal, outputting the pwrite signal to the RTC module 1110;
1140-three AND gate circuit, one end receives the signal output by the power wake-up register 1050 and the signal input by the prstn_rtc pin 1000, and one end receives the signal after the iso_en is inverted; output to OR gate 1130; thus, when the RTC outputs a high level signal of the wake-up source 1, the RTC outputs a low level to the three and gate 1140 after the opposite, and then outputs a low level to the or gate 1130, so that the level of the or gate 1130 input to the RTC module 1110 is always kept low, thereby isolating the pwrite signal;
1150-synchronizer 1150 receives control of clock signal 1160, adjusts the input wk_ack signal output to second register 1020 by combining the pwen_ctrl_wk_pulse signal output from power wake-up register 1050 with the input of the clock signal;
1160—clock signal input by main power domain;
referring to FIG. 3 above for a specific illustration of the circuitry of the isolation circuit 115, a second register 1010 is communicatively coupled to an external power enable pin from the industrial level clock controller and is used to drive the state of the power enable control port; the state of the second register driving power supply start control port includes: driving a power supply start control port according to first configuration information in the industrial clock controller to control the external power supply to be powered down; outputting a power-on control signal to a main power supply according to the preset time of the clock circuit, and controlling the external power supply to be powered on; and outputting a power-on control signal to a main power supply according to a power-on signal input by an external power-on pin of the industrial clock controller, and controlling the external power supply to be powered on.
The second register 1020, also called pwen_ctl_drv register, is used to drive the state of the pwen_ctl port, and includes:
-software write register 0, driving pwen_ctl low, powering down off the off-chip PMIC.
-RTC times out, driving pwen_ctl_wk_pulse high, powering up the off-chip PMIC.
When the prstn_rtc pin has a low pulse, the pwen_ctl_drv register is set to 1, driving pwen_ctl high, powering up the off-chip PMIC.
A power wake-up register 1050 is further arranged between the second register 1020 and the clock circuit, and the power wake-up register 1050 and the second register 1020 are in communication connection with an external power start pin 1000 of the industrial clock controller through a first OR gate 1010; when the clock circuit inside the RTC module outputs a high level signal from T1 to the power wake-up register 1050 after a preset time (or according to configuration information of software), the power wake-up register 1050 inputs a high level to the or circuit 1030; the power wake-up register 1050 also inputs a control signal (wk_ack signal) to the second register 1010 through the synchronization circuit 1150, such that the second register 1010 is configured to input a high level to the first or gate 1030 beginning at T2.
The first register 1120, also referred to as the pwen_ctl_status register, is defined as follows:
| bit31 | bit1 | bit0 |
| prstn_rtc | pwen_ctl_mk |
the function of the pwen_ctl_status register is as follows:
after the inversion of the-pwen_ctl_mk bit, i.e. rstn_mk
Software write pwen_ctl_mk bit0, masking reset behavior of the RTC by present/rtc_rstn
Software write pwen_ctl_mk bit1, does not mask reset behavior of the RTC by present/rtc_rstn
After a restart, the register is read, determining if the restart is triggered by RTC or prstn_rtc
As shown in fig. 3, the isolation circuit includes a first isolation circuit for controlling writing information, the first isolation circuit includes a three and gate 1140 and a two and gate 1130, and input ends of the three and gate 1140 are respectively connected with an output end of a power wake-up register, an isolation signal input from the outside, and an external power start pin of the industrial clock controller; the input end of the second and circuit 1130 is connected to the output end of the third and circuit and the externally input write signal, respectively, and the output end of the second and circuit is connected to the RTC module 1110 where the first register 1120 is located, so that abnormal overwriting of the configuration information in the first register 1120 can be prevented.
And the isolation circuit further includes a second isolation circuit that controls the reset information, the second isolation circuit including: the output end of the inverter 1100 is respectively connected with the input end of the second or gate 1080 and the input end of the third or gate 1090, and the second or gate 1080 and the third or gate 1090 respectively receive a first reset signal (for example, a presetn signal) and a second reset signal (for example, a rtc_rstn signal) which are input from the outside; the outputs of the second or gate 1080 and the third or gate 1090 are connected to the input of the first register 1120 and the input of the second register 1020, respectively. And the second or gate 1080 output is also input to the RTC module.
From the above description, if the main power supply is desired to be powered down, only 0 needs to be written to pwen_ctl_drv. Since the pwen_ctl_mk register bit will also be 0 at this time, the reset signal (rtc_rstn/unsetn) from the main power domain is isolated to an inactive state (high) during main power down. After the main system is restarted and the rtc_rstn/presetn reset is finished, software is required to write 1 to pwen_ctl_mk to finish the isolation of rtc_rstn/presetn. In this way, when the host system is restarted, the reset signal from it will not reset the RTC.
In general, during the power-up process of the main power supply, because there is a large in-rush current, an APB interface signal sent from the main power supply domain to the RTC power supply domain is caused to have a large noise, and when these interface signals with noise just meet the write operation condition of the RTC register, the value of the register is rewritten, so that besides the presetn/rtc_rstn is isolated, it is necessary to isolate the pwrite so that the pwrite is in a write inhibit (pwrite is low) state before the main power supply is stable.
Isolation of pwrite by handshaking is described below in conjunction with fig. 4. For other signals of the APB interface, during the power-down period of the main power domain, the signals are isolated to an invalid state only through the iso_en signal, and special treatment is not needed.
The isolation procedure for presetn/pwrite is described as follows:
1) During main power down, pwrite is isolated low (pwrite_mk is an isolated signal) and presetn is isolated high (presetn_mk is an isolated signal).
2) RTC timing arrives, generating power-on wake-up signal (rtc_int_pulse)
3) rtc_int_pulse causes pwen_ctl_wk_pulse to set 1 (handshake process starts), thereby causing pwen_ctl to set 1, pmic to start powering the main power supply, and main system to start entering power-up process.
4) After the main power supply is stable, rtc_rstn is reset (rtc_rstn jumps from 0 to 1)
5) The clock pclk (the clock signal of the APB bus) from the host system samples pwen_ctl_wk_pulse, generating the host system power-on response signal wk_ack.
Description: wk_ack is set to 1, indicating that the host system is powered up stable.
6) The pwk_ack 1 is recognized by the pwn_ctl_drv register, and pwn_ctl_drv is set to 1
7) After pwen_ctl_drv is set to 1, pwen_ctl_wk_pulse is automatically cleared to 0 (handshake process is ended), i.e. the pwen_ctl pin is no longer controlled by pwen_ctl_wk_pulse and starts to be controlled by pwen_ctl_drv.
8) Before the main power supply starts to supply power and before the power supply is stable, the power supply of the PMIC is controlled by a pwen_ctl_wk_pulse signal, so that the pwrite signal is isolated by the signal to eliminate noise on pwrite.
(Note that although other APB signals are noisy during power-up, the RTC register can be prevented from being rewritten by mistake by only isolating the pwrite)
9) During operation of the host system, a reset operation is allowed to be performed on the RTC, so that the reset isolation of the RTC needs to be released first. The isolation of the reset is removed by software writing a 1 to the pwen_ctl_mk register.
10 The host system reads the state of the RTC register, determines the restart mode, responds to the interrupt, and executes the corresponding software branch program.
The clock signal in fig. 4 works as follows:
rtc_clk is the working clock of the RTC module, typically 32768Hz, which works all the way after the RTC is powered up, unless the RTC power domain is powered down.
Pclk is the clock signal of the APB bus,
the signal is clamped to a low state during a power down of the main power domain and input to the RTC module.
When the main power domain is awakened again by the RTC, a certain stable time is passed, and the stable time is input to the RTC module.
By the above described presetn isolation, pwrite isolation, erroneous writing of RTC register contents during power-up of the main power supply can be reliably prevented.
The technical solution provided in this embodiment is further explained below with reference to fig. 3:
it should be noted that, after the first power-up, all registers of the RTC may not be reset, i.e., the values of the registers are random. Because pwen_ctl_mk affects the state of rstn_mk; the state of pwen_ctl_mk is also affected by rstn_mk, and this closed loop (loop) logic structure can result in uncertainty in the value of pwen_ctl_mk after initial power-up. If 1, rstn_mk does not mask the reset from the host system; if it is 0, rstn_mk will mask the reset from the host system. This is also why step (9) above is to be performed.
As to how to determine whether the RTC control main power supply is powered up, in addition to determining the state of the pwen_ctl_mk register, a 16-bit register (power_up_code register) is also configured in the design, and if the value obtained by reading the register is 0 or other random value after the power up, the system is indicated to be powered up for the first time; if a preset value, e.g., 5A5A, is read, this indicates that the RTC is controlling the main power up. The preset value is set before the main power supply is powered down. After the first power-up, the state of pwen_ctl_mk is also indefinite, so that the restart mode is determined to be inaccurate by pwen_ctl_mk at this time. However, the following restart determination may be performed by determining the restart mode because it already has a stable 0 or 1, but it is precisely determined by combining the power_up_code register.
Finally, the role of the prstn_rtc pin is explained. Sometimes we do not want to wait until the RTC restarts the host system, but want to restart the host system immediately through some pin, the prstn_rtc pin is this effect. Whether an external pin restart of the host system occurs is determined by reading the state of the prstn_rtc bit of the pwen_ctl_status register. The restart mode does not overwrite the contents of the RTC register because the pulse width of the prstn_rtc low pulse from off-chip is much longer than the power settling time, i.e., the pwrite signal is always in isolation before the main power can operate steadily.
As shown in fig. 6, the present embodiment further provides an electronic device 400, including:
a processor 410, the processor 410 may employ an industrial-level control system, such as a SoC, as provided in fig. 1 above;
a memory 420, peripheral circuitry 430;
and the industrial level control system executes read-write and reset operations to registers in an industrial level clock controller in the industrial level clock controller according to the information in the memory and/or the state of the peripheral circuit.
For example, the electronic apparatus 400 may set a predetermined time or enter a sleep state when the peripheral circuit does not receive an operation instruction; thus, the main power domain inside the SoC needs to be controlled to turn off the power supply; and different sleep grades can be set according to different requirements, and the modules for closing the power supply are different. And a power-up operation needs to be performed on the main power domain inside the SoC when a condition in the peripheral circuit or the memory 420 satisfies a predetermined requirement.
As shown in fig. 5, the present embodiment further provides a control method for an industrial-scale clock controller, including:
s110, when the industrial level clock controller is electrified for the first time, a main power supply starting signal is input to an external pin of the industrial level clock controller so as to drive an output pin connected with the output of the main power supply to output a high level;
s120, driving a power manager to supply power to a main power supply by high level output by an output pin connected with the output of the main power supply;
s130, when the industrial clock controller is restarted, isolating externally input information through an isolating circuit, wherein the input information is used for rewriting configuration information in a first register in the industrial clock controller; the configuration information in the first register comprises source information of a power-on signal, wherein the source information comprises main power supply starting signal information input from an external pin of the industrial-level clock controller and main power supply starting signal information associated with a clock circuit.
The detailed control details are understood in conjunction with the descriptions of fig. 1, 2 and 3, and are not described herein.
In addition, regarding software stored internally after the SoC is powered on or software loaded from an external memory, the following operations are performed:
1) The chip is first powered up, requiring the prstn_rtc pin to input a low level to drive the pwen_ctl pin to output a high level.
Note that: the initial power-up is a special case of off-chip pin (prstn_rtc) triggering power-up. The following table (one) lists the differences between the two.
2) The signal output by the pwen_ctl pin controls the operation of the PMIC chip to supply power to the main power supply.
3) After the main power supply is electrified, the main system starts to work, and the restarting mode can be judged firstly:
is it first powered up?
Is it a RTC controlling the main power up?
Is it a piece of outer pin (prstn_rtc) triggering power-up?
It is first determined whether the power up code register is a preset value,
if not, power up for the first time, jump to subroutine 1
-if so, wake up power up
The prstn _ rtc pin is asserted (by reading bit1 of pwen _ ctl _ status),
-0, prstn_rtc wakes up, jumps to subroutine 2
-bit 0, which is not 0, of the pwen_ctl_status is again determined
-0, then RTC wakes up to power up, jumps to subroutine 3
Otherwise, warm start, jump to subroutine 4
4) The masking of the main system reset signal ends with pwen_ctl_mk position 1.
5) The main system control rtc_rstn resets RTC.
6) Processing other transactions
7) When the main power supply is intended to be powered down, the RTC is first configured, including power-up wakeup time/interrupt, etc.
In addition, a special value, e.g., 5A, needs to be set to the power_up_code register.
Finally, the software writes 0 to pwen_ctl_drv.
8) The main power supply is powered down, and the RTC continues to work.
If the RTC is not expected to wake up the main power supply, the main power supply can be immediately awakened through the prstn_rtc pin.
9) After the main power supply is powered on, the method starts from step 3.
Note that: the above steps omit some branching procedures, such as sub-procedure 1/2/3/4, the content of which depends on the application scenario.
Regarding judging the cold start mode, the configuration information may be obtained from the following table:
by adopting the technical scheme provided by the embodiment, the information in the first register is rewritten by the isolated main power side in the starting process of the main power by adding the isolation circuit; therefore, the working mode of the RTC module cannot cause the reset and write operation in the starting process of the control system in the resetting process of the control system, and the error rewriting of the configuration information corresponding to the working mode of the RTC module in the industrial clock controller is caused.
Those of ordinary skill in the art will appreciate that: the above-described methods according to embodiments of the present invention may be implemented in hardware, firmware, or as software or computer code storable in a recording medium such as a CD ROM, RAM, floppy disk, hard disk, or magneto-optical disk, or as computer code originally stored in a remote recording medium or a non-transitory machine-readable medium and to be stored in a local recording medium downloaded through a network, so that the methods described herein may be processed by such software on a recording medium using a general purpose computer, a special purpose processor, or programmable or special purpose hardware such as an ASIC, FPGA, or SoC. It is understood that a computer, processor, microprocessor controller, or programmable hardware includes a memory component (e.g., RAM, ROM, flash memory, etc.) that can store or receive software or computer code that, when accessed and executed by the computer, processor, or hardware, implements the processing methods described herein. Further, when the general-purpose computer accesses code for implementing the processes shown herein, execution of the code converts the general-purpose computer into a special-purpose computer for executing the processes shown herein.
Those of ordinary skill in the art will appreciate that the elements and method steps of the examples described in connection with the embodiments disclosed herein can be implemented as electronic hardware, or as a combination of computer software and electronic hardware. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the solution. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the embodiments of the present invention.
Finally, it should be noted that the above description is only a preferred embodiment of the present invention, and is not intended to limit the present invention in any way. Any person skilled in the art can make many possible variations and simple substitutions to the technical solution of the present invention by using the methods and technical matters disclosed above without departing from the scope of the technical solution of the present invention, and these all fall into the scope of protection of the technical solution of the present invention.
Claims (9)
1. An industrial-scale clock controller, comprising:
a clock circuit for generating real time;
a power supply starting control port connected with the clock circuit, and outputting a power-on control signal to a main power supply after a preset time;
the first register is used for storing source information of a power-on control signal output by the industrial clock controller to the main power supply, and the source information of the power-on control signal comprises main power supply starting signal information input from an external pin of the industrial clock controller and main power supply starting signal information associated with the clock circuit;
the isolation circuit is used for isolating the main power side from rewriting the information in the first register in the starting process of the main power; and
a second register communicatively coupled to an external power enable pin from the industrial level clock controller and configured to drive a state of the power enable control port; and the second register and the first register are configured to be the same address; and when a write operation is performed on the address, data is written into the first register and the second register at the same time, and when a read operation is performed on the address, only configuration information of the first register is read out.
2. The industrial-level clock controller of claim 1, wherein the second register driving the state of the power-on control port comprises: driving the power supply starting control port according to first configuration information in the industrial clock controller to control the external power supply to be powered down; outputting a power-on control signal to a main power supply according to the clock circuit after the preset time, and controlling the external power supply to be powered on; and outputting a power-on control signal to a main power supply according to a power-on signal input by an external power-on pin of the industrial clock controller, and controlling the external power supply to be powered on.
3. The industrial level clock controller of claim 2, wherein a power wake-up register is further provided between the second register and the clock circuit, and the power wake-up register and the second register are in communication connection with an external power start pin of the industrial level clock controller through a first or gate circuit; when the clock circuit starts to output a high-level signal to the power supply wake-up register from T1 after a preset time, the power supply wake-up register inputs a high level to the first OR gate circuit; the power wake-up register also inputs a control signal to the second register through a synchronization circuit such that the second register is configured to input a high level to the first or gate beginning at T2.
4. The industrial-level clock controller of claim 3, wherein the isolation circuit comprises a first isolation circuit for controlling writing information, the first isolation circuit comprises a three and gate circuit and a two and gate circuit, and the input ends of the three and gate circuits are respectively connected with the output end of the power wake-up register, an externally input isolation signal and an external power start pin of the industrial-level clock controller; the input ends of the two AND gates are respectively connected with the output ends of the three AND gates and the externally input write signals, and the output ends of the two AND gates are connected with the first register.
5. The industrial level clock controller of any one of claims 1-4, wherein the isolation circuit comprises a second isolation circuit that controls reset information, the second isolation circuit comprising: the output end of the inverter is respectively connected with the input end of the second OR gate and the input end of the third OR gate, and the second OR gate and the third OR gate respectively receive a first reset signal and a second reset signal which are input from the outside; and the output ends of the second OR gate circuit and the third OR gate circuit are respectively connected with the input end of the first register and the input end of the second register.
6. An industrial-scale control system, comprising:
the industrial-scale clock controller of any one of claim 1-5,
peripheral bus, power manager, and connected to the industrial level clock controller
And the main power domain is respectively connected with the peripheral bus and the power manager.
7. The industrial level control system of claim 6, further comprising a battery electrically connected to the industrial level clock controller.
8. An electronic device, comprising:
the industrial grade control system of claim 6 or 7,
a memory, a peripheral circuit;
and the industrial level control system executes read-write and reset operations to registers in an industrial level clock controller in the industrial level clock controller according to the information in the memory and/or the state of the peripheral circuit.
9. A control method of an industrial-level clock controller, comprising:
when the industrial clock controller is electrified for the first time, a main power supply starting signal is input to an external pin of the industrial clock controller so as to drive an output pin connected with the output of the main power supply to output a high level;
the high level output by the output pin connected with the output of the main power supply drives the power supply manager to supply power to the main power supply;
when the industrial clock controller is restarted, isolating externally input information through an isolating circuit, wherein the input information is used for rewriting configuration information in a first register in the industrial clock controller; the configuration information in the first register comprises source information of a power-on control signal, wherein the source information of the power-on control signal comprises main power supply starting signal information input from an external pin of the industrial-level clock controller and main power supply starting signal information associated with a clock circuit; and is also provided with
Receiving communication information of an external power supply starting pin of the industrial clock controller through a second register, wherein the second register is used for driving the state of a power supply starting control port; and the second register and the first register are configured to be the same address; and when a write operation is performed on the address, data is written into the first register and the second register at the same time, and when a read operation is performed on the address, only configuration information of the first register is read out.
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