KR101815239B1 - An apparatus and method for optimizing the stanby power of a computer system by using a switching device - Google Patents

Abstract

The present invention relates to a computer system having various operating modes such as S0 to S5 modes. The computer system is more advanced in the technological aspect than what is currently being actively developed to block the standby power, minimizes the power consumption by only using the 5 VSB power supply for a circuit operation in a normal operation while using 3 VSB and/or 1.5 V for the remaining operations, is implemented with a single switching device, and blocks the 5VSB while recognizing the sleep mode on a software basis. The present invention also relates to the standby power optimization device of the computer system using the switching device and a method for the same. The standby power optimization device controls the switching devices (SW1, 40) applying relatively high-voltage first standby power to an advanced technology extended (ATX) power connector (21) of a switched mode power supply (SMPS) (20) from a signal input and output (SIO) unit (19) of a main board. The SIO (19) always supplies second standby power lowered to a relatively low voltage through a first converter (41) from the first standby power. The first standby power is separately supplied to a memory (10a, 10a) while being lowered to third standby power of a minimal voltage being supplied even in a sleep mode at the minimum. The first standby power is turned on or off by the switching device (4) by a control operation of the SIO control signals (5VSB_CTRL# signals). The first standby power is directly supplied to various components of the computer system or as a voltage lowered by a third converter even when the switching device is turned on. The second and third standby power can be continuously supplied to the corresponding devices.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an apparatus and method for optimizing a standby power of a computer system using a switching device,

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a technique for optimizing a standby power of a main board of a computer and a power supply supplied thereto from a stand-by mode, And more particularly, to an apparatus and method for optimizing a standby power of a computer system using a switching element that optimizes standby power by adding a simple switching element and solves the problem by software.

1, a power supply 20 such as an SMPS is connected to the SIO 12 of the main board 10 through 24 pins, one of which is connected to a standby Voltage (+ 5VSB).

When the user presses the power switch (not shown) of the PC case, the mechanically connected power button 13 is pressed, the power button 13 sends the first signal PWRBTN # to the SIO 12, The power supply 20 activates the power-on signal line PSON # with the power supply 20 and issues the second signal PWRBTN # _SB to the chipset 14. The power supply 20 is connected to the CPU 11 ) And the chipset 14 to inform it of the power supply signal, and then supply power to the main board.

Reference numeral 15 denotes a reset button of the chipset, 16 is a battery, 17 is a reset reset (17), and 18 is a LAN. In addition, AC, FWH, Super IO 19, AGP slot, PCI slot, IDE connected to the CPU and the chipset are connected.

Meanwhile, as described above, +5 V standby power is applied between the power supply 20 and the main board during non-operation, and standby power of about 1 W is required for recognizing the start button and recognizing the remote start do.

And this leads to a waste of energy, which is never high individually, and a huge amount of energy for a whole organization and even for a whole country.

In order to solve such a problem, there has been developed a socket having a switch which completely cuts off the power supply from the power socket itself to make the standby power zero (first prior art). On the other hand, Korean Patent Publication No. 2013-0043923 (Second conventional technique) for recognizing the on / off state of the power switch to completely shut off the power supply, such as the power supply device and the image forming apparatus including the power supply device.

However, in the case of the first prior art, in spite of the fact that it is practically possible for the user to sit in the outlet without turning off the power supply completely disconnected from the outlet, the second prior art is very complicated and expensive It is indispensable to mount such a device on a general PC.

Accordingly, the present inventor has proposed a computer power supply apparatus which is very simple but minimizes standby power automatically, and proposed Korean Patent No. 1328393 (name: computer power supply apparatus whose standby power is reduced) This will be described as a third prior art.

As shown in FIG. 2, the third prior art technology has a CPU 11, an SIO 12, a power button 13, a chipset 14, a reset button 15, a first battery 16, a LAN 18 ) And a super IO (19); An SMPS (20) for supplying power to the main board; A microcomputer 30 for controlling standby power supply of the SMPS; A power connector 60 for mediating signal and standby power connection between the main board and the SMPS; And a switching unit (40) for switching standby power on / off according to the control of the microcomputer. And the microcomputer 30 controls the standby power supplied to the main board by controlling the standby power (5VSB) of the power supply by the switching unit 40. [

2, the power supply apparatus of the third prior art includes an existing CPU 11, an SIO 12, a power button 13, a chipset 14, a reset button 15, A main board 10 having a power supply 16, a resetting reset 17, a LAN 18, a super IO 19, and the like, an SMPS 20 for supplying power to the main board, And a switching unit 40 for switching the standby power on / off according to the control of the microcomputer 30 and the microcomputer. The reference numeral 50 denotes a power switch of the PC case, and 60 denotes a power connector between the main board and the SMPS.

In the third prior art, the power connector 60 mediates signal and standby power connection between the main board 10 and the SMPS 20, and the SMPS 20 and the power connector are connected with 23 pins 1 is different from the conventional power supply of FIG. 1 in that a + 5V standby power line (+ 5VSB) which is one pin instead of a power connector is connected to the microcomputer 30 and the switching unit 40 instead of the power connector. The switching unit 40 may be a power switch IC or an FET circuit.

In addition, the microcomputer 30 receives the signal of either or both of the SMPS good signal (PS_ON #) and the power good signal (PWR_ON) from the SMPS 20 from the SMPS 20. The power good signal PWR_ON is also applied to the CPU 11 and the chipset 14.

Meanwhile, the microcomputer 30 also starts the standby power supply start operation by the switching signal CASE_PWR_BTN from the external case power switch 50, so that the standby power of +5 V (+ 5VSB) When the control signal 5VSB_SW of the microcomputer 30 is 'ON', the switching unit 40 applies the 5V standby signal P5V_STBY to the main board 10 through the switching unit 40, And the + 5V standby power (+ 5VSB) from the SMPS 20 is applied to the main board 10 as the 5V standby signal P5V_STBY.

From the SMPS (20) power connector to the mainboard (10) power connector, the PC's normal operating power goes to + 12V and -12V lines, + 5V standby power lines, + 3.3V power lines, and power hardening (PWR_ON) signals. However, the 5V standby power line (5VSB) goes to the switching device (40), and the standby power signal (P5V_STBY) goes from the switching device (40) back to the main board power connector.

Further, the standby power switch signal 5VSB_SW from the microcomputer 30 to the switching unit 40 and the power button signal MB_PWR_BTN to the main power button 12 go.

Conversely, the SMPS good (PS_ON #) signal goes from the mainboard 10 power connector to the SMPS 20 power connector.

First, the microcomputer 30 of the third prior art controls the standby power (5VSB) of the power supply by the switching unit 40 so as to control the power supplied to the main board When the power is off, the microcomputer senses the power cord PWR_ON and / or SMPS good signal (PS_ON #) between the connectors, and turns off the 5V standby power when the power is off. That is, in this case, since standby power is not supplied to the main board, the computer can not be turned on.

On the other hand, when the PC user presses the case power switch 50, the microcomputer 30 of the third prior art is activated by this signal, and the microcomputer controls the power good PWR_ON and / or the SMPS good PS_ON # And when the power is on, the control signal 5VSB_SW to the switching unit 40 is turned on so that the 5V standby power source 5VSB is applied to the main board. When the power button 13 of the main board is turned on, an input / output start command is issued to the SIO 12, and the SIO 12 transmits power supply completion signal PS_ON # to the SMPS 20 via the power connector 60. [ The SMPS transmits the PWR_ON signal to the main board 10 via the connector 60 and activates the main board operation power source (+12 V) when the situation is normal.

Therefore, according to the third prior art, standby power and computer start-up can be performed only by standby power of about 0.1 W corresponding to the standby power of the microcomputer without consuming standby power of 1 W corresponding to standby power of the computer activation system There are advantages.

Unlike conventional systems that only have the system power 'on' and 'off' states, modern PCs adopt the S1 to S5 mode, adopting various granular modes and thus the most efficient System operation. For reference, the S0 mode is a computer operation mode, the S1 mode is a state in which the processor is in an idle state and is in a low power supply state or a state in which power is still supplied to the RAM, and S2 mode is a deep sleep mode However, in the S3 mode (power saving / standby mode), the power is still supplied to the RAM. In this case, the + 5V SB should not be turned off as the data is stored in the memory and the minimum power is maintained. At this time, depending on the type of DDR memory, VDD power is maintained at 1.2 ~ 1.5V, but power is supplied only to some parts such as memory and RTC. On the other hand, in S4 mode (hibernate mode), the data is stored on the hard disk and all the system power is turned off. That is, it is almost the same as the power OFF state. At this time, VDD power of memory is output as 0 V as when power is OFF. In other words, the VDD signal is 0 V in the OFF state of the system standby power and in the case of the S4 mode, and the system operation which is the standby power ON condition (Power ON state) and S3 (power saving / standby mode), the VDD signal outputs 1.2 to 1.5V.

Therefore, in the case of the system having the recent S0 to S5 mode, in the case of the third prior art, it is necessary to check all the states of the power source in order to block such standby power. 2) Checking some signals such as 'power good', and checking them. 1) When checking the current, an expensive analog-to-digital converter (ADC) and a peripheral circuit are required There is no cost-effective value to reduce standby power of 1W. 2) Also, when checking through signals such as 'power good', all power can not be checked by one signal. Therefore, Structure, which leads to a problem of low production efficiency.

On the other hand, a conventional general power-on operation will be described with reference to Figs. 3 to 7. Fig.

3, the PS_ON circuit 19a in the super IO 19 recognizes the power ON state when the power button is turned on, as shown in FIG. 3, The PS_ON # terminal of the 20-pin connector of the SIO 12 of the main board 10 is activated while communicating with the south bridge of the chipset 14 so that power is applied to the main board 10.

An example of the block diagram of the PS_ON circuit 19a of FIG. 3 is shown in detail in FIG. 4, when the switch S1 corresponding to the power button is pressed, the PS_ON circuit 19a is activated while falling to a low level, so that various voltages are applied from the SMPS to the main board (See the timing chart of Fig.

On the other hand, FIG. 6 shows another example of a conventional power-on operation concept. When power-on switching (PWR) is performed, the chipset 14 transmits the P.ON signal to the SIO 12, And the SIO 12 outputs the PON signal to the PS_ON # terminal of the connector of the main board so that the power is applied from the SMPS to the main board.

FIG. 7 is a timing chart of the signals of FIG. 6, and when the VAC is activated (AC power is applied), the PS_ON # signal is activated while falling to a low level and various voltages are applied from the SMPS to the main board, It responds with a good signal.

6, the PS_ON # signal (SMPS power on) is also turned on first by turning on the + 5V SB signal and then by connecting the south bridge and the Super I / O chipset , The PS_ON # signal is generated in the SMPS, and the connection and remodeling workability of the cable is poor, resulting in low productivity.

In order to solve the above problems, the inventor of the present invention has proposed a computer power supply apparatus which is very simple and automatically minimizes standby power even in a computer system having various operation modes, And proposed a computer power supply device that reduces standby power and has been patented as a patent No. 1623756. [ This will be described with reference to FIG. 2 and FIGS. 8 to 10. FIG.

FIG. 8 is a block diagram of a computer power supply apparatus in which standby power is reduced according to a fourth conventional technique, FIG. 9 is a detailed circuit diagram of a computer power supply apparatus in which standby power is reduced according to a fourth conventional technique, 4 is a flowchart of the operation of the microcomputer of the computer power supply apparatus in which the standby power according to the related art is reduced.

First, the invention of the fourth related art will be described with reference to the block diagram of FIG. 8. First, it is detected whether the PC power source 50 is 'on', and the ATX power cable from the SMPS 20 to the main board Activate the PS_ON # signal to the 'low' level, causing the line except the 5V SB line to go to the mainboard. At this time, the 5V SB line does not go directly to the main board but provides Vcc to the microcomputer 30 and the first switching unit 40 and activates them, thereby activating the power control signal PWR_CTRL, The first switching unit 40 sends the power output signal PWR_OUT to the 5V SB terminal of the mainboard so that the main board is operated while all the power is supplied to the main board do.

At this time, the microcomputer 30 applies the PS_ON # signal to the SMPS 20 to turn on the SMPS, and the signal and the common ground signal interlocked therewith are transmitted from the SMPS to the main board 10 via the ATX cable, The microcomputer 30 may directly supply the PS_ON # signal to the main board through the second switching unit 41 without passing through the SMPS, as shown in FIG. 8, , But it is also possible to apply it to the PS_ON # terminal of the power connector 60 through the power button 13, the PS_ON circuit 19a, and the main board.

9, the on / off state of the PC power 'on' switch 50 is provided through the switching input (SW_IN) terminal (pin 16 of the chip) of the microcomputer 30 .

Thereafter, the microcomputer 30 activates the common ground terminal (turns from 'high' to 'low') so that all of the 5V, 3.3V, 12V, power cord (PWR_OK) So that various powers are applied from the SMPS to the main board. In addition, the PS_ON # signal may be output to the SMPS 20 through the PS_ON # terminal (pin 2 of the chip) and may be connected to the corresponding terminal of the power connector 60 of the main board 10 through the ATX power cable 9, the SW_OUT signal is output to the second switching unit 41 through the fifth terminal of the microcomputer, and the switching signal is output to the super IO 19 through the power button # 13 in the main board To the corresponding terminal of the power connector 60 by activating the PS_ON circuit 19a.

The power control signal PWR_CTRL is output through the 14th pin of the microcomputer 30 to activate the first and third transistors Q1 and Q3 of the switching unit 40 to output the power output PWR_OUT signal To the 5V standby signal terminal of the connector of the main board 10. This means that the main board (computer) including the function of the memory finally operates.

Lastly, the voltage supplied to the memory (for example, DDR3) of the main board 10 is sensed by the fourth transistor Q4 of the sensing unit 70, and the result is the power GD_PWR Pin 15 of the chip).

The operation of the microcomputer of the fourth conventional art will be described once again with reference to FIG.

First, the microcomputer 30 of the present invention is operated when the system standby power is in the off state (in a state in which the AC power is not inputted). (S1). In such a case, is the PC power switch "on"? The power control signal PWR_CTRL (PWR_CTRL) is set to the power control signal PWR_CTRL (step S2). If the power control signal PWR_CTRL The switching unit 40 sends the power output signal PWR_OUT to the 5V SB terminal of the mainboard so that all the power is supplied to the main board S3). At the same time, the power button # 13 is activated and the PS_ON # signal is activated to operate the main board (S4 ').

That is, the microcomputer 30 receives a signal that the PC power switch is 'on', activates the power control signal PWR_CTRL to the first switching unit 40, and outputs the power output signal PWR_OUT) to the 5V SB terminal of the main board to supply all the power to the main board (S3) and to output the switching-out signal (SW_OUT) to another second switching unit 41 The transistor Q2 of the second switching unit 41 is turned on and the PS_ON # signal is applied to the power button 13 of the main board so that the power button 13 and the super I / The PS_ON # terminal of the connector 60 is activated through the PS_ON circuit 19a of the controller 19 to operate the main board (S4 ').

Thereafter, the voltage V _DD supplied to the memory 10a of the main board is checked (S5), and it is determined whether it is less than a predetermined voltage (for example, 0.7 V) (S6). If the voltage is abnormal ), The 5V SB power 'on' state is maintained and power supply to the main board is continued. Otherwise, the memory is considered to have stopped operating, and the power control signal PWR_CTRL is deactivated, The switching unit 40 disables the power output signal PWR_OUT and turns off the system standby power in step S7.

That is, as described above in the related art, the + 5V SB should not be turned off in the S3 mode (power saving / standby mode), while in the S4 mode (the maximum power saving mode) Turn off all power. That is, in the S4 mode and the S5 mode in which the power is OFF, 0V is output. In other words, the VDD signal is 0 V in the OFF state of the system standby power and in the case of the S4 mode, and the system operation which is the standby power ON condition (Power ON state) and S3 (power saving / standby mode), the VDD signal outputs 1.2 to 1.5V. Therefore, in S5 and S6, the voltage V _DD supplied to the memory is checked (S5), and it is determined whether or not it is less than a predetermined voltage (Vr: 0.7 V, for example) The power 'on' state is maintained, and less than (V _DD ≪ Vr), the system standby power is turned off (S7).

The fourth prior art recognizes the S3 and S4 modes by a relatively simple method of checking the voltage (V _DD ) supplied to the memory and continues to supply the 5V standby power in the S3 mode, In the S4 mode, the standby power is cut off to save power in the dash mode. However, there is an advantage that it can be performed without additional cable construction.

However, in S3 (standby / power saving mode), in addition to the specific mode, there is no need to supply standby power of 5 V, and only standby power of about 3 V is sufficient.

In addition, in the above-mentioned conventional techniques, since the mode recognition such as S3 and S4 is checked with a voltage in a secondary device such as a memory, a separate device for checking the mode is necessary. In addition, In addition, although there is a very low possibility of wiring to the microcomputer, there is a problem that the system can not accurately sense the inconsistency between the secondary device such as the current mode and the memory due to the error of the system. Mode, even if the memory and the like have to be supplied with a minimum amount of power, the countermeasures against it are insufficient.

Korean Patent Publication No. 2013-0043923 (Patent Application No. 2011-0108115) Korea Patent No. 1328393 (name: computer power supply device for saving standby power) Korean Patent No. 1623756 (Title: Standby power cutoff method of standby power cutoff device using system memory power)

The present invention provides a 5VSB power supply for circuit operation only in normal operation, in a computer system having various operation modes (for example, S0 to S5 mode) And the other driving is to use 3VSB and / or 1.5V to minimize the power consumption, realize it with only one switching device, and realize software mode of sleep mode recognition and 5VSB blocking. Standby power optimization apparatus and method.

In order to achieve the above object, a standby power optimizing apparatus for a computer system using a switching device according to an aspect of the present invention includes a CPU 11, an SIO 19, a chipset 14, and a memory 10a. A system for optimizing the standby power of a computer system including a board, an SMPS (20) having an ATX power connector (21), and various peripherals, wherein the SIO (19) (SW1) 40 for turning on / off the application of a first standby power supply of a general standby voltage (5VSB) to the first standby power supply 21, and the first standby power supply is connected to the first standby power supply (3VSB) than the first standby power source through the converter 41, and the first standby power source is supplied at least through the second converter 43 in the sleep mode as well To the third standby power supply of the minimum voltage to be stored in the memory 10a, 10a ' The first standby power supply is turned on / off by the switching device 40 under the control of the SIO control signal (5VSB_CTRL # signal), so that the first standby power supply is turned on only when the switching device is turned on The second standby power is supplied to the various elements of the computer system by the power supplied directly or by the third converter and the second standby power is stepped down to the low voltage (3VSB) by the first converter 41, And the third standby power supply is supplied to the elements to be supplied with a minimum voltage like the memory by the second converter 43 .

Preferably, the OS 10c of the main board has information on the CPU, the memory 10a, and the application 90, so that if the CPU usage is less than a predetermined value, And stops the operation of the CPU core of the predetermined part according to the CPU usage amount and operates the entire CPU core.

More preferably, the first standby power source is lowered to the low voltage (3VSB) by the third converter 42 and then supplied to devices for external communication such as a USB or LAN connector. Even if it is not in the sleep mode And the power supplied to devices for external communication such as a USB or LAN connector is shut off if the CPU usage is below a predetermined value.

According to another aspect of the present invention, there is provided a method for optimizing a standby power of a computer system using a switching device, the method comprising the steps of: (a) when the power is on and the computer system is started, By supplying the first standby power to the entire system by turning on the switching device 40 and supplying all operation power (3V, 5V, 12V, etc.) to various devices on the main board through the ATX power connector (S12); (b) the SIO checks the CPU usage with the chipset, and checks whether the CPU usage is less than a predetermined level (S13); (c) performing energy use optimization including performing a predetermined level (50%) or more as a result of the determination in step (b) and turning off a certain portion of the CPU core if the predetermined level is less than 50% (S14); (e) checking the CPU usage amount again to determine whether the CPU usage amount checked again is less than a predetermined level (S17); (f) If it is determined in step (e) that the CPU usage amount is equal to or higher than a predetermined level, the CPU core is all turned on again, and the energy usage optimization execution is canceled (S18) ; (g) checking whether the computer system is in the S3 mode (sleep mode) if the CPU usage is less than a predetermined level as a result of the determining in the step (e); And (h) returning to step (e) if it is not the S3 mode as a result of the determination in step (g), and turning off the switching element when the mode is the S3 mode, Stopping power supply (S20); And a control unit.

According to another aspect of the present invention, there is provided a method of optimizing standby power of a computer system using a switching device, the method comprising the steps of: (a) when the power is turned on and a computer system is started, 5V, 12V, and the like) to various devices on the main board through the ATX power connector 21. The first standby power is supplied to the entire system by turning on the switching device 40, (S12); (b) the SIO checks the CPU usage with the chipset, and checks whether the CPU usage is less than a first reference value (S13); (c) repeating the step (b) if the first reference value is equal to or greater than the first reference value, and turning off a predetermined portion of the CPU core if the first reference value is less than the first reference value S14); (e) checking the CPU usage amount again to determine whether the CPU usage amount checked again is less than the first reference value (S17); (f) If the CPU usage amount is equal to or greater than the first reference value as a result of the determination in step (e), the entire CPU core is turned on again, and the energy use optimization execution is canceled (S18) ; (g1) As a result of the determination in the step (e), it is checked whether the CPU usage amount is less than the first reference value and the CPU usage amount is checked again, and the CPU usage amount is less than the second reference value which is lower than the first reference value Step S31; (g2) If it is determined in step (g1) that the CPU usage amount is between the first reference value and the second reference value, the process returns to step (e) to continuously check the CPU usage amount, If the memory usage is less than the second reference value, checking whether the memory usage change amount is less than a predetermined reference value (S32); (g3) As a result of the determination in step (g2), if No is returned to the step (b) and the CPU checks again from the beginning and if the result is Yes, Blocking the function and the peripheral device (S33); (g4) checking whether the CPU usage amount or the memory usage amount has increased after the step (g3) (S34); (g5) As a result of the determination in step (g4), if there is no change, the control unit continuously checks whether the CPU usage amount is equal to or greater than the second reference value. (g6) If it is determined in step (g5) that the CPU usage amount is equal to or greater than the second reference value, the CPU clock is turned on to restart the entire CPU operation, and the network function and the peripheral device are also activated (S36) Returning to the step of performing the CPU usage check again; (g7) step (S19) of checking whether the computer system is in the S3 mode (sleep mode) if the CPU usage amount is less than the first reference value as a result of the determination in the step (g5); And (h) stopping the first standby power supply to the system by turning off the switching element (40) if it is determined to be the S3 mode as a result of the determination in the immediately preceding step (S20); If it is determined in step (g7) that the current mode is not the S3 mode, the process returns to step (g5) and repeats the process.

Preferably, after step (h), (j) checking whether the computer system wakes up (S22); And (k) when the wake-up has occurred as a result of the checking in the step (j), the first standby power supply to the entire system is resumed by turning on the switching device 40 (S23) Returning to step < RTI ID = 0.0 > And further comprising:

More preferably, (m) step (S24) is performed to check whether the wake-up has not occurred in S4 mode (hibernation mode) or S5 mode (off mode) ; And (n) returning to step (j) after a predetermined period of time, if it is not the S4 mode or the S5 mode as a result of the determination in step (m) When it is determined that S4 mode or S5 mode has occurred, the SIO 19 supplies all the operation power (3V, 5V, 12V, etc.) to various devices on the main board through the ATX power connector 21 Step S25 to stop; And further comprising:

Preferably, after step (c), (d) checking whether or not the additional application 90 has been executed (S15), and if the additional application has been executed, waiting for a predetermined time for loading the program (step S16); Wherein the execution of the energy use optimization in the step (c) includes not only turning off a certain portion of the CPU core, but also performing the " interruption of the unused interface " And at least one of them is further included.

According to the apparatus and method for optimizing the standby power of a computer system using the switching device according to the present invention, energy savings can be achieved by minimizing standby power cutoff and operating power by using minimum components in a computer system having various operation modes, In addition, it is possible to optimize the standby power by operating only necessary devices at the time of operation.

Other objects and advantages of the present invention will become apparent from the detailed description of the embodiments with reference to the attached drawings.

1 is a conceptual diagram of a conventional computer power supply;
2 is a block diagram of a computer power supply in which standby power is reduced according to the third prior art.
3 is a view for explaining a concept of a conventional general power-on operation;
4 is a block diagram of the PS_ON circuit 19a of Fig.
5 is a timing chart of the signals of FIG. 3;
FIG. 6 is another example of a concept of a conventional general power-on operation; FIG.
FIG. 7 is a timing chart of the signals of FIG. 6; FIG.
FIG. 8 is a block diagram of a computer power supply in which standby power is reduced according to a fourth prior art; FIG.
FIG. 9 is a detailed circuit diagram of a computer power supply apparatus in which standby power is reduced according to a fourth prior art; FIG.
FIG. 10 is a flowchart illustrating an operation of a microcomputer of a computer power supply apparatus according to a fourth prior art in which standby power is reduced. FIG.
11 is a block diagram of a computer system according to the first embodiment of the present invention.
12 is a flowchart illustrating an operation method of a computer system according to the first embodiment of the present invention;
13 is a flowchart illustrating an operation method of a computer system according to a second embodiment of the present invention;

Hereinafter, preferred embodiments according to the present invention will be described in detail with reference to the accompanying drawings.

FIG. 11 is a block diagram of a computer system according to the first embodiment of the present invention, and FIGS. 12 and 13 are operational flowcharts showing a method of operating a computer system according to the first and second embodiments of the present invention .

It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the invention, You will know.

(A standby power optimizing apparatus of a computer system according to the first embodiment of the present invention)

First, a standby power optimizing apparatus for a computer system using a switching device according to the first embodiment of the present invention will be described with reference to FIG.

11, in the main board, the SIO 19 is connected to the ATX power connector 21 of the SMPS 20 at a relatively high voltage (5VSB) corresponding to a normal standby voltage, (SW1) 40 for turning on / off the application of the first standby power source of the first standby power source.

The ATX power connector (21) is connected to the auxiliary connector only for the 5VSB terminal, and the remaining power supplies (5V, 3.3V, 12V, etc.) are connected to the main connector and are commonly grounded. 19) of the common ground terminal.

Meanwhile, the second standby power source, in which the first standby power source of 5VSB is stepped down to the relatively low voltage (3VSB_IO) via the first converter 41, is always supplied to the SIO 19, In addition to the switching of the power button 13, it is necessary to check the operation of the keyboard or the mouse. In addition to the chipset 14, it is necessary to monitor the I / O device in the sleep mode or other boot mode. This is because it is necessary to control the first standby power source of 5VSB to be applied to the system in recognition of the switching. For reference, the second standby power supply is simultaneously supplied to the keyboard 70 and the keyboard 70.

On the other hand, the first standby power source of the 5VSB is supplied to the memory 10a or 10a '(for example, a DDR memory) separately from the third standby power source of the minimum voltage (1.5V) through the second converter 43 For example, in S3 sleep mode, the first standby power supply of 5VSB to the system is cut off, but the minimum power must be supplied to the memory even in the S3 sleep mode. In this case, the minimum standby power (approximately 1.2W) This is because only the third standby power supply of 1.5 V is sufficient. In addition, the third standby power supply must be supplied to the CPU 11 and the chipset 14 as well.

The CPU is interfaced with the HDMI connectors 31 and 32 through the 'Port B' and the 'Port C' and is connected to the LVDS connector 34 through the 'Port D' And exchange information with them. Furthermore, the CPU 11 is also connected to an EDP (Electronic Data Processing) device 35 via a 'port E', and on the other hand, the DDR memories 10a and 10a ').

In addition, the chipset 14 is connected to the LANs 18 and 18 'and the PCIe device 15 by a PCIe method, and is connected to the keyboard 70 and the mouse 70 by the PS2 or USB method, , SPI flash 73 and serial ATA cable 74, such as SATA3, for example. The chipset 14 is also connected to a hardware monitoring device 80 via a watchdog 82, fans 83 and 84, a communication module 85, a H / W monitor 86, a DIO 87, / MS < / RTI >

On the other hand, the first standby power supply of 5VSB is turned on / off by the switching element 40 as described above, and is supplied as AVDD to the audio codec 75 and the audio amplifier 77 of the entire system.

In addition, the first standby power source of the 5VSB is depressed to 3VSB by the third converter 42, and then is supplied to the USB 3.0 71, the USB 2.0 72, the SPI flash 73, a LAN Connectors 18a and 18a 'are supplied to the AVDD 33 on an interface 15 such as PCIe.

The reference numerals 41a, 42a and 43a denote loads to be added together with the resistors and the capacitors to the first converter 41, the third converter 42 and the second converter 43, Reference numeral 81 denotes a TPM, reference numeral 75 denotes an audio codec, reference numeral 76 denotes an audio input / output device, reference numeral 77 denotes an audio amplifier, and reference numeral 78 denotes a speaker.

In particular, in the system of the present invention, the CPU 11 and the chipset 14 are designed to optimize standby power in the sleep mode in a manner programmed by the OS 10c according to the execution of the application 90, 12 will be described later.

According to the standby power optimizing apparatus for a computer system using the switching device according to the present invention, a standby power minimizing method is provided by a simple switching device SW1, so that the added cost can be minimized while implementing the optimal function As a method of energy saving in the system standby mode, a third standby power source (1.5V) as a memory power source is separated from a normal standby power source (5VSB) and a second standby power source (3VSB) 1 and the second standby power can be shut down. Since the recent PC use time is reduced to a smart phone or the like, it is optimized for power consumption reduction such as reduction of standby power interruption and energy consumption of standby mode S3. In addition, the performance of computers compared to the programs used for general office use is very high, and the multi-PCs that are used by multiple users on one computer share this performance, and the tendency to utilize the idle resources of the computers, And application programs. In addition, when a problem occurs in installing a program by a user or a problem with a virus, etc., the whole system is down or infected and there are many problems in usage. This reduces energy consumption by reducing the number of CPU cores or by turning off unused interfaces, depending on the program load you are using. Examples of unused interface types include USB, LAN, PCI Ex, and AUDIO. Energy optimization sets include "Hyper threading off", "Limiting the active processor core to two or four in total""Intel C-status enable", "C1E support enable" (a function that lowers the clock when the CPU usage is low), and the like.

(A method for optimizing standby power of a computer system according to the first embodiment of the present invention)

Now, a standby power optimization method for a computer system using the switching device according to the first embodiment of the present invention will be described with reference to FIG.

12, when the user presses the power button 13 to turn on the power and the computer system starts, the 5VSB_CTRL # signal is set to "L" to turn on the switching element 40, (3V, 5V, 12V, etc.) to various devices on the main board through the ATX power connector 21 (S12).

Now, the SIO checks the CPU usage with the chipset and checks whether the CPU usage is less than a certain level (e.g., 50%) (S13). If the CPU usage is above a certain level (50% (50%), optimization of energy use is performed. For example, a certain portion (for example, half) of the CPU core is turned off (S14). That is, two CPU cores are turned off in a system having four CPU cores and four cores are turned off in a system having eight CPU cores. In addition, as described above, optimization of energy use such as shutting down unused interfaces or lowering the CPU clock is performed.

It is checked whether or not the application 90 has been further executed (S15). If the additional application has been executed, the CPU waits for a predetermined time for loading the program (S16). If there is no additional application execution, If it is determined that the CPU usage amount is less than a predetermined level (for example, 50%) (S17), the CPU core is turned on again (S18) And repeats the process from step S13.

If it is determined in step S17 that the CPU usage is less than a predetermined level (50%), it is checked whether the computer system is in the S3 mode (sleep mode) (S19) (S3), the 5VSB_CTRL # signal is set to 'H', and the switching device 40 is turned off, thereby stopping the supply of the first standby power of 5VSB to the system (S20) .

For reference, the S3 mode (sleep mode) has been proved. Even if the first standby power supply of 5VSB is interrupted, the supply of the third standby power supply of 1.5V still continues (S21), and the SIO occasionally wakes up (Step S22). When wake-up occurs, the 5VSB_CTRL # signal is set to "L" to turn on the switching element 40 to resume the first standby power supply to the entire system ) (S23), the process returns to step S13 and repeats the process from step S13.

On the other hand, if it is determined in step S22 that wake up has not occurred, the SIO will check whether it is an S4 mode (maximum power saving mode) or an S5 mode (off mode) As a result of the determination in step S24, if it is not the S4 mode or the S5 mode (the S3 mode continues), the process returns to step S22 after a predetermined period of time to repeat the process of checking whether wake- do.

On the other hand, if it is determined in step S24 that the S4 mode or the S5 mode has occurred, the SIO 19 sets the PS_ON # signal to 'H' (S25) to stop supplying all the operation power (3V, 5V, 12V, etc.) to the power supply of the computer system.

According to the apparatus and method for optimizing the standby power of a computer system using the switching device of the present invention, it is possible to efficiently supply the first standby voltage of 5VSB in the sleep mode of the computer system by simply adding the very simple switching device 40 Ii) By adding only the first converter 41, the 3VSB voltage of low voltage is selectively applied instead of 5VSB depending on the characteristics of the apparatus during operation as well as during operation of the computer system to reduce the total power consumption, iii) By adding only the second converter 43, it is possible to multiplex various standby power supplies so as to continuously supply the minimum (for example, 1.5V) third standby power supply to the memory in which the minimum power must be supplied even in the sleep mode, Iv) In addition, by analyzing the degree of CPU usage by software, CPU usage is constant (eg 50%), (By example in the off part of the CPU core) to conduct hayimyeon energy use optimization is also possible to reduce the overall system power consumption.

(A method for optimizing standby power of a computer system according to a second embodiment of the present invention)

Now, a standby power optimization method of a computer system using a switching device according to a second embodiment of the present invention will be described with reference to FIG.

The difference between the second embodiment and the first embodiment will be described. In the case of the first embodiment, if the CPU usage is less than the first reference value (50%) as a result of the determination in step S17, (S19). If the mode is not the S3 mode, the process returns to the step S17 and is repeatedly performed from the step S17. If the mode is the S3 mode, the 5VSB_CTRL # (S20). On the contrary, in the case of the second embodiment, it is checked whether or not the S3 mode (sleep mode) is directly set even when the CPU usage amount is less than the first reference value (50%) (Sleep mode) while intercepting the network differently depending on whether or not the CPU usage amount is less than the second reference value (5%) which is the minimum reference value lower than the first reference value (50% Check to 5V It is determined whether or not to stop the first standby power supply of the SB.

More specifically, as shown in FIG. 13, which is a comparison with FIG. 12, the CPU usage is checked in steps S11 to S18, that is, in step S17, and the CPU usage is reduced to a first reference value (for example, 50% If the first reference value is 50% or more, the entire CPU core is turned on again (S18), and the process returns to step S13 and repeats the process from step S13.

However, if it is determined in step S17 that the CPU usage amount is less than the first reference value (50%) and the CPU usage amount is again checked, the CPU usage amount is less than the first reference value (50% 5%) (S31). If the CPU usage amount is between the first reference value and the second reference value (5 to 50%), the process returns to step S17 to continuously check the CPU usage amount, If the CPU usage amount does not reach the second reference value (5%) which is the minimum reference value, it is checked whether the memory usage change amount is less than the minimum reference value (e.g., 5%) (S32).

As a result of the determination in step S32, if it is determined to be No, it is determined that the memory usage has surged. Therefore, the process returns to step S13 to check again from the beginning. If the result is Yes, (PCI ON # = 'H') (S33) by stopping the entire CPU operation by turning off the CPU clock and blocking the network function and the peripheral devices.

Then, it is checked whether the CPU usage amount or the memory usage amount has increased. If the CPU usage amount or the memory usage amount has increased, it is checked whether the CPU usage amount or the memory usage amount has increased. , The CPU clock is turned on in accordance with the wakeup to resume the entire CPU operation, and the network function and the peripheral device are also activated (PCI ON # = 'L') (S36) .

If it is determined in step S35 that the CPU usage amount is less than the second reference value (5%) which is the minimum reference value, the computer system checks whether the computer system is in the S3 mode (sleep mode) If the mode is not the mode, the process returns to step S35 and is repeatedly performed from step S35. If the mode is the S3 mode, the switching device 40 is turned off by setting the 5VSB_CTRL # signal to "H" (S20).

Since steps S20 to S25 are the same as those of the first embodiment, detailed description thereof will be omitted.

It should be noted that the first reference value and the second reference value are not necessarily limited to 50% and 5%, and it is obvious to those skilled in the art that a somewhat different value is not outside the scope of the present invention. If the reference value is lower than the first reference value, it suffices. However, if the second reference value is set too high, the user may approach the deep sleep mode even though the user is performing the operation, and it may be rather inconvenient. Therefore, it is preferable to hold the second reference value not too high. Generally, it is preferably about 2 to 15%, more preferably about 3 to 10%, and most preferably 5%.

Therefore, according to the second embodiment, when the CPU usage is less than or equal to a predetermined first threshold value (50%), only some CPU cores are turned off in the first place, and when the CPU usage is less than the minimum reference value (5% The device also has the added advantage of being able to save 5VSB, still in standby mode, while still saving energy, by shutting down the device.

While the present invention has been described in connection with what is presently considered to be practical exemplary embodiments, it is to be understood that the invention is not limited to the disclosed embodiments, but, on the contrary, Of course.

(Prior art)
10: Motherboard
11: CPU 12: SIO (System IO)
13: Power button 14: Chipset
15: reset button 16: first battery
17: RESET RESET 18: LAN
19: Super IO (Super IO) 19a: PS_ON circuit
20: Power supply (SMPS) 30: Microcomputer
40: first switching unit 41: second switching unit
50: Case power switch 60: Power connector
70: V _DD sensing unit
(Invention)
10: main board 10a, 10a ': memory
10c: OS 11: CPU
13: Power button 14: Chipset
15: PCIe 18, 18 ': LAN
19: SIO
20: Power supply (SMPS) 41: ATX power connector
40: switching element 41: first converter
42: third converter 43: second converter
70: Keyboard and mouse 80: Hardware monitoring device
90: Application

Claims (8)

A computer system including a main board including a CPU 11, an SIO 19, a chipset 14 and a memory 10a, an SMPS 20 having an ATX power connector 21, As a standby power optimizer,
In the main board, the SIO 19 controls the switching element SW1 40 that turns on / off the application of the first standby power supply of the general standby voltage (5VSB) to the ATX power connector 21 of the SMPS 20 and,
The first standby power source is always supplied with the second standby power that is lowered to a low voltage (3VSB) than the first standby power source through the first converter 41,
The first standby power source is supplied to the memory 10a or 10a 'separately by being supplied to the third standby power source of the minimum voltage to be minimally supplied even in the sleep mode through the second converter 43,
The first standby power source is turned on / off by the switching device 40 under the control of the SIO control signal (5VSB_CTRL # signal), so that the first standby power source is turned on only when the switching device is turned on, To the various components of the computer system,
The second standby power source is supplied to the devices that are operated in the sleep mode including the SIO 19 by being lowered to the low voltage (3VSB) by the first converter 41,
And the third standby power supply is supplied to the elements, such as the memory, to which a minimum voltage is to be supplied by the second converter (43). The method according to claim 1,
The OS 10c of the main board has information on the CPU, the memory 10a, and the application 90. If the CPU usage is below the predetermined value even if the sleep mode is not selected, And stops the operation of the CPU core of the predetermined portion according to the amount of the CPU usage and also operates the entire CPU core. 3. The method of claim 2,
The first standby power source is reduced to the low voltage (3VSB) by the third converter 42 and then supplied to devices for external communication such as a USB or LAN connector,
The power supply to devices for external communication such as a USB or LAN connector is shut off when the CPU usage is below a predetermined value even if the sleep mode is not used. A standby power optimization method for a computer system using a switching device using a standby power optimization apparatus of a computer system using the switching element of claim 1,
(a) When the power is turned ON and the computer system is started, the SIO 19 turns on the switching device 40 to supply the first standby power to the entire system, and the ATX power connector 21 A step S12 of supplying all the operation power sources (3V, 5V, 12V, etc.) to the various devices on the main board through the step S12;
(b) the SIO checks the CPU usage with the chipset, and checks whether the CPU usage is less than a first reference value (S13);
(c) repeating the step (b) if the first reference value is equal to or greater than the first reference value, and turning off a predetermined portion of the CPU core if the first reference value is less than the first reference value S14);
(e) checking the CPU usage amount again to determine whether the CPU usage amount checked again is less than the first reference value (S17);
(f) If the CPU usage amount is equal to or greater than the first reference value as a result of the determination in step (e), the entire CPU core is turned on again, and the energy use optimization execution is canceled (S18) ;
(g) checking whether the computer system is in the S3 mode (sleep mode) if the CPU usage amount is less than the first reference value (S19) as a result of the determination in the step (e); And
(h) stopping the first standby power supply to the system by turning off the switching device (40) if the mode is the S3 mode as a result of the determination in the immediately preceding step (S20);
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And if it is not the S3 mode as a result of the determination in step (g), the method returns to step (e) and repeats the operation. A standby power optimization method for a computer system using a switching device using a standby power optimization apparatus of a computer system using the switching element of claim 1,
(a) When the power is turned ON and the computer system is started, the SIO 19 turns on the switching device 40 to supply the first standby power to the entire system, and the ATX power connector 21 A step S12 of supplying all the operation power sources (3V, 5V, 12V, etc.) to the various devices on the main board through the step S12;
(b) the SIO checks the CPU usage with the chipset, and checks whether the CPU usage is less than a first reference value (S13);
(c) repeating the step (b) if the first reference value is equal to or greater than the first reference value, and turning off a predetermined portion of the CPU core if the first reference value is less than the first reference value S14);
(e) checking the CPU usage amount again to determine whether the CPU usage amount checked again is less than the first reference value (S17);
(f) If the CPU usage amount is equal to or greater than the first reference value as a result of the determination in step (e), the entire CPU core is turned on again, and the energy use optimization execution is canceled (S18) ;
(g1) As a result of the determination in the step (e), it is checked whether the CPU usage amount is less than the first reference value and the CPU usage amount is again checked. If the CPU usage amount is less than the first reference value, Step S31;
(g2) If it is determined in step (g1) that the CPU usage amount is between the first reference value and the second reference value, the process returns to step (e) to continuously check the CPU usage amount, If the memory usage is less than the second reference value, checking whether the memory usage change amount is less than a predetermined reference value (S32);
(g3) As a result of the determination in step (g2), if No is returned to the step (b) and the CPU checks again from the beginning and if the result is Yes, Blocking the function and the peripheral device (S33);
(g4) checking whether the CPU usage amount or the memory usage amount has increased after the step (g3) (S34);
(g5) As a result of the determination in step (g4), if there is no change, the control unit continuously checks whether the CPU usage amount is equal to or greater than the second reference value.
(g6) If it is determined in step (g5) that the CPU usage amount is equal to or greater than the second reference value, the CPU clock is turned on to restart the entire CPU operation, and the network function and the peripheral device are also activated (S36) Returning to the step of performing the CPU usage check again;
(g7) step (S19) of checking whether the computer system is in the S3 mode (sleep mode) if the CPU usage amount is less than the first reference value as a result of the determination in the step (g5); And
(h) stopping the first standby power supply to the system by turning off the switching device (40) if the mode is the S3 mode as a result of the determination in the immediately preceding step (S20);
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And if it is not the S3 mode as a result of the determination in step (g7), the method returns to step (g5) and repeats the operation. 6. The method according to claim 4 or 5, wherein, after the step (h)
(j) checking whether the computer system wakes up (S22); And
(k) If the wake-up has occurred in step (j) as a result of the checking in step (j), the first standby power supply to the entire system is resumed by turning on the switching device 40 (S23) Returning to step;
Further comprising the steps of: determining a standby power of the computer system; The method according to claim 6,
(m) If it is determined in step (j) that the wake-up has not occurred, step (S24) is performed to check whether it is an S4 mode (hibernation mode) or an S5 mode (off mode); And
(n) If it is determined in step (m) that the mode is not the S4 mode or the S5 mode, the process returns to step (j) after a predetermined period of time to check whether wake- If it is determined that the S4 mode or the S5 mode has occurred, the SIO 19 stops supplying all the operation power (3V, 5V, 12V, etc.) to various devices on the main board through the ATX power connector 21 (S25);
Further comprising the steps of: determining a standby power of the computer system; 6. The method according to claim 4 or 5, wherein after the step (c)
(d) It is checked whether or not the additional application 90 has been executed (S15), and if the additional application has been executed (S16), waiting for a predetermined time for loading the program;
Further comprising:
The energy use optimization execution in the step (c) further includes at least one of "interruption of an unused interface" or "operation to lower the CPU clock" in addition to turning off a certain portion of the CPU core Wherein the standby power of the computer system is optimized.

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