CN101145075A - Veneer reposition control method - Google Patents
Veneer reposition control method Download PDFInfo
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- CN101145075A CN101145075A CNA2007101406135A CN200710140613A CN101145075A CN 101145075 A CN101145075 A CN 101145075A CN A2007101406135 A CNA2007101406135 A CN A2007101406135A CN 200710140613 A CN200710140613 A CN 200710140613A CN 101145075 A CN101145075 A CN 101145075A
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Abstract
The present invention discloses a veneer-reset control method, and involves the following steps: S202, the control signal of the veneer running state can be supplied to a programmable logic chip of the system in the programmable logic chip the veneer is positioned; S204, the signal of the watchdog chip of the system in programmable logic chip the veneer is positioned, and thereby is output by the programmable logic chip, can be controlled by controlling the state of the control signal of the veneer running state, so as to control the veneer reset. The present invention can solve complex process that a veneer needs to be replaced when in debugging state, and the present invention can solve the defect that the codes of the testing veneer, and the finished veneer is different from the programmable logic code.
Description
Technical field
The present invention relates to the CPU (central processing unit) application, relate more specifically to a kind of veneer reposition control method.
Background technology
The patent No. is that the patent of CN03131634 has been described a kind of device technique that the watchdog chip watchdog function is chosen of controlling, though this technology can be consistent debugging veneer and finished product single plate hardware, the shortcoming of this technology is that the FPGA (Field Programmable Gate Array) code of debugging veneer and finished product veneer can not be consistent.
At veneer CPU (central processing unit) (Center Processing Unit, abbreviation CPU) in the application, the CPU minimum system generally is made of guiding (BOOT) chip, flash memory (FLASH) chip, random-access memory (ram) chip, programmable logic chip and board resetting circuit.Wherein, the FLASH chip is used to load application program; RAM chip construction system internal memory is used to run application and preserve data; Programmable logic chip is used to finish the spuious logic of minimum system.Program in the BOOT chip runs on debugging mode (being used for debugging software) and other states according to the state of the running state of single plate control signal that is connected to I/O (I/O) pin of CPU (Switch is called for short SW) by BOOT.
Reset circuit in the veneer CPU application mainly is made of programmable logic chip and watchdog chip, and the board resetting scheme as shown in Figure 1.Wherein, the watchdog chip circuit is used for the watchdog routine operation, program must allow house dog import (WatchDog Input at the appointed time, be called for short WDI) saltus step, be that WDI is changed to high level to low level or by low level by high level, otherwise house dog output (WatchDog Output, be called for short WDO) the meeting output low level, the low output of WDO is then because the logic function of programmable logic chip can make house dog hand-reset input (Manual Reset, abbreviation MR) signal becomes low level, and this makes that watchdog reset output (Reset Output is called for short RESET) is low level, thereby make cpu reset, finally cause monoboard programme to rerun.
When BOOT program run during in debugging mode, owing to need the single step executive routine during debugging utility, can cause house dog input (WDI) not have saltus step for a long time, finally cause cpu reset, debugging work can't be carried out, so when BOOT runs on debugging mode, need forbid watchdog function, promptly during in debugging mode, not have saltus step for a long time and also can not cause cpu reset even must guarantee house dog input (WDI) in the BOOT program run.
For the method for forbidding watchdog function, traditional way is that the house dog output pin (WDO) of watchdog chip is provoked, do not allow the resetting of house dog output (WDO) control CPU, when hardware is issued, again the house dog output pin (WDO) of watchdog chip is welded again.This way makes debugging veneer and finished product single plate hardware inconsistent on the one hand, and welding is also cumbersome again on the other hand.Though the patent No. is the patented technology of CN03131634 debugging veneer and finished product single plate hardware can be consistent, the shortcoming of this technology is that the FPGA (Field Programmable Gate Array) code of debugging veneer and finished product veneer can not be consistent.
Summary of the invention
One or more problems in view of the above the invention provides a kind of veneer reposition control method.
Basic thought of the present invention is, also be connected to the running state of single plate control signal (SW) that is connected to the I/O pin of CPU in the programmable logic chip, whether the logical code of programmable logic chip is controlled house dog output (WDO) according to the state of running state of single plate control signal (SW) can directly influence house dog hand-reset input (MR), thereby whether the remote effect watchdog reset is exported (RESET) in control house dog output (WDO).
Wherein, the signal (OTHER) that house dog output, house dog hand-reset input, running state of single plate control signal (toggle switch signal) and other control that is used for CPU reset all is connected to programmable logic chip.Logic function design by programmable logic chip when being implemented in the running state of single plate control signal and being in debugging mode, is forbidden the influence of house dog output to house dog hand-reset input.
Adopt the present invention, can solve veneer needs to weld again veneer under debugging mode loaded down with trivial details process and debugging veneer and finished product single plate hardware and the inconsistent defective of FPGA (Field Programmable Gate Array) code.
Description of drawings
Accompanying drawing described herein is used to provide further understanding of the present invention, constitutes the application's a part, and illustrative examples of the present invention and explanation thereof are used to explain the present invention, do not constitute improper qualification of the present invention.In the accompanying drawings:
Fig. 1 is the main flow scheme synoptic diagram of existing realization board resetting;
Fig. 2 is the process flow diagram according to the veneer reposition control method of the embodiment of the invention;
Fig. 3 is the scheme synoptic diagram of board resetting method according to another embodiment of the present invention.
Embodiment
Below with reference to accompanying drawing, describe the specific embodiment of the present invention in detail.
With reference to figure 2, the veneer reposition control method according to the embodiment of the invention is described.As shown in Figure 2, this veneer reposition control method may further comprise the steps: S202 offers the running state of single plate control signal programmable logic chip of veneer place system; S204 by the state of control running state of single plate control signal, controls the signal that programmable logic chip exports the watchdog chip of veneer place system to, with resetting of control veneer.
Wherein, the house dog hand-reset input end of watchdog chip is connected to programmable logic chip.In step S204, the signal that exports the house dog hand-reset input end of watchdog chip to by the control programmable logic chip is controlled the signal of the house dog output terminal of watchdog chip, with resetting of control veneer.
Wherein, the house dog output terminal of watchdog chip is connected to programmable logic chip.Other reset signals that are used to control board resetting all are connected to programmable logic chip.The running state of single plate control signal can be toggle switch signal or wire jumper signal.And this toggle switch signal or wire jumper signal can be toggle switch signal or the wire jumper signals more than 1.
With reference to figure 3, board resetting method according to another embodiment of the present invention is described.In method shown in Figure 3, the running state of single plate control signal adopts 4 toggle switch signal SW[3:0].Wherein, when these 4 toggle switch signals were 1 entirely, the expression veneer was in debugging mode.
Wherein, house dog can be exported (WDO) and be connected to programmable logic chip, house dog hand-reset input (MR) is connected to programmable logic chip, and the toggle switch signal is connected to programmable logic chip.The signal (OTHER) that wherein, also other control can be resetted is connected to programmable logic chip.
Logic function design by programmable logic chip when can be implemented in the toggle switch signal and being in debugging mode, is forbidden house dog output (WDO) influence to house dog hand-reset input (MR).Wherein, can realize above-mentioned functions by following VERILOG language:
assign?MR1＝OTHER
assign?MR2＝WDO&OTHER
assign?MR＝(sw＝＝4’hF)？MR1：MR2；
From above two embodiment as can be seen, the present invention can guarantee that watchdog function is under an embargo automatically when BOOT runs on debugging mode, thereby removed the trouble of welding again from, but also guaranteed the consistance of debugging veneer and finished product single plate hardware and FPGA (Field Programmable Gate Array) code.
The above is embodiments of the invention only, is not limited to the present invention, and for a person skilled in the art, the present invention can have various changes and variation.Within the spirit and principles in the present invention all, any modification of being done, be equal to replacement, improvement etc., all should be included within the claim scope of the present invention.
Claims (7)
1. a veneer reposition control method is characterized in that, may further comprise the steps:
S202 offers the running state of single plate control signal programmable logic chip of described veneer place system;
S204 controls the signal that described programmable logic chip exports the watchdog chip of described veneer place system to by the state of controlling described running state of single plate control signal, to control resetting of described veneer.
2. veneer reposition control method according to claim 1 is characterized in that, the house dog hand-reset input end of described watchdog chip is connected to described programmable logic chip.
3. veneer reposition control method according to claim 2, it is characterized in that, in described step S204, control the signal of the house dog output terminal of described watchdog chip by controlling signal that described programmable logic chip exports the house dog hand-reset input end of described watchdog chip to, to control resetting of described veneer.
4. veneer reposition control method according to claim 3 is characterized in that, the house dog output terminal of described watchdog chip is connected to described programmable logic chip.
5. veneer reposition control method according to claim 4 is characterized in that, other reset signals that are used to control described board resetting all are connected to described programmable logic chip.
6. veneer reposition control method according to claim 5 is characterized in that, described running state of single plate control signal is toggle switch signal or wire jumper signal.
7. veneer reposition control method according to claim 6 is characterized in that, described toggle switch signal is the toggle switch signal more than 1 or 1, and described wire jumper signal is the wire jumper signal more than 1 or 1.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNA2007101406135A CN101145075A (en) | 2007-08-09 | 2007-08-09 | Veneer reposition control method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNA2007101406135A CN101145075A (en) | 2007-08-09 | 2007-08-09 | Veneer reposition control method |
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| CN101145075A true CN101145075A (en) | 2008-03-19 |
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| CNA2007101406135A Pending CN101145075A (en) | 2007-08-09 | 2007-08-09 | Veneer reposition control method |
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Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102063081A (en) * | 2010-11-04 | 2011-05-18 | 天津曙光计算机产业有限公司 | Design method for realizing power on and off and time sequence resetting of Loongson mainboard by utilizing state machine |
| CN102270028A (en) * | 2011-07-21 | 2011-12-07 | 曙光信息产业股份有限公司 | Automatic Loongson mainboard resetting device based on field programmable gate array (FPGA) |
| CN102854962A (en) * | 2012-08-23 | 2013-01-02 | 哈尔滨工业大学 | MPC8280 minimum system applying CPLD (complex programmable logic device) and state switching method for setting hard reset configuration words |
| CN103248507A (en) * | 2012-02-08 | 2013-08-14 | 中兴通讯股份有限公司 | Single-board power-down device and method |
| CN103677904A (en) * | 2013-12-01 | 2014-03-26 | 国家电网公司 | Switching method and control circuit for controlling CPU (central processing unit) to enter different states in time of start |
-
2007
- 2007-08-09 CN CNA2007101406135A patent/CN101145075A/en active Pending
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102063081A (en) * | 2010-11-04 | 2011-05-18 | 天津曙光计算机产业有限公司 | Design method for realizing power on and off and time sequence resetting of Loongson mainboard by utilizing state machine |
| CN102063081B (en) * | 2010-11-04 | 2013-08-28 | 曙光信息产业股份有限公司 | Design method for realizing power on and off and time sequence resetting of Loongson mainboard by utilizing state machine |
| CN102270028A (en) * | 2011-07-21 | 2011-12-07 | 曙光信息产业股份有限公司 | Automatic Loongson mainboard resetting device based on field programmable gate array (FPGA) |
| CN103248507A (en) * | 2012-02-08 | 2013-08-14 | 中兴通讯股份有限公司 | Single-board power-down device and method |
| CN102854962A (en) * | 2012-08-23 | 2013-01-02 | 哈尔滨工业大学 | MPC8280 minimum system applying CPLD (complex programmable logic device) and state switching method for setting hard reset configuration words |
| CN102854962B (en) * | 2012-08-23 | 2015-05-13 | 哈尔滨工业大学 | MPC8280 minimum system applying CPLD (complex programmable logic device) and state switching method for setting hard reset configuration words |
| CN103677904A (en) * | 2013-12-01 | 2014-03-26 | 国家电网公司 | Switching method and control circuit for controlling CPU (central processing unit) to enter different states in time of start |
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Open date: 20080319 |