TWI564722B - Black plane and method for detecting serial general purpose input/output signal thereof - Google Patents

Description

Hard disk backplane and its serial detection method for detecting common input and output signals

The present invention relates to a method for detecting a hard disk backplane and its serial general-purpose input and output signals, and more particularly to a hard disk backplane capable of determining the frame capacity of a series of general-purpose input and output signals transmitted by a start end and Serial detection of general-purpose input and output signals.

In the computer field, the server can use a Serial General Purpose Input/Output Bus (SGPIO bus) to communicate between the Motherboard and the Blackplane. Generally, a SGPIO cable can be connected between the motherboard and the hard disk backplane, and the motherboard transmits the SGPIO signal to the hard disk backplane through the SGPIO cable, and then the hard disk backplane decodes the SGPIO signal to control multiple A pointing component (such as a Light-Emitting Diode, LED for short) is used to indicate the state of the hard disk. For example, each hard disk corresponds to three light-emitting diodes, and the light-emitting diodes respectively indicate information such as an activity, a locate, and an error of the hard disk.

Further, a hard disk control component (such as a host bus adapter (HBA) card or a Redundant Array of Independent Disks (RAID) card) may be inserted into the motherboard. Or a platform controller (PCH), etc., the hard disk control component is configured to transmit a SGPIO signal conforming to the SFF-8485 specification to a hard disk backplane. The hard disk control element can be regarded as an initiator, and the hard disk backplane can be regarded as a target. It is worth noting that the number of hard disks supported by different hard disk control components is different, so the frame size of SGPIO signals transmitted by different hard disk control components is also different.

Therefore, when the user wants to replace the existing hard disk control component on the motherboard, if the hard disk control component to be set is different from the frame capacity of the SGPIO signal provided by the existing hard disk control component, the user must The manual jumper (Jump) is used to switch the SGPIO signal on the hard disk backplane, so that the hard disk backplane knows the frame capacity of the SGPIO signal to correctly decode the SGPIO signal. Otherwise, the hard disk backplane will not be able to control the indicator component to display the hard disk status. However, the method of the jumper is simple and low-cost, but it wastes General Purpose Input/Output (GPIO) resources, and when multiple hard disk control components of multiple motherboards need to be replaced at the same time. , it is easy to cause human error, causing the hard disk backplane to not correctly decode the SGPIO signal.

On the other hand, in addition to the above-mentioned jumper mode, the internal integrated circuit bus (integrated circuit) can be used after the server is powered on, and the related information is collected by the Basic Input/Output System (BIOS). Bus, referred to as I ₂ C-bus), achieves data transfer between the motherboard and the hard disk backplane, but this method not only wastes GPIO resources, but also increases firmware development time and hardware implementation cost.

The present invention provides a method for detecting a hard disk backplane and a serial general-purpose input/output signal thereof, wherein the hard disk backplane can identify a string transmitted by the motherboard by performing the method of detecting the serial general-purpose input and output signals. Column frame input and output signal frame capacity.

An embodiment of the present invention provides a method for detecting a serial input/output signal. The method for detecting a serial general-purpose input/output signal includes obtaining a serial general-purpose input and output signal from a motherboard, wherein the serial input/output signal is serially connected. Including a load signal and a clock signal, and based on the load signal and the pulse signal, the initial value is zero. a first count value is accumulated, and when the first count value is greater than a first preset value, the first count value is captured at a time according to the voltage level state of the load signal, and according to the intercepted A count value is used to determine the frame capacity of the serial input/output signals.

Embodiments of the present invention provide a hard disk backplane, including a communication interface and a processing module. The communication interface is coupled to a start end to receive a serial input and output signal. The processing module is coupled to the communication interface to receive the serial general-purpose input and output signals, and the processing module can perform the detection method of the serial general-purpose input and output signals as claimed in claim 1 to determine the serial input/output signals. Frame capacity.

In summary, the method for detecting a hard disk backplane and its serial general-purpose input and output signals according to the embodiments of the present invention can determine the string according to the load signal and the pulse signal in the serial general-purpose input and output signals. The frame input capacity of the general-purpose input/output signal, whereby the hard disk backplane can effectively decode the serial general-purpose input and output signals transmitted from the start end, and display the hard disk state corresponding to the control indicating component.

The detailed description of the present invention and the accompanying drawings are to be understood by the claims The scope is subject to any restrictions.

1‧‧‧hard disk system

11‧‧‧ motherboard

12‧‧‧ Hard disk backplane

13‧‧‧SGPIO cable

14‧‧‧Indicating components

111, 121‧‧‧ communication interface

122‧‧‧Processing module

1221‧‧‧Detection circuit

1222‧‧‧Control circuit

Sclock‧‧‧ clock signal

Sload‧‧‧Load signal

Count‧‧‧first count value

Start‧‧‧second count value

Sdataout‧‧‧ data output signal

Sdatain‧‧‧ data input signal

S111, S113, S115, S117, S119‧‧ steps

1 is a block diagram showing the architecture of a hard disk system according to an embodiment of the present invention.

2 is a timing diagram of signal waveforms of a hardware backplane in accordance with an embodiment of the present invention.

3 is a timing diagram of signal waveforms of a hardware backplane according to another embodiment of the present invention.

4 is a flow chart of a method for detecting a serial general-purpose input and output signal according to an embodiment of the invention.

Various illustrative embodiments are described more fully hereinafter with reference to the accompanying drawings. However, the concept of the present invention may be The invention is in many different forms and should not be construed as being limited to the illustrative embodiments set forth herein. Rather, these exemplary embodiments are provided so that this invention will be in the In the drawings, the size and relative sizes of layers and regions may be exaggerated for clarity. Similar numbers always indicate similar components.

It will be understood that, although the terms first, second, third, etc. may be used herein to describe various elements, such elements are not limited by the terms. These terms are used to distinguish one element from another. Thus, a first element discussed below could be termed a second element without departing from the teachings of the inventive concept. As used herein, the term "and/or" includes any of the associated listed items and all combinations of one or more.

[Embodiment of a method for detecting a hard disk backplane and its serial general-purpose input and output signals]

Please refer to FIG. 1. FIG. 1 is a schematic structural diagram of a hard disk system according to an embodiment of the present invention. The hard disk system 1 includes a motherboard 11, a hard disk backplane 12, and a plurality of indicating components 14 (not shown). The motherboard 11 is coupled to the hard disk backplane 12 via a SGPIO cable 13, and the hard disk backplane 12 is coupled to a plurality of indicator elements 14, wherein the plurality of indicator elements 14 can be LED lights or other light-emitting elements having an indicating function.

The motherboard 11 includes a communication interface 111 and a hard disk control component (not shown), and the communication interface 111 is coupled to the hard disk control component. The communication interface 111 can be a SGPIO bus slot, and the hard disk control component can be an HBA card, a RAID card, a PCH, or other expander or interface card that supports SGPIO communication. The hard disk control component can be regarded as a start end, and can be selectively inserted on the motherboard 11, whereby the motherboard 11 can transmit the SGPIO signal conforming to the SFF-8485 specification to the hard disk through the hard disk control component. Backboard 12.

The hard disk backplane 12 can be regarded as a target end, which is, for example, a hard disk drive (HDD), which includes a communication interface 121 and a processing module 122, and the communication interface 121 is coupled to the processing module 122. The communication interface 121 can be a SGPIO bus slot for receiving the SGPIO signal through the SGPIO cable 13. The processing module 122 can be a Complex Programmable Logic Device (referred to as Complex Programmable Logic Device, referred to as CPLD), Field Programmable Gate Array (FPGA) or other microcontroller (Microcontroller, MCU for short) with appropriate firmware. The processing module 122 controls whether the plurality of indicator elements 14 emit light according to the SGPIO signal transmitted by the motherboard 11.

In this embodiment, the motherboard 11 can generate a SGPIO signal conforming to the specification of the SFF-8485 specification, and the SGPIO signal includes a time pulse signal sclock, a load signal sload, and a data output signal with hard disk status information. Sdataout. The processing module 122 receives the SGPIO signal through the SGPIO cable 13, and determines the frame capacity of the SGPIO signal according to the clock signal sclock and the load signal sload in the SGPIO signal. Then, the processing module 122 decodes the data output signal sdataout according to the frame capacity to control the plurality of indicator elements 14 to emit light, and correspondingly generates the data input signal sdatain to the motherboard 11.

In detail, the SGPIO communication between the start end and the target end in the hard disk system is in compliance with the SGPIO protocol (that is, the specification of the SFF-8485 specification), and therefore, during a period in which a hard disk system is reset (reset), The start end converts the clock signal sclock and the load signal sload to a high voltage level (ie, the logic state is 1). When the initiator wants to transmit the SGPIO signal to the target end, the load signal sload in the SGPIO signal provided at the start end is converted to the low voltage level state (ie, the logic state is changed from 1 to 0), and then the target end is It will start to latch the data of each bit according to each falling edge of the clock signal sclock. In addition, after the load signal sload is first changed from the high voltage level to the low voltage level, during the transmission period of the first four bits of data, the load signal sload may be a vendor-specific pattern.

Here, the present invention utilizes the specification features of the SFF-8485 specification to provide a method for detecting serial serial input and output signals capable of determining the frame capacity of the SGPIO signal, and applying the method to the hard disk backplane 12 The hard disk backplane 12 can determine the frame capacity of the received SGPIO signal to correctly decode the SGPIO signal, and accordingly control the plurality of indicator elements 14 to emit light.

In more detail, in this embodiment, the processing module 122 includes a detection circuit 1221. And the control circuit 1222, and the detection circuit 1221 is coupled to the control circuit 1222. The detecting circuit 1221 can accumulate a count value whose initial value is zero according to the clock signal sclock and the load signal sload. When the count value is greater than a predetermined value, the detecting circuit 1221 captures the count value at a time according to the voltage level state of the load signal sload. Next, the detecting circuit 1221 determines the frame capacity of the SGPIO signal according to the intercepted count value, and accordingly generates a frame capacity indication signal F. The control circuit 1222 can decode the received SGPIO signal according to the frame capacity indication signal F to control whether the plurality of indicator elements 14 emit light.

In order to explain in more detail the working principle of the method for detecting a hard disk backplane and its serial general-purpose input and output signals according to the present invention, at least one of the following embodiments will be further described. Please refer to FIG. 1 , FIG. 2 and FIG. 3 simultaneously. FIG. 2 is a timing diagram of signal waveforms of a hardware backplane according to an embodiment of the invention. 3 is a timing diagram of signal waveforms of a hardware backplane according to another embodiment of the present invention. It should be noted that the clock signal sclock and the load signal sload shown in FIG. 2 and FIG. 3 are respectively provided by hardware control elements supporting 4 and 7 hard disks. In this embodiment, when the detecting circuit 1221 detects that the loading signal sload changes from the high voltage level to the low voltage level, the detecting circuit 1221 starts detecting the falling edge number of the clock signal sclock, so as to The first count value count whose initial value is 0 is accumulated, and the detecting circuit 1221 adds 1 to the second count value start whose initial value is 0. Next, when the first count value count is greater than 4 (ie, the preset value), if the detecting circuit 1221 detects that the load signal sload is again changed from the high voltage level to the low voltage level, the detecting circuit 1221 will again increment the second count value start by one. Next, when the second count value start is 2, the detecting circuit 1221 stops accumulating the first count value count, and determines the frame capacity of the SGPIO signal according to the current first count value count. The signal sources of the first count value count and the second count value start are all generated by the detecting circuit 1221 in the hard disk backboard 12.

In other words, if the hardware control component of the motherboard 11 supports 4 hard disks, when the first count value count is greater than 4 and the load signal sload is changed from the high voltage level to the low voltage. When the level is in position, the detecting circuit 1221 retrieves the first count value count of the value 12 to inform the control circuit 1222 that the frame capacity of the SGPIO signal is 12 bits. On the other hand, if the hardware control component of the motherboard 11 supports 7 hard disks, when the first count value count is greater than 4 and the load signal sload is changed from the high voltage level to the low voltage level, the detection is performed. The circuit 1221 retrieves the first count value count of the value 21 to inform the control circuit 1222 that the frame capacity of the SGPIO signal is 21 bits. Thereby, the control circuit 1222 can generate a control signal to the plurality of indicator elements 14 to control the illumination state (eg, long light or blink) of the plurality of indicator elements 14.

It is worth mentioning that, in another implementation, when the first count value count is greater than the preset value, if the detecting circuit 1221 detects that the load signal sload is at a high voltage level, the detecting circuit 1221 will The current first count value count is retrieved, and then the captured first count value count is incremented by one, and the frame capacity of the SGPIO signal is determined accordingly. For example, in FIG. 2, when the first count value count is greater than 4 and the load signal sload is at a high voltage level, the detecting circuit 1221 captures the first count value count of the value 11, and then Add one to determine the frame size of the SGPIO signal as 12 bits. On the other hand, taking FIG. 3 as an example, when the first count value count is greater than 4 and the load signal sload is at a high voltage level, the detecting circuit 1221 captures the first count value count of the value 20, and then Add one to determine the frame size of the SGPIO signal is 21 bits. Therefore, the detecting circuit 1221 can immediately decode the SGPIO signal according to the frame capacity of the SGPIO signal before the next frame is transmitted to the hard disk backplane 12, to control the complex number. Whether the indicator element 14 emits light.

In short, when the hard disk backplane 12 obtains the SGPIO signal from the motherboard 11, the hard disk backplane 12 can generate a count value according to the clock signal sclock and the load signal sload, and when the count value is greater than a preset value. When the hard disk backplane 12 is in accordance with the voltage level state of the load signal sload, the count value is retrieved at a time, and the frame capacity of the SGPIO signal is determined accordingly.

Please refer to FIG. 4. FIG. 4 is a flowchart of a method for detecting a serial general-purpose input and output signal according to an embodiment of the present invention. The detection method can be performed on the hard shown in FIG. The disc backing plate 12, so please understand it together with FIG. 1 to FIG. 4, and the detecting method includes the following steps.

In step S111, the hard disk backplane 12 can receive the SGPIO signal conforming to the specification of the SFF-8485 specification through the motherboard 11, and then the hard disk backplane 12 can obtain a load signal sload and a clock from the SGPIO signal. Signal sclock.

In step S113, the hard disk backplane 12 determines whether the load signal sload is converted from a high voltage level to a low power level voltage. If the hard disk backplane 12 determines that the load signal sload is changed from the high voltage level to the low power level, step S115 is performed. On the other hand, if the hard disk backplane 12 determines that the load signal sload is not converted from the high voltage level to the low power level, step S113 is performed again.

In step S115, the hard disk backplane 12 starts accumulating the first count value count whose initial value is zero according to the number of falling edges of the clock signal sclock.

In step S117, when the first count value count is greater than a predetermined value, the hard disk backplane 12 determines whether the load signal sload is at a high voltage level. If the hard disk backplane 12 determines that the load signal sload is at a high voltage level, step S119 is performed. On the other hand, if the hard disk backplane 12 determines that the load signal sload is not at the high voltage level, step S117 is performed again.

In step S119, the hard disk backplane 12 captures the current first count value count and adds it to determine the frame capacity of the SGPIO signal. Thereby, the hard disk backplane 12 can correctly parse the SGPIO signal transmitted by the motherboard 11, and correspondingly control whether the plurality of indicator components 14 on the back end emit light to instantly display the state of the hard disk.

The details of the steps of the method for detecting the serial input/output signals of the hard disk backplane 12 have been described in detail in the above embodiment of FIG. 1, and will not be described herein.

It should be noted that the steps of the embodiment of FIG. 4 are only for convenience of description, and the embodiments of the present invention do not use the steps of the steps as a limitation of the embodiments of the present invention.

In addition, it should be noted that the steps of the above-described method for detecting the serial input/output signals can be implemented by at least one piece of code, and the steps correspond to At least one piece of code can be recorded in computer-readable media.

[Effects of possible examples]

In summary, the method for detecting a hard disk backplane and its serial general-purpose input and output signals according to the embodiments of the present invention can be determined according to the load signal and the pulse signal in the serial general-purpose input and output signals. The frame capacity of the serial input/output signal is serialized, so that the hard disk backplane can correctly decode the serial general-purpose input and output signals to effectively control the illumination states of the plurality of indicator components. Therefore, compared with the prior art, the method for detecting the hard disk backplane and the serial general-purpose input and output signals thereof of the present invention does not increase the hardware cost, and can avoid the loss and waste of general-purpose input and output. Resources.

The above description is only the preferred embodiment of the present invention, but the features of the present invention are not limited thereto, and any one skilled in the art can easily change or modify it in the field of the present invention. It is covered by the scope of the invention.

S111, S113, S115, S117, S119‧‧ steps

Claims (10)

A method for detecting a serial input/output signal includes: obtaining a serial input/output signal, wherein the serial input/output signal comprises a load signal and a clock signal; and according to the load signal and the clock a signal, accumulating a first count value whose initial value is zero; and when the first count value is greater than a first preset value, according to the voltage level state of the load signal, capturing the first time a count value, and determining a frame capacity of the serial general-purpose input and output signals according to the intercepted first count value. The method for detecting a serial general-purpose input/output signal according to claim 1 further includes: when the load signal is changed from a high voltage level to a low power level for the first time, according to the decline of the clock signal The number of edges starts to accumulate the first count value whose initial value is zero. The method for detecting a serial general-purpose input/output signal according to claim 1, further comprising: when the first count value is greater than a first preset value and the load signal is at a high voltage level, capturing the current The first count value is incremented by the intercepted first count value to determine the frame capacity of the serial general-purpose input and output signal. The method for detecting a serial general-purpose input/output signal according to claim 1, further comprising: when the first count value is greater than a first preset value and the load signal is changed from a high voltage level to a low voltage level The current first count value is retrieved to determine the frame capacity of the serial general-purpose input and output signals. The method for detecting a serial general-purpose input/output signal according to claim 1 further includes: When the first count value is greater than a first preset value and the load signal is changed from a high voltage level to a low voltage level, stopping accumulating the first count value, and according to stopping the accumulated first The value is counted to determine the frame capacity of the serial general-purpose input and output signals. The method for detecting a serial general-purpose input/output signal according to claim 1 further includes: when the load signal is changed from a high voltage level to a low power level for the first time, the initial value is zero. The second count value is incremented by one; when the first count value is greater than a first preset value and the load signal is changed from the high voltage level to the low voltage level, the second count value is incremented by one again; When the second count value is equal to two, the first count value is stopped to be accumulated, and the frame count capacity of the serial general-purpose input and output signal is determined according to the stop of the accumulated first count value. A hard disk backplane includes: a communication interface coupled to a start end for receiving a serial input/output signal; and a processing module coupled to the communication interface to receive the serial general input and output signal, and The method for detecting the serial general-purpose input and output signals as claimed in claim 1 is performed to determine the frame capacity of the serial general-purpose input and output signals. The hard disk backplane of claim 7, wherein the processing module comprises: a detecting circuit for detecting a state of the loading signal and the first count value, so that the loading signal is firstly applied by a high voltage When the level is changed to the low level voltage, the first count value is generated according to the number of falling edges of the clock signal. The hard disk backplane of claim 8, wherein the detecting circuit is converted from a high voltage level to a first value after the first count value is greater than a first preset value When the voltage is low, the detection circuit generates a frame capacity indication signal according to the current first count value, or when the load signal is at a high voltage level, the detection circuit captures the current The first count value is incremented, and the intercepted first count value is incremented by one to generate the frame capacity indication signal. The hard disk backplane of claim 9, wherein the processing module comprises: a control circuit coupled to the detecting circuit and at least one indicating component, the control circuit decoding the serial according to the frame capacity indicating signal A general purpose input and output signal to control the at least one indicator component.