CN108388481B - Intelligent watchdog circuit system of OLT equipment - Google Patents
Intelligent watchdog circuit system of OLT equipment Download PDFInfo
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- CN108388481B CN108388481B CN201810186882.3A CN201810186882A CN108388481B CN 108388481 B CN108388481 B CN 108388481B CN 201810186882 A CN201810186882 A CN 201810186882A CN 108388481 B CN108388481 B CN 108388481B
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
- G06F11/0751—Error or fault detection not based on redundancy
- G06F11/0754—Error or fault detection not based on redundancy by exceeding limits
- G06F11/0757—Error or fault detection not based on redundancy by exceeding limits by exceeding a time limit, i.e. time-out, e.g. watchdogs
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Abstract
The embodiment of the invention discloses an intelligent watchdog circuit system of OLT equipment, comprising: the CPU circuit, the CPLD circuit and the reset circuit; the CPU circuit is connected with the CPLD circuit through a serial interface line; the reset circuit is connected to the CPLD circuit; the CPLD circuit realizes the watchdog function and the reset function; the CPU circuit adjusts the reset time and the reset time sequence of the reset circuit through the CPLD circuit, and when the CPU circuit is abnormal, the watchdog circuit of the CPLD circuit realizes the reset of the whole board, thereby ensuring the system to operate again. The invention is connected to the CPU circuit through a serial interface, determines whether to reset or not and whether to trigger the watchdog or not by analyzing the instruction sent by the CPU circuit, and realizes the accurate control of time by counting the external clock.
Description
Technical Field
The invention relates to the technical field of watchdog circuits, in particular to an intelligent watchdog circuit system of OLT equipment.
Background
Currently, the watchdog used in the electronic device is divided into a hardware watchdog and a software watchdog. A special watchdog chip is adopted, and a CPU controls a watchdog feeding signal and a watchdog enabling signal to control the watchdog chip, and the mode is called as a hardware watchdog; a watchdog circuit integrated inside the CPU is used, which is called a software watchdog. The software watchdog is influenced by the CPU, so that a plurality of devices with higher requirements on the watchdog do not adopt the mode.
The hardware watchdog generally adopts a 706 chip, a 6 th pin of the 706 chip is a dog feeding signal input, when no dog feeding is performed in 1.6S, an 8 th pin is triggered to be changed into a low level, because the 1 st pin is connected with the 8 th pin, and when the 1 st pin detects that the low level exists, the 7 th pin is reset, so that a watchdog resetting process is completed. When the equipment is powered on, the 706 chip outputs a reset signal 1.6S after being powered on, so that the equipment can be effectively reset after being powered on.
706 chip this way has high reliability but is limited by industry universal rule constraints, the reset is triggered after 1.6S without dog feeding, and the reset has only one 7 th pin. This cannot be met when the time required to change 1.6S and the chip to be reset has special timing requirements. Because the dog feeding signal is provided by the CPU, at least 1.6S of the dog feeding signal needs to be provided once, and the CPU resource is occupied when the CPU process is tense. The OLT project uses too few GPIO resources of the CPU, and the GPIO can not guarantee that the action of level conversion is made within 1.6S in the upgrading process, because the OLT device is complicated, and the reset time sequence required by peripheral IC devices is different, the traditional 706 can not completely meet the reset and watchdog functions of the OLT device. Because the OLT device originally uses the CPLD, the realization of the watchdog and reset functions by the CPLD can solve the problem which cannot be solved by the traditional 706 chip and can save the cost.
Accordingly, there is a need in the art for improvements.
Disclosure of Invention
The embodiment of the invention aims to solve the technical problem that: the utility model provides an intelligent watchdog circuit system of OLT equipment to solve the problem that prior art exists, intelligent watchdog circuit system of OLT equipment includes:
the CPU circuit, the CPLD circuit and the reset circuit;
the CPU circuit is connected with the CPLD circuit through a serial interface line, and the serial interface line comprises a clock line and a data line;
the reset circuit is connected to the CPLD circuit;
the CPU circuit and the CPLD circuit self-define the work thereof;
the CPLD circuit realizes the watchdog function and the reset function;
the CPU circuit adjusts the reset time and the reset time sequence of the reset circuit through the CPLD circuit, and when the CPU circuit is abnormal, the watchdog circuit of the CPLD circuit realizes the reset of the whole board, thereby ensuring the system to operate again.
In another embodiment of the intelligent watchdog circuit system based on the OLT device of the present invention, the CPLD circuit includes: the device comprises a serial port module, a judgment module, a clock module, a self-reset module, an external reset module and a watchdog module;
the serial port module is connected with the CPU circuit and used for detecting data sent by a serial port, judging information sent behind an instruction code as effective information when the serial port module detects the instruction code sent by the data, and sending the information to the external reset module and the watchdog module;
the judging module is connected with the serial port module and the watchdog module, judges whether the CPU circuit works according to whether the serial port module changes, judges the fault of the CPU circuit if the clock level of the serial port module does not change within a set time threshold value, and sends the judging result to the watchdog module;
the self-reset module is used for controlling the self-reset function of the CPLD circuit to be realized;
the clock module is used for detecting an external clock, realizing a plurality of counters inside, facilitating time sequence control and time control, and sending clock signals to the serial port module, the judgment module, the self-reset module, the external reset module and the watchdog module;
the external reset module is used for controlling the reset of external equipment to reset the external equipment according to any sequence and any time;
the watchdog module is connected with the serial port module and the judging module, determines whether to trigger the function of the watchdog module according to the result obtained by the judging module, and receives the data sent by the serial port module when the serial port module has data sending.
In another embodiment of the intelligent watchdog circuit system based on the OLT device of the present invention, the instruction code for data transmission is: 10100101, when the serial module receives the instruction code, it determines that the information sent after the instruction code is valid information.
In another embodiment of the intelligent watchdog circuit system based on the OLT apparatus of the present invention, the time threshold is 10 minutes.
In another embodiment of the intelligent watchdog circuit system based on the OLT device of the present invention, the clock module is externally connected to a clock circuit with a frequency of 2.048M, and the clock module obtains an arbitrary time of 0.5us multiple greater than 0.5us through the external clock circuit.
Compared with the prior art, the invention has the following advantages:
the invention provides a novel intelligent watchdog circuit system of OLT equipment, which is connected to a CPU circuit through a serial interface, determines whether to reset or not and whether to trigger a watchdog or not by analyzing an instruction sent by the CPU circuit, and realizes accurate time control by counting an external clock.
The technical solution of the present invention is further described in detail by the accompanying drawings and embodiments.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description, serve to explain the principles of the invention.
The invention will be more clearly understood from the following detailed description, taken with reference to the accompanying drawings, in which:
fig. 1 is a schematic structural diagram of an embodiment of an intelligent watchdog circuit system of an OLT apparatus according to the present invention.
In the figure: the device comprises a 1CPU circuit, a 2CPLD circuit, a 21 serial port module, a 22 judgment module, a 23 clock module, a 24 self-reset module, a 25 external reset module, a 26 watchdog module and a 3 reset circuit.
Detailed Description
Various exemplary embodiments of the present invention will now be described in detail with reference to the accompanying drawings. It should be noted that: the relative arrangement of the components and steps, the numerical expressions and numerical values set forth in these embodiments do not limit the scope of the present invention unless specifically stated otherwise.
Meanwhile, it should be understood that the sizes of the respective portions shown in the drawings are not drawn in an actual proportional relationship for the convenience of description.
The following description of at least one exemplary embodiment is merely illustrative in nature and is in no way intended to limit the invention, its application, or uses.
Techniques, methods, and apparatus known to those of ordinary skill in the relevant art may not be discussed in detail but are intended to be part of the specification where appropriate.
Fig. 1 is a schematic structural diagram of an embodiment of an intelligent watchdog circuit system of an OLT device according to the present invention, and as shown in fig. 1, the intelligent watchdog circuit system of the OLT device includes:
a CPU circuit 1, a CPLD circuit 2 and a reset circuit 3;
the CPU circuit 1 is connected with the CPLD circuit 2 through a serial interface line, and the serial interface line comprises a clock line and a data line;
the reset circuit 3 is connected to the CPLD circuit 2;
the CPU circuit 1 and the CPLD circuit 2 self-define the work thereof;
the CPLD circuit 2 realizes a watchdog function and a reset function;
the CPU circuit 1 adjusts the reset time of the reset circuit through the CPLD circuit 2, when the CPU circuit 1 is abnormal, the watchdog circuit of the CPLD circuit 2 realizes the reset of the whole board, and the system is ensured to operate again.
The reset circuit 3 comprises a plurality of reset control interfaces, and the reset circuit 3 receives reset information under the control of the CPLD circuit 2.
The CPLD circuit 2 includes: the device comprises a serial port module 21, a judgment module 22, a clock module 23, a self-reset module 24, an external reset module 25 and a watchdog module 26;
the serial port module 21 is connected to the CPU circuit 1, and is configured to detect data sent by a serial port, and when the serial port module 21 detects a command code sent by the data, determine that information sent behind the command code is valid information, and send the information to the external reset module 25 and the watchdog module 26;
the judging module 22 is connected with the serial port module 21 and the watchdog module 26, judges whether the CPU circuit 1 is working according to whether there is a change in the serial port module 21, judges that the CPU circuit 1 is faulty if the clock level of the serial port module 21 does not change within a set time threshold, and sends the judgment result to the watchdog module 26;
the self-reset module 24 is used for controlling the realization of the self-reset function of the CPLD circuit 2;
the clock module 23 is configured to detect an external clock, implement a plurality of counters inside, facilitate timing control and time control, and send clock signals to the serial port module 21, the determination module 22, the self-reset module 24, the external reset module 25, and the watchdog module 26;
the external reset module 25 is used for controlling the reset of the external device, so that the external device is reset according to any sequence and any time;
the watchdog module 26 is connected with the serial port module 21 and the judgment module 22, determines whether to trigger the function of the watchdog module 26 according to the result obtained by the judgment module 22, and receives the data sent by the serial port module 21 when the serial port module 21 has data to send.
The instruction code for sending the data is as follows: 10100101, when the serial module 21 receives the instruction code, it determines that the information sent after the instruction code is valid information.
The time threshold is 10 minutes.
The clock module 23 is externally connected with a clock circuit with the frequency of 2.048M, and the clock module 23 obtains time which is larger than 0.5us and is multiplied by any 0.5us through the external clock circuit.
The working process of the intelligent watchdog circuit system of the OLT equipment is as follows:
and (3) electrifying:
the power-on time of the system is 3 minutes, and the maximum upgrade time is 5 minutes, so the watchdog module 26 determines the set time for resetting to be 10 minutes. After the device is powered on, the serial port module 21 does not work, the judgment module 22 starts to work, and because the start is completed in 3 minutes, the CPU circuit 1 sends some management data through the clock line of the serial interface line at variable times after the start is completed, so that the watchdog module 26 is not triggered to reset, and the system can be started normally. The input pin of the self-reset module 24 is externally connected with RC reset, the output is high resistance when the power is on, the external reset module 25 is started to be executed after the input is reset through the RC, other modules of the equipment are reset, after the system is started, the CPLD circuit 2 is controlled by the CPU circuit 1 through a self-defined serial port, the output of the self-reset module 24 is changed into the control of the CPLD circuit 2, the high resistance is changed into the output, a clock line of a serial interface line accesses the CPLD circuit 2 irregularly, and the system is ensured not to be restarted.
Abnormal operation
When the CPU circuit 1 operates abnormally, the clock line of the serial interface line connected with the CPU circuit 1 and the CPLD circuit 2 does not send data any more, when the judging module 22 detects that the serial clock keeps 0 or 1 for more than 10 minutes, the watchdog module 26 is triggered, the CPLD circuit 2 considers that the system is abnormal, the output low level of the self-reset module 24 keeps 200ms and then is pulled high, the input of the self-reset module 24 detects that the low level exists, then the CPLD circuit 2 resets and executes external reset again, and the system can be ensured to be started normally again
Upgrade restart
During the use of the system, due to version updating or firmware upgrading, unscheduled upgrading is needed, and the system generally needs to be restarted after the upgrading is completed. The CPU circuit 1 sends a command to the CPLD circuit 2 through the serial port module 21, maintains the output low level from the reset module 24 for 200ms, then pulls up, detects a low level from the input of the reset module 24, then resets the CPLD circuit 2, and re-executes the external reset module 25. And ensuring that the system can be restarted normally.
In the present specification, the embodiments are described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same or similar parts in the embodiments are referred to each other. For the system embodiment, since it basically corresponds to the method embodiment, the description is relatively simple, and for the relevant points, reference may be made to the partial description of the method embodiment.
The description of the present invention has been presented for purposes of illustration and description, and is not intended to be exhaustive or limited to the invention in the form disclosed. Many modifications and variations will be apparent to practitioners skilled in this art. The embodiment was chosen and described in order to best explain the principles of the invention and the practical application, and to enable others of ordinary skill in the art to understand the invention for various embodiments with various modifications as are suited to the particular use contemplated.
Claims (4)
1. An intelligent watchdog circuit system of an OLT device, comprising:
the CPU circuit, the CPLD circuit and the reset circuit;
the CPU circuit is connected with the CPLD circuit through a serial interface line, and the serial interface line comprises a clock line and a data line;
the reset circuit is connected to the CPLD circuit;
the CPLD circuit realizes the watchdog function and the reset function;
the CPU circuit adjusts the reset time and the reset time sequence of the reset circuit through the CPLD circuit, and when the CPU circuit is abnormal, the watchdog circuit of the CPLD circuit realizes the reset of the whole board, thereby ensuring the system to operate again;
the CPLD circuit comprises:
the device comprises a serial port module, a judgment module, a clock module, a self-reset module, an external reset module and a watchdog module;
the serial port module is connected with the CPU circuit and used for detecting data sent by a serial port, judging information sent behind an instruction code as effective information when the serial port module detects the instruction code sent by the data, and sending the information to the external reset module and the watchdog module;
the judging module is connected with the serial port module and the watchdog module, judges whether the CPU circuit works according to whether the serial port module changes, judges the fault of the CPU circuit if the clock level of the serial port module does not change within a set time threshold value, and sends the judging result to the watchdog module;
the self-reset module is used for controlling the self-reset function of the CPLD circuit to be realized;
the clock module is used for detecting an external clock, realizing a plurality of counters inside, facilitating time sequence control and time control, and sending clock signals to the serial port module, the judgment module, the self-reset module, the external reset module and the watchdog module;
the external reset module is used for controlling the reset of external equipment to reset the external equipment according to any sequence and any time;
the watchdog module is connected with the serial port module and the judging module, determines whether to trigger the function of the watchdog module according to the result obtained by the judging module, and receives the data sent by the serial port module when the serial port module has data sending.
2. The intelligent watchdog circuit of the OLT apparatus of claim 1, wherein the instruction code for the data transmission is: 10100101, when the serial module receives the instruction code, it determines that the information sent after the instruction code is valid information.
3. The intelligent watchdog circuit of the OLT apparatus of claim 1, wherein the time threshold is 10 minutes.
4. The intelligent watchdog circuit system of OLT facility of claim 1, wherein said clock module is externally connected to a clock circuit with a frequency of 2.048M, said clock module obtaining any 0.5us multiple of time greater than 0.5us via an external clock circuit.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201810186882.3A CN108388481B (en) | 2018-03-07 | 2018-03-07 | Intelligent watchdog circuit system of OLT equipment |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201810186882.3A CN108388481B (en) | 2018-03-07 | 2018-03-07 | Intelligent watchdog circuit system of OLT equipment |
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| CN108388481A CN108388481A (en) | 2018-08-10 |
| CN108388481B true CN108388481B (en) | 2021-05-11 |
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| CN109753373A (en) * | 2019-01-11 | 2019-05-14 | 东莞固高自动化技术有限公司 | Intelligent watchdog system based on Complex Programmable Logic Devices |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1435743A (en) * | 2002-01-29 | 2003-08-13 | 深圳市中兴通讯股份有限公司上海第二研究所 | Reset method |
| JP2011145208A (en) * | 2010-01-15 | 2011-07-28 | Hitachi Kokusai Electric Inc | Substrate |
| CN204667385U (en) * | 2015-06-10 | 2015-09-23 | 深圳桥通通信技术有限公司 | Based on the hardware watchdog circuit of CPLD/FPGA technology |
| CN206224371U (en) * | 2016-11-07 | 2017-06-06 | 深圳市恒扬数据股份有限公司 | A kind of computer and the reset circuit for computer motherboard |
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2018
- 2018-03-07 CN CN201810186882.3A patent/CN108388481B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1435743A (en) * | 2002-01-29 | 2003-08-13 | 深圳市中兴通讯股份有限公司上海第二研究所 | Reset method |
| JP2011145208A (en) * | 2010-01-15 | 2011-07-28 | Hitachi Kokusai Electric Inc | Substrate |
| CN204667385U (en) * | 2015-06-10 | 2015-09-23 | 深圳桥通通信技术有限公司 | Based on the hardware watchdog circuit of CPLD/FPGA technology |
| CN206224371U (en) * | 2016-11-07 | 2017-06-06 | 深圳市恒扬数据股份有限公司 | A kind of computer and the reset circuit for computer motherboard |
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