CN211087224U - Mainboard and computer equipment - Google Patents

Abstract

The embodiment of the utility model provides a mainboard and computer equipment relates to computer technology field to the device that distributes on solving the mainboard is more, and the overall arrangement space of mainboard is just less, and the wiring surplus of mainboard is corresponding to be reduced, thereby directly influences the stability of system operation and the problem of reliability. Wherein, the mainboard includes: the chip comprises a first chip, a bridge chip and a second chip, wherein the second chip is connected with the first chip and is connected with the bridge chip; the second chip is used for controlling a power-on time sequence and a reset time sequence of the mainboard; the second chip is also used for controlling the logic function of the mainboard; the logic functions of the mainboard at least comprise an interference noise processing function, a second-level starting function, a second-level shutdown function, a reset function, a communication IO expansion function and a mainboard voltage state control function.

Description

Mainboard and computer equipment

Technical Field

The utility model relates to a computer technology field especially relates to a mainboard and computer equipment.

Background

Along with the requirement of the design function of the mainboard is more and more complex, in order to meet the circuit function, more and more devices are distributed on the mainboard. Along with more and more devices distributed on the mainboard, the layout space of the mainboard is less and less, and the wiring allowance of the mainboard is correspondingly reduced, so that the stability and the reliability of the system operation are directly influenced.

SUMMERY OF THE UTILITY MODEL

In view of the above problems, a motherboard and a computer device are provided to overcome the above problems or at least partially solve the above problems, so as to solve the problems that the more devices distributed on the motherboard, the less the layout space of the motherboard, and the less the wiring margin of the motherboard, which directly affect the stability and reliability of the system operation.

On the one hand, in order to solve the above problem, the embodiment of the utility model discloses a mainboard, including first chip and bridge piece, still include: a second chip connected to the first chip and the bridge chip; the second chip is used for controlling a power-on time sequence and a reset time sequence of the mainboard; the second chip is also used for controlling the logic function of the mainboard; the logic functions of the motherboard at least include an interference noise processing function, a second-level power-on function, a second-level power-off function, a reset function, an Input/Output (IO) expansion function of communication, and a motherboard voltage state control function.

Preferably, the main board further includes:

the power supply chip is connected with the external interface of the second chip;

the logic function of the mainboard further comprises a power signal indication function.

Preferably, the second chip is a Field-Programmable Gate Array (FPGA) chip.

Preferably, a plurality of triggers and a plurality of IO pins are integrated inside the FPGA chip;

each trigger is used for storing logic resources used in the FPGA chip;

each IO pin is used for connecting the FPGA chip with the first chip or the bridge chip.

Preferably, the first chip is a Loongson 3A3000 processor or a Loongson 3A4000 processor.

Preferably, the first chip is connected to the FPGA chip through a General-purpose input/output (GPIO) interface.

Preferably, the bridge chip is a Loongson 7A1000 bridge chip, and the Loongson 7A1000 bridge chip is connected with the FPGA chip through an I2C interface.

Preferably, the main board further includes:

a light-Emitting Diode (L light-Emitting Diode (L ED) for short, wherein the L ED is connected with the GPIO interface of the second chip;

wherein the L ED is used for indicating the power-on condition of the mainboard.

Preferably, the main board further includes:

a Peripheral Component Interconnect Express (PCIE) device, where the PCIE device is connected to a PCIE interface of the bridge chip;

and the network equipment is connected with a gigabit media access Control (GMC) interface of the bridge chip.

On the other hand, in order to solve the above problem, the embodiment of the utility model discloses a computer equipment, including above-mentioned mainboard.

The embodiment of the utility model provides a include following advantage:

the utility model discloses in provide a mainboard: in the structure of the original first chip and the bridge chip, a second chip is added, and the second chip is connected with the first chip and the bridge chip. The second chip is used for controlling the power-on time sequence and the reset time sequence of the mainboard. The second chip replaces a power-on scheme which is gradually promoted by a hardware circuit in the prior art, the circuit design requirements are met through the second chip according to the time sequence reset requirement, a large complex circuit is not needed to realize specific functions, and the design density of the mainboard is effectively reduced. In addition, the second chip is also used for controlling the logic function of the mainboard, and the logic function of the mainboard at least comprises an interference noise processing function, a second-level startup function, a second-level shutdown function, a reset function, a communication IO expansion function and a mainboard voltage state control function. The mainboard design scheme based on the second chip sequential logic control replaces a large-scale logic circuit adopted in the design of the mainboard in the prior art, reduces the design density of the mainboard, has sufficient space for layout and wiring, and can achieve the purpose of controlling the logic function of the mainboard, thereby ensuring the stability and reliability of the functional design of the mainboard.

Drawings

Fig. 1 is one of block diagrams of a main board of an embodiment of the present invention;

fig. 2 is a second block diagram of the main board according to the embodiment of the present invention;

fig. 3 is a third block diagram of the main board according to the embodiment of the present invention;

fig. 4 is a fourth block diagram of the main board according to the embodiment of the present invention.

Detailed Description

In order to make the above objects, features and advantages of the present invention more comprehensible, the present invention is described in detail with reference to the accompanying drawings and the detailed description.

Example one

Referring to fig. 1, the present embodiment provides a main board including: the chip comprises a first chip 1 and a bridge chip 2 and further comprises a second chip 3, wherein the second chip 3 is connected with the first chip 1, and the second chip 3 is connected with the bridge chip 2. The second chip 3 is used for controlling the power-on time sequence and the reset time sequence of the mainboard; the second chip 3 is also used for controlling the logic function of the mainboard; the logic function of the mainboard at least comprises an interference noise processing function, a second-level starting function, a second-level shutdown function, a reset function, a communication IO expansion function and a mainboard voltage state control function.

Preferably, according to the functions that can be realized by the second chip 3, it can be considered that the second chip 3 includes a power-on reset timing control module and a logic function control module. The power-on reset time sequence control module is used for controlling the power-on time sequence and the reset time sequence of the mainboard; and the logic function control module is used for controlling the logic functions of the mainboard, such as an interference noise processing function, a second-level starting function, a second-level shutdown function, a reset function, a communication IO expansion function and a mainboard voltage state control function.

The utility model discloses in provide a mainboard: in the structure of the first chip 1 and the bridge chip 2, the second chip 3 is added, the second chip 3 is connected with the first chip 1 through an external interface, and the second chip 3 is connected with the bridge chip 2. The second chip 3 can realize the functions of controlling the power-on time sequence and the reset time sequence of the mainboard.

In the prior art, the power-on sequence function is realized by a hardware circuit, namely, a power-on scheme which is developed step by adopting the hardware circuit is adopted. Specifically, in the hardware circuit in the prior art, a complex hardware circuit is composed of hardware devices, and the power-on timing function for the motherboard is realized by the functions of the hardware devices, wherein the power-on timing function is realized by first 12V, then 5V, then 3.3V, and so on. In the present embodiment, the second chip 3 may implement part of the functions through a hardware description language. Preferably, control of the second chip 3 on the power-on time sequence and the reset time sequence of the mainboard is realized by using a Verilog hardware description language, so that the power-on time sequence and the reset time sequence function realized by a complex hardware circuit consisting of a large number of hardware devices in the prior art can be realized only by one second chip 3, and the design density of the mainboard is effectively reduced; moreover, the sequential control of power-on and reset of the mainboard and the like through the second chip 3 can reach a nanosecond level, and the sequential control effect can meet the functional requirements of the mainboard on the power-on sequential and reset sequential.

Further, the second chip 3 can implement a logic function of controlling the main board. The logic functions of the mainboard at least comprise an interference noise processing function, a second-level (such as 1 second) starting function, a second-level (such as 4 seconds) shutdown function, a reset function, a communication IO expansion function and a mainboard voltage state control function.

In summary, based on the design of the second chip 3, the motherboard design scheme capable of implementing sequential logic control replaces the large-scale logic circuit adopted in the existing motherboard design, and reduces the design density of the motherboard, and the layout and wiring have sufficient space to ensure the stability of the motherboard function design while implementing the function of the existing large-scale logic circuit.

Specifically, in this embodiment, a first chip 1, a bridge chip 2, and a second chip 3 are designed, where a connection interface between the second chip 3 and the first chip 1 and a connection interface between the second chip 3 and the bridge chip 2 are involved, and these connection interfaces may be a common IO interface or a specific external connection interface.

Preferably, the first chip 1 and the second chip 3 may be connected through a general purpose input/output GPIO interface for transmitting GPIO signals; the first chip 1 and the second chip 3 can also be connected through an IO interface and used for transmitting a CPU RST # signal.

Preferably, the first chip 1 is a loongson No. 3 processor, for example, the first chip 1 may be any one of a loongson 3a3000 processor and a loongson 3a4000 processor.

Preferably, the bridge piece 2 is a dragon core 7 bridge piece, for example, the bridge piece 2 may be any one of a dragon core 7a1000 bridge piece and a dragon core 7a2000 bridge piece.

Example two

The embodiment provides a main board. Preferably, the first chip 1 is a loongson No. 3 processor, for example, the first chip 1 may be any one of a loongson 3a3000 processor and a loongson 3a4000 processor.

Preferably, the bridge piece 2 is a dragon core 7 bridge piece, for example, the bridge piece 2 may be any one of a dragon core 7a1000 bridge piece and a dragon core 7a2000 bridge piece.

Preferably, as shown in fig. 2, the main board further includes a power chip 4, and the power chip 4 is connected to an external interface of the second chip 3 for supplying power to the first chip and the bridge chip in the main board.

Referring to fig. 3, the connection between the bridge chip 2 and the second chip 3 may be connected through a plurality of IO interfaces, and is respectively used for transmitting ACPI PWRBTN # signals, ACPI PWROK signals, and the like; the connection between the bridge 2 and the second chip 3 may also be connected via an IIC (also referred to as I2C) interface for transmitting IIC signals.

In the connection relationship shown in fig. 3, the start of an arrow is used to indicate a signal transmitting end, and the end of the arrow is used to indicate a signal receiving end.

In fig. 3, taking the first chip 1 as the processor No. 3 and the bridge chip 2 as the bridge chip No. 7 as an example, in the power chip 4, P12V, P5V, and P3V3 respectively represent voltage values generated by the power chips related to the motherboard, and the voltage values include 12V, 5V, and 3.3V; 7APWR, CPUPWR and MEMPWR respectively represent that the power supply voltage values of No. 7 Loongson bridge chips related to the mainboard are 1.2V and 1.8V, the power supply voltage values of No. 3 Loongson processors are 1.1V, 1.2V, 1.8V and 2.5V, and the power supply voltage value of the memory is 2.5V; all the voltages are generated by the power chip 4, the enable signal PWR EN of the power chip 4 is sent by the second chip 3, and accordingly, when the power chip 4 outputs the voltages normally, the signal PWR GOOD is sent to the second chip 3.

Furthermore, the motherboard further includes a physical switch (not shown in the figure), as shown in fig. 3, the PWR BTN # signal is a signal generated by the physical switch, the second chip 3 can control the motherboard to be turned on and off according to the PWR BTN # signal, CPURST #, CP L D _7A RST #, and RST device signals are all signals sent by the second chip 3 to reset other devices such as the motherboard godson 3 processor and the godson 7 bridge, ACPI PWRBTN #, ACPI PWROK, ACPI S3#, ACPI S4#, and ACPI S5# are all signals of the second chip 3 communicating with the godson 7 bridge, and are all used to realize the control of the motherboard on and off function, and ACPI P L TRST # is used to realize the reset control function of the motherboard.

In fig. 3, transmission interfaces of signals such as CPU RST #, CP L D _7A RST #, ACPI PWRBTN #, ACPI PWROK, ACPI S3#, ACPI 4#, ACPI S5#, ACPI P L TRST # and the like are specific IO interfaces of the loongson No. 3 processor and the loongson No. 7 bridge, interfaces of the second chip 3 corresponding to the signals may correspond to different IO interfaces, GPIO interfaces are specific interfaces of the second chip 3 and the CPU, and an external interface of the power chip 4 may be connected to the IO interface of the second chip 3.

EXAMPLE III

For example, the second chip 3 may be a Complex Programmable logic Device (CP L D) chip, and preferably, the second chip 3 is an FPGA chip.

The FPGA chip is a programmable logic device, adopts a high-speed Complementary Metal Oxide Semiconductor (CMOS) process, has low power consumption, integrates abundant triggers and IO pins in the FPGA chip, and has the characteristics of flexible logic units and high integration level. In addition, the FPGA chip can design different logic gate circuits into circuits capable of realizing specific functional requirements, so that the development progress of a hardware system is improved, and the development cost is reduced.

The FPGA chip integrates a large number of logic gate circuits, saves the design space of a mainboard, and provides reliability guarantee for the stable operation of later system functions.

Preferably, a plurality of flip-flops and a plurality of IO pins are integrated inside the FPGA chip. Each trigger is used for storing logic resources used for code programming in the FPGA chip and is connected with a corresponding IO pin so as to realize different logic functions of the mainboard; each IO pin is used for connecting the FPGA chip with the first chip 1 or with the bridge chip 2.

Preferably, the first chip 1 is a loongson No. 3 processor, for example, the first chip 1 may be any one of a loongson 3a3000 processor and a loongson 3a4000 processor.

Preferably, the bridge piece 2 is a dragon core 7 bridge piece, for example, the bridge piece 2 may be any one of a dragon core 7a1000 bridge piece and a dragon core 7a2000 bridge piece.

In the mainboard design scheme based on Loongson No. 3 treater and Loongson No. 7 bridge, according to mainboard functional requirements, utilize the FPGA chip can realize the characteristic of specific function with different logic gate circuit design backs, can effectively improve the reliability and the stability of mainboard.

The mainboard design scheme based on FPGA sequential logic control can realize the characteristic of specific function after different logic gate circuits are designed through an FPGA chip, replaces a large-scale hardware circuit adopted in the original mainboard design, and reduces the design density of the mainboard, so that the layout and wiring on the mainboard have sufficient space, and the stability of the mainboard in function design is ensured.

In the embodiment of the invention, the second chip 3 is used for realizing the functions of starting up, hard shutdown, soft shutdown, hard reset and the like of the mainboard in the mainboard design scheme. When the functions of starting up and hard shutdown of the mainboard are realized, the starting up signal and the hard shutdown signal of the mainboard are required to be second-level signals; when the functions of soft shutdown and hard reset of the mainboard are realized, the soft shutdown signal and the hard reset signal are required to be nanosecond level signals. Based on the requirement of the mainboard for sequential logic control, in the embodiment of the utility model, the FPGA chip is utilized to realize the functions of starting, hard shutdown, soft shutdown and hard reset of the mainboard in the design scheme of the mainboard comprising the FPGA chip; and when the power-on time sequences of different voltage chips on the mainboard and the logic function of the mainboard are controlled by the FPGA chip, the nanosecond level can be accurately achieved, and therefore the requirement of the mainboard on time sequence logic control can be met through the FPGA chip.

Referring to fig. 4, preferably, the loongson No. 3 processor communicates with a GPIO interface of the FPGA chip through its own GPIO interface; in addition, the Loongson No. 3 processor can also communicate with an IO interface of the FPGA chip through the IO interface thereof (not shown in the figure). The Loongson No. 7 bridge chip can communicate with an I2C interface of an FPGA chip through an I2C interface of the Loongson No. 7 bridge chip, so that the board-level voltage monitoring or IO expansion function is realized; in addition, the Loongson No. 7 bridge chip can also communicate with an IO interface of the FPGA chip through the IO interface (not shown in the figure).

In the prior art, the power-on scheme of the mainboard is gradually deduced by a hardware circuit, and although the power supply voltages of the Loongson No. 3 processor and the Loongson No. 7 bridge chip do not have strict power-on time sequences, the reset time sequences of the Loongson No. 3 processor and the Loongson No. 7 bridge chip have strict requirements. This requires timing issues to be considered when designing power-on signals and reset signals of the motherboard, i.e. in the power-on process, the reset signal can only be enabled when the voltage of the main chips (including the processor No. 3 of the Loongson and the bridge No. 7 of the Loongson) is stable and reaches a rated value; and, after the main chips are reset successfully, the mainboard can work normally.

Based on the above process, it is necessary to design a complicated hardware circuit for the motherboard to achieve the required precise control. The embodiment of the utility model provides an in, adopt the last electric chronogenesis of FPGA chip control mainboard and the chronogenesis that resets, according to the chronogenesis design requirement, utilize Verilog hardware description language for the function of FPGA chip satisfies the circuit design demand, the effectual design density that reduces the mainboard, and the sequential control precision can be realized to the nanosecond level moreover.

In the implementation process, the main board further comprises a power supply chip, and the power supply chip is used for supplying power to the first chip and the bridge chip in the main board; the enabling signals of the power chips of the Loongson No. 3 processor and the Loongson No. 7 bridge chip are controlled by the FPGA chip, the enabling signals of the Loongson No. 3 processor and the Loongson No. 7 bridge chip are all enabled, the working voltages of the two devices can be normal, and then the two devices are reset through the reset signals, so that the two devices can work normally.

Furthermore, the mainboard also comprises PCIE equipment and network equipment; reset signals of the whole mainboard are sent to the FPGA chip by the Loongson No. 7 bridge chip, and the reset of the Loongson No. 3 processor, the PCIE equipment and the network equipment is realized by the FPGA chip. The interface between the PCIE device and the Loongson No. 7 bridge chip is a PCIE interface, that is, the PCIE interface of the PCIE device is connected to the PCIE interface of the Loongson No. 7 bridge chip; the interface of the network device connected with the Loongson No. 7 bridge chip is a GMC interface, namely the GMC interface of the network device is connected with the GMC interface of the Loongson No. 7 bridge chip.

In addition, the processor No. 3 may be further connected to the bridge No. 7, where an interface of the processor No. 3 may be an end-to-end bus (HT) interface (not shown), that is, an HT interface of the processor No. 3 is connected to an HT interface of the bridge No. 7.

Preferably, the power chip 4 is used for supplying power to the Loongson No. 3 processor and the Loongson No. 7 bridge chip; optionally, the motherboard may include a power chip 4, which respectively supplies power to the Loongson No. 3 processor and the Loongson No. 7 bridge according to characteristics of the Loongson No. 3 processor and the Loongson No. 7 bridge; or, the motherboard may include two power chips 4, which are a first power chip and a second power chip, respectively, where the first power chip supplies power to the processor No. 3 of the Loongson, and the second power chip supplies power to the bridge chip No. 7 of the Loongson.

In the embodiment of the utility model, the FPGA chip comprises a relatively mature time function module, a key shaking removal module, a signal synchronization module and an upper power-on time sequence module which can be directly called by a top layer design module, thereby realizing the function of design requirement; based on the method, the power-on reset time sequence control of the power supply chip on the mainboard is realized through the FPGA chip according to the hardware function requirement of the mainboard.

Preferably, the logic function control module comprises: a noise unit for controlling an interference noise processing function; the switch unit is used for controlling a 1-second starting function and a 4-second shutdown function; a reset unit for controlling a reset function; and the expansion unit is used for controlling the IO expansion function of communication.

In the prior art, for the problem of interference noise of a mainboard hardware system, a mode of setting up a filter circuit for an input signal and an output signal by using a capacitance inductor to filter out noise is generally adopted when a circuit is designed, but the problem of noise cannot be thoroughly solved by a hardware circuit; the embodiment of the utility model provides an in, can be inside the FPGA chip, can realize accurate noise treatment through generating logic circuit. The generated logic circuit is a noise unit, and is used for controlling an interference noise processing function so as to process interference noise in a mainboard hardware system.

In order to prevent false triggering of the mainboard hardware system, the startup and shutdown function is realized through the FPGA chip, the 1-second startup and 4-second shutdown functions can be realized, and the normal work of the mainboard hardware system is not influenced by misoperation. The switch unit in the FPGA chip can realize the on-off function.

The embodiment of the utility model provides an in, through the communication between FPGA chip and the key chip, realize logic control. For example, in the embodiment of the utility model provides an in, when the fatal trouble of non-appears in longson No. 3 treater, No. 3 treater of longson transmits Error signal Error through GPIO interface and FPGA chip. After receiving the Error signal, the FPGA chip can reset the mainboard system, and the normal operation of the mainboard is ensured. The reset unit in the FPGA chip can realize the logic control function.

The embodiment of the utility model provides an in, the FPGA chip still can realize extending the IO function. For example, the Loongson No. 7 bridge chip is connected with an I2C interface of the FPGA chip through an I2C interface of the Loongson No. 7 bridge chip, that is, the Loongson No. 7 bridge chip can transmit 8 bytes of data to the FPGA chip through an I2C interface, and each byte can contain 8 bits; when the Power supply chip on the mainboard works normally, the Power supply chip can send out a Power Good (PWR GOOD in fig. 3) signal to the FPGA chip; according to the mechanism and the characteristics of the mainboard, the mainboard has various voltage values, the specific voltage values include 12V, 5V and 3.3V, the voltage value of a CPU and the voltage value of an internal memory, after the voltage values all work normally, the corresponding Power supply chip sends Power Good signals to the FPGA chip, and after the FPGA chip receives the signals, the signals are communicated with an I2C interface (a data line and a clock line of I2C) of a No. 7 bridge chip through an I2C interface (a data line and a clock line of I2C) according to an I2C format. Similarly, the version signal of the FPGA chip is transmitted to the No. 7 bridge chip through the I2C interface, so that the No. 7 bridge chip monitors the state of the mainboard; in prior art, need a plurality of pins (interface) just can accomplish the communication between FPGA chip and No. 7 bridgeplates, and the embodiment of the utility model provides an, only need two pins of data line and the clock line of I2C interface, only have two pins because of the I2C bus that the I2C interface corresponds, correspond data line and clock line respectively, the FPGA chip passes through I2C bus communication with No. 7 bridgeplates, make the data line can transmit a lot of IO data, and how specific data line realizes transmitting a lot of IO data, can realize through the FPGA chip, thereby can save the pin use of chip, adopt the I2C interface to extend the function of chip IO. The expansion unit in the FPGA chip can realize the expansion IO function.

Preferably, the expansion unit includes: and the monitoring subunit is used for monitoring the voltage state of the mainboard.

The monitoring subunit sends the voltage state of the mainboard obtained by monitoring to the Loongson No. 7 bridge chip through the I2C interface, so that the Loongson No. 7 bridge chip monitors the state of the mainboard.

Preferably, the logic function control module in the FPGA chip further includes: and the indicating unit is used for controlling the power supply signal indicating function.

Preferably, the mainboard further comprises L ED connected with the IO interface of the second chip and used for indicating the Power-ON condition of the mainboard explicitly, and an indicating unit in the FPGA chip is used for indicating the Power-ON function, when the Power Good signal of the Power chip 4 is connected to the FPGA chip, the input Power Good signal is at a high level, the FPGA chip drives L ED through the IO interface ON the FPGA chip after receiving the high level signal, when L0 ED is ON, the Power is normal, and simultaneously, the Power-ON timing of the system can be realized by a plurality of L1 EDs, for example, four L2 EDs are arranged, wherein the four L EDs are respectively L ED0, L ED1, L ED2 and L ED3, when the PWR _ ON Power-ON timing is normal, the corresponding L ED states L ED 0-L ED2 and L ED3 are ON, and when the mainboard has a fault, the system can detect the Power-ON state intuitively, and the Power-ON status of the system is convenient for positioning the fault.

In sum, as the design function requirements of the main board are more and more complex, the integration level on the main board is higher and higher, and the stability and reliability of the system operation are directly influenced. When the circuit is designed, on the premise of meeting the circuit function, the number of devices is reduced as much as possible, a chip with higher function integration level is selected, the layout space of the mainboard is reduced, and the wiring allowance of the mainboard is increased, so that the reliability of the functional design of the mainboard is increased. The mainboard design scheme based on the FPGA chip replaces a large-scale logic circuit adopted in the original mainboard design through the FPGA chip with higher integration level, reduces the design density of the mainboard, has sufficient space for layout and wiring, and ensures the stability of the mainboard during main function design.

Example four

The embodiment provides a computer device, which comprises the main board in any one of the above embodiments.

Referring to fig. 1 to 4, the main board includes: the chip comprises a first chip 1 and a bridge chip 2 and further comprises a second chip 3, wherein the second chip 3 is connected with the first chip 1, and the second chip 3 is connected with the bridge chip 2. The second chip 3 is used for controlling the power-on time sequence and the reset time sequence of the mainboard; the second chip 3 is also used for controlling the logic function of the mainboard; the logic function of the mainboard at least comprises an interference noise processing function, a second-level starting function, a second-level shutdown function, a reset function, a communication IO expansion function and a mainboard voltage state control function.

The utility model discloses in provide a computer equipment, including the mainboard, the mainboard has increased second chip 3 in original first chip 1 and bridge piece 2's structure, and second chip 3 is connected with first chip 1, and is connected with bridge piece 2. The second chip 3 can realize the functions of controlling the power-on time sequence and the reset time sequence of the mainboard. In the original hardware circuit, the functions of the hardware devices are used for realizing the power-on scheme that the power is firstly 12V, then 5V, then 3.3V and the like, and the power is gradually pushed out by the hardware circuit. In this embodiment, the design density of the motherboard is effectively reduced by the second chip, and the timing control can be performed at nanosecond level. Further, the second chip 3 is also used to control the logic functions of the motherboard. The logic functions of the mainboard at least comprise an interference noise processing function, a second-level (such as 1 second) starting function, a second-level (such as 4 seconds) shutdown function, a reset function, a communication IO expansion function and a mainboard voltage state control function. In conclusion, based on the design of the second chip 3, the mainboard design scheme of sequential logic control can be realized, a large-scale logic circuit adopted in the original mainboard design is replaced, the design density of the mainboard is reduced, the layout and wiring have sufficient space, and the stability of the mainboard in functional design is ensured.

The embodiments in the present specification are described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments are referred to each other.

As will be appreciated by one skilled in the art, embodiments of the present invention may be provided as a method, apparatus, or computer program product. Accordingly, embodiments of the present invention may take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Furthermore, embodiments of the present invention may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, and the like) having computer-usable program code embodied therein.

Embodiments of the present invention are described with reference to flowchart illustrations and/or block diagrams of methods, terminal devices (systems), and computer program products according to embodiments of the invention. It will be understood that each flow and/or block of the flow diagrams and/or block diagrams, and combinations of flows and/or blocks in the flow diagrams and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing terminal to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing terminal, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.

These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing terminal to function in a predictive manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.

These computer program instructions may also be loaded onto a computer or other programmable data processing terminal to cause a series of operational steps to be performed on the computer or other programmable terminal to produce a computer implemented process such that the instructions which execute on the computer or other programmable terminal provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.

While preferred embodiments of the present invention have been described, additional variations and modifications of these embodiments may occur to those skilled in the art once they learn of the basic inventive concepts. It is therefore intended that the following claims be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the embodiments of the invention.

Finally, it should also be noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or terminal that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or terminal. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other like elements in a process, method, article, or terminal that comprises the element.

The main board and the computer device provided by the present invention are introduced in detail, and the principle and the implementation of the present invention are explained by applying specific examples, and the descriptions of the above embodiments are only used to help understand the method and the core idea of the present invention; meanwhile, for the general technical personnel in the field, according to the idea of the present invention, there are changes in the specific implementation and application scope, to sum up, the content of the present specification should not be understood as the limitation of the present invention.

Claims (10)

1. A motherboard, comprising: first chip and bridge piece, its characterized in that still includes:

a second chip connected to the first chip and the bridge chip;

the second chip is used for controlling a power-on time sequence and a reset time sequence of the mainboard;

the second chip is also used for controlling the logic function of the mainboard;

the logic functions of the mainboard at least comprise an interference noise processing function, a second-level starting function, a second-level shutdown function, a reset function, a communication IO expansion function and a mainboard voltage state control function.

2. The motherboard of claim 1, further comprising:

the power supply chip is connected with the external interface of the second chip;

the logic function of the mainboard further comprises a power signal indication function.

3. The motherboard of claim 1 or 2, wherein the second chip is an FPGA chip.

4. The mainboard of claim 3, wherein a plurality of flip-flops and a plurality of IO pins are integrated within the FPGA chip;

each trigger is used for storing logic resources used in the FPGA chip;

each IO pin is used for connecting the FPGA chip with the first chip or the bridge chip.

5. The motherboard of claim 3, wherein the first chip is a Loongson 3A3000 processor or a Loongson 3A4000 processor.

6. The mainboard of claim 5, wherein the first chip is connected to the FPGA chip via a GPIO interface.

7. The mainboard of claim 3, wherein the bridge is a Loongson 7A1000 bridge, and the Loongson 7A1000 bridge is connected with the FPGA chip through an I2C interface.

8. The motherboard of claim 3, further comprising:

l ED, the L ED interfacing with a GPIO of the second chip;

wherein the L ED is used for indicating the power-on condition of the mainboard.

9. The motherboard of claim 3, further comprising:

the PCIE equipment is connected with a PCIE interface of the bridge piece;

a network device connected to the GMC interface of the bridge slice.

10. A computer device comprising a motherboard according to any of claims 1 to 9.

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