CN214311726U

CN214311726U - A adapter plate for prototype is verified

Info

Publication number: CN214311726U
Application number: CN202022637671.2U
Authority: CN
Inventors: 王栋栋; 唐超杰
Original assignee: Xinhuazhang Technology Co ltd
Current assignee: Xinhuazhang Technology Co ltd
Priority date: 2020-11-13
Filing date: 2020-11-13
Publication date: 2021-09-28
Anticipated expiration: 2030-11-13

Abstract

The present disclosure provides an adapter board for prototype verification. This adapter plate includes: a motherboard interface for connecting the adapter board to a motherboard; a plurality of external interfaces for connecting a plurality of external devices; and the first controller is connected with the motherboard interface and the plurality of external interfaces and is used for communicating the motherboard interface with one of the plurality of external interfaces.

Description

A adapter plate for prototype is verified

Technical Field

The present disclosure relates to an adapter board technology, and more particularly, to an adapter board for adapting to a prototype verification motherboard.

Background

A prototype verification system can prototype and debug a logic system design that includes one or more modules. The logic System design may be, for example, a design for an Application Specific Integrated Circuit (ASIC) or a System-On-Chip (SOC) for a Specific Application. Therefore, the logic system design that is prototyped in the prototype verification system may also be referred to as a Device Under Test (DUT). The prototype verification system may verify the device under test by one or more configurable components, such as a Field Programmable Gate Array (FPGA), including performing various operations of the device under test, so as to test and verify the functions of various modules of the device under test before manufacturing.

The prototype verification system includes a motherboard and a daughter board. The daughter board may also be referred to as an adapter board. The motherboard loads the FPGA to instantiate the device under test. The daughter board is connected to the motherboard for providing an external interface. In the prior art, one motherboard may be associated with a plurality of daughter boards (e.g., a memory interface daughter board, a video interface daughter board, an ethernet interface daughter board, a PCI interface daughter board, etc.). These daughter boards may be connected to the motherboard via connectors (e.g., 6 connectors) of the motherboard and constitute a complete prototype verification system.

Since the number of connectors of the motherboard is limited and the number of daughter boards is large, a daughter board supporting a plurality of interface protocols needs to be developed.

SUMMERY OF THE UTILITY MODEL

In view of the above, the present disclosure proposes an adapter board for prototype verification. This adapter plate includes: a motherboard interface for connecting the adapter board to a motherboard; a plurality of external interfaces for connecting a plurality of external devices; and the first controller is connected with the motherboard interface and the plurality of external interfaces and is used for communicating the motherboard interface with one of the plurality of external interfaces.

In some embodiments, the first controller is a field programmable gate array, an application specific integrated circuit, or a micro-control unit.

In some embodiments, the input signal of the first controller is a motherboard signal from the motherboard, the first controller configured to: determining a type according to the motherboard signal; determining a target external interface corresponding to the type of the motherboard signal; and sending the motherboard signal to the target external interface.

In some embodiments, the input signal of the first controller is an external device signal from an external interface, the first controller configured to: generating an indication signal for indicating a type of the external device signal; and sending the external device signal to the motherboard interface.

In some embodiments, the adapter plate further comprises: a second controller connected to the first controller via an SPI bus for controlling communication of the first controller with the plurality of external interfaces.

In some embodiments, the adapter plate further comprises: a crystal oscillator connected to the second controller via an I2C bus for providing a clock frequency to the first controller, wherein the second controller is further configured to control the clock frequency of the crystal oscillator.

In some embodiments, the plurality of external interfaces includes a PCI-E interface, an ethernet interface, a memory interface, a SAS interface, or an optical communication interface.

In some embodiments, the motherboard interface is a HapsTrak interface.

By providing a first controller in the adapter board and connecting the respective external interfaces to the first controller, the first controller is enabled to communicate between the adapter board and the motherboard according to the type of signal. Therefore, one adapter board can integrate various external interfaces and support various interface protocols, the occupation of a connector of a motherboard is reduced, and the number of the adapter boards required by a user for debugging equipment to be tested is reduced. Meanwhile, the first controller and the second controller are provided, so that a user has certain configuration capacity on the adapter board, and the adaptation capacity of the adapter board is improved.

Drawings

In order to more clearly illustrate the present disclosure or the technical solutions in the prior art, the drawings needed for the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only the present disclosure, and other drawings can be obtained by those skilled in the art without inventive efforts.

Fig. 1 shows a schematic view of an adapter board for prototype verification according to an embodiment of the present disclosure.

Detailed Description

For the purpose of promoting a better understanding of the objects, aspects and advantages of the present disclosure, reference is made to the following detailed description taken in conjunction with the accompanying drawings.

It is to be noted that technical or scientific terms used herein should have the ordinary meaning as understood by those of ordinary skill in the art to which this disclosure belongs, unless otherwise defined. The use of "first," "second," and similar terms in this disclosure is not intended to indicate any order, quantity, or importance, but rather is used to distinguish one element from another. The word "comprising" or "comprises", and the like, means that the element or item listed before the word covers the element or item listed after the word and its equivalents, but does not exclude other elements or items. The terms "connected" or "coupled" and the like are not restricted to physical or mechanical connections, but may include electrical connections, whether direct or indirect.

As described above, since the number of connectors of the motherboard is limited and the number of adapter boards is large, it is necessary to develop an adapter board supporting a plurality of interface protocols. Typically, a motherboard may provide 6 connectors (e.g., HapsTrak connectors) for connection to an adapter board, while an existing memory interface adapter board (e.g., DDR interface adapter board) consumes 3 connectors. Not to mention that each adapter board is expensive, and a plurality of adapter boards are needed to completely build the verification environment of the equipment to be tested, which is very expensive. Therefore, it is necessary to develop an adapter board supporting multiple interface protocols, so as to save the connectors and reduce the cost.

Fig. 1 shows a schematic view of an adapter board 100 for prototype verification according to an embodiment of the present disclosure.

As shown in fig. 1, the adapter board 100 may include a plurality of

external interfaces

102 and 110, a motherboard interface 112, and a first controller 114 connected to the motherboard interface 112 and the plurality of

external interfaces

102 and 110.

The motherboard interface 112 may be used to connect the adapter board 100 to a motherboard (not shown). In some embodiments, the motherboard may be a HAPS (High-performance ASIC Prototyping System) motherboard and the motherboard interface 112 may be a hapsrak interface. The motherboard interface 112 may be adapted to one or more connectors (e.g., 3).

The plurality of

external interfaces

102 and 110 may include a PCI-E interface, an Ethernet interface, a memory interface, a SAS interface, or an optical communication interface for connecting a plurality of external devices (e.g., PCI-E devices, Ethernet devices, memory devices, SAS devices, or optical communication devices). In some embodiments, external interface 102 may be a PCI-E interface, external interface 104 may be an ethernet interface, external interface 106 may be a memory interface (e.g., a DDR4 interface), external interface 108 may be a sas (serial Attached scsi) interface, and external interface 110 may be an optical communication interface (e.g., a four-channel SFP interface).

The first controller 114 may be used to communicate the motherboard interface 112 with one of the plurality of

external interfaces

102 and 110. In this way, the motherboard can communicate with external devices connected to some external interface via motherboard interface 112. In some embodiments, the first controller 114 may be a Field Programmable Gate Array (FPGA), an Application Specific Integrated Circuit (ASIC), a Micro Controller Unit (MCU), or the like.

In some embodiments, the input signal of the first controller 114 may be a motherboard signal from a motherboard, and the first controller 114 is configured to send the motherboard signal to a target external interface (e.g., one of the external interfaces 102 and 110) corresponding to the type of the motherboard signal according to the type of the motherboard signal. For example, the motherboard signal may include a field to indicate the type of motherboard signal. The type of motherboard signal may be a PCI-E signal, an ethernet signal, a memory signal, a SAS signal, or an optical communication signal. The first controller 114 may accordingly transmit the motherboard signal to the corresponding external interface according to the type of the motherboard signal, and further to the corresponding external device.

In some embodiments, the input signal of the first controller 114 may be an external device signal from an external interface (e.g., any one of the external interfaces 102 and 110). At this time, the first controller 114 may be configured to: generating an indication signal for indicating a type of the external device signal; and transmits the external device signal to the motherboard interface 112. For example, when the input signal is from a memory device, the first controller 114 may generate an indication signal for indicating that the external device signal is a memory signal. For example, the first controller 114 may determine the type of the external device signal according to an interface number of the external interface. When the motherboard (not shown) receives the external device signal, the external device signal may be processed accordingly according to the indication information.

It will be appreciated that the first controller 114 may implement the above-described functions accordingly, depending on the type of device it is used with. For example, when the first controller 114 is an FPGA, the above functions may be described in a Hardware Description Language (HDL) and loaded into the FPGA for execution. When the first controller 114 is a dedicated chip (or asic), the above functions may be solidified into the functions of the dedicated chip. When the first controller 114 is an MCU, the functions may be implemented by the MCU in an embedded programming manner. Those of ordinary skill in the art will appreciate that the first controller 114 may be implemented in a variety of ways not limited to the exemplary descriptions above.

As shown in fig. 1, the adapter board 100 may further include a second controller 116 and a crystal oscillator 118.

The second controller 116 may be connected to the first controller 114 via the SPI bus for controlling the communication between the first controller 114 and the plurality of

external interfaces

102 and 110. In some embodiments, the second controller 116 may be an MCU.

The crystal 118 may be connected to the second controller 116 via an I2C bus for providing a clock frequency to the first controller 114. Accordingly, the second controller 116 may be further configured to control the clock frequency of the crystal oscillator 118. Thus, the user can configure the clock frequency of the first controller 114 via the second controller 116. A typical clock frequency may be set to 156.25 Mhz.

By providing a first controller in the adapter board and connecting the respective external interfaces to the first controller, the first controller is enabled to communicate between the adapter board and the motherboard according to the type of signal. Therefore, one adapter board can integrate various external interfaces, the occupation of a connector of a motherboard is reduced, and the number of the adapter boards required by a user for debugging equipment to be tested is reduced. Meanwhile, the first controller and the second controller are provided, so that a user has certain configuration capacity on the adapter board, and the adaptation capacity of the adapter board is improved.

Those of ordinary skill in the art will understand that: the discussion of any embodiment above is meant to be exemplary only, and is not intended to intimate that the scope of the disclosure, including the claims, is limited to these examples; within the idea of the present disclosure, features in the above embodiments or in different embodiments may also be combined, steps may be implemented in any order, and there are many other variations of the different aspects of the present disclosure as described above, which are not provided in detail for the sake of brevity.

The present disclosure is intended to embrace all such alternatives, modifications and variances which fall within the broad scope of the appended claims. Therefore, any omissions, modifications, equivalents, improvements, and the like that may be made within the spirit and principles of the disclosure are intended to be included within the scope of the disclosure.

Claims

1. An adapter board for prototype verification, comprising:

a motherboard interface for connecting the adapter board to a motherboard;

a plurality of external interfaces for connecting a plurality of external devices; and

and the first controller is connected with the motherboard interface and the plurality of external interfaces and is used for communicating the motherboard interface with one of the plurality of external interfaces.

2. The adapter board of claim 1, wherein the first controller comprises a field programmable gate array, an application specific integrated circuit, or a micro control unit.

3. The adapter board of claim 1, wherein the input signal of the first controller is a motherboard signal from the motherboard, the first controller configured to:

determining a type of the motherboard signal;

determining a target external interface corresponding to the type of the motherboard signal; and

sending the motherboard signal to the target external interface.

4. The adapter board of claim 1, wherein the input signal of the first controller is an external device signal from an external interface, the first controller configured to:

generating an indication signal for indicating a type of the external device signal; and

sending the external device signal to the motherboard interface.

5. The adapter board of claim 1, further comprising:

a second controller connected to the first controller via an SPI bus for controlling communication of the first controller with the plurality of external interfaces.

6. The adapter board of claim 5, further comprising:

a crystal oscillator connected to the second controller via an I2C bus for providing a clock frequency to the first controller, wherein,

the second controller is further configured to control a clock frequency of the crystal oscillator.

7. The adapter board of claim 1, wherein the plurality of external interfaces comprise PCI-E interfaces, ethernet interfaces, memory interfaces, SAS interfaces, or optical communication interfaces.

8. The adapter board of claim 1, wherein the motherboard interface is a HapsTrak interface.