CN112269347B - Power-on and power-off time sequence control device - Google Patents
Power-on and power-off time sequence control device Download PDFInfo
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- CN112269347B CN112269347B CN202011542078.8A CN202011542078A CN112269347B CN 112269347 B CN112269347 B CN 112269347B CN 202011542078 A CN202011542078 A CN 202011542078A CN 112269347 B CN112269347 B CN 112269347B
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- G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
- G05B19/00—Programme-control systems
- G05B19/02—Programme-control systems electric
- G05B19/04—Programme control other than numerical control, i.e. in sequence controllers or logic controllers
- G05B19/042—Programme control other than numerical control, i.e. in sequence controllers or logic controllers using digital processors
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
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Abstract
A power-on and power-off time sequence control device comprises a first power-on and power-off time sequence control unit, a second power-on and power-off time sequence control unit, a power supply monitoring circuit, an OR circuit and an AND circuit. The power supply monitoring circuit is used for outputting a first state electric signal or a second state electric signal when the input voltage is higher than a first preset value or the input voltage is lower than a second preset value. The first power-on and power-off time sequence control unit and the second power-on and power-off time sequence control unit respectively comprise a power supply sequence control circuit and at least one power supply branch circuit, the power supply sequence control circuit responds to an enabling signal and sequentially sends a switch control signal to the power supply branch circuits according to a preset sequence, and the power supply branch circuits respond to the switch control signal and convert the power-on power supply into an output power supply to be output. The OR circuit and the AND circuit are used for outputting enable signals to the first power-up and power-down sequence control unit and the second power-up and power-down sequence control unit respectively. The power supply monitoring circuit is only used for controlling the output of the power-on and power-off instructions, so that the power-on and power-off time sequence control can be realized without programming devices.
Description
Technical Field
The invention relates to the technical field of radio frequency circuits, in particular to a power-on and power-off time sequence control device.
Background
Some rf chips in rf circuits require strict power-up and power-down timing, such as a high-frequency rf switch, and the power-up and power-down timing must be reciprocal, that is, power-up is performed first and then power-down is performed, and power-up and power-down of some rf chips need a certain delay to be turned on and off completely. When the two radio frequency chips are in the same radio frequency circuit system, the power-up and power-down time sequence needs to be accurately controlled, and the power-up and power-down sequence and the power-up and power-down delay time need to be controlled.
Disclosure of Invention
The technical problem to be solved by the application is how to realize the power-on and power-off time sequence control of a radio frequency chip in a radio frequency circuit.
According to a first aspect, an embodiment provides a power-on/power-off timing control apparatus, including a power input terminal, at least two groups of power-on output terminals, a first power-on/power-off timing control unit, a second power-on/power-off timing control unit, a power monitoring circuit, an or circuit, and an and circuit;
the power supply input end is used as the input end of a power-on power supply;
the power supply monitoring circuit comprises a first connecting end and a second connecting end, the first connecting end of the power supply monitoring circuit is connected with the power supply input end, and the second connecting end of the power supply monitoring circuit is respectively connected with the OR circuit and the AND circuit; the power supply monitoring circuit is used for outputting a first state electric signal through a second connecting end of the power supply monitoring circuit when the input voltage of the power supply input end is higher than a first preset value, and outputting a second state electric signal through the second connecting end of the power supply monitoring circuit when the input voltage of the power supply input end is lower than a second preset value; the first preset value is larger than the second preset value;
the first power-up and power-down time sequence control unit and the second power-up and power-down time sequence control unit comprise a power supply sequence control circuit and at least one power supply branch circuit; the power supply sequence control circuit comprises a first connecting end, an enabling signal input end and sequence control signal output ends, wherein the number of the sequence control signal output ends is the same as that of the power supply branches; the first connecting end of the power supply sequence control circuit is connected with the power supply input end; each sequential control signal output end of the power sequential control circuit is connected with one power branch; the enable signal input end of the power supply sequence control circuit is used for inputting an enable signal; the power supply sequence control circuit is used for responding to the enabling signal and sequentially sending a switch control signal to the power supply branch circuit according to a preset sequence through the sequence control signal output end; the power supply branch circuit comprises a first connecting end, a second connecting end and a third connecting end, wherein the first connecting end of the power supply branch circuit is connected with the first connecting end of the power supply sequence control circuit, and the second connecting end of the power supply branch circuit is connected with one sequence control signal output end of the power supply sequence control circuit; the third connecting end of the power supply branch of the first power-up and power-down time sequence control unit is used for being connected with one group of power-up output ends, and the third connecting end of the power supply branch of the second power-up and power-down time sequence control unit is used for being connected with the other group of power-up output ends; the power supply branch circuit is used for responding to the switch control signal to convert the power-on power supply into an output power supply and outputting the output power supply through a third connecting end of the power supply branch circuit;
the OR circuit comprises a first connecting end, a second connecting end and a third connecting end; the first connecting end of the OR circuit is connected with the second connecting end of the power supply monitoring circuit, and the second connecting end of the OR circuit is connected with the last order control signal output end of the power supply order control circuit of the second power-up and power-down time sequence control unit; the third connecting end of the OR circuit is connected with an enabling signal input end of a power supply sequence control circuit of the first power-on and power-off time sequence control unit; the OR circuit is used for outputting the enable signal to a power sequence control circuit of the first power-up and power-down sequence control unit when at least one of a first connecting end and a second connecting end of the OR circuit inputs a high-level electric signal;
the fetch and connection circuit comprises a first connection end, a second connection end and a third connection end; the first connecting end of the taking and connecting circuit is connected with the second connecting end of the power supply monitoring circuit, and the second connecting end of the taking and connecting circuit is connected with the last order control signal output end of the power supply order control circuit of the first power-up and power-down time sequence control unit; the third connecting end of the taking and connecting circuit is connected with an enabling signal input end of a power supply sequence control circuit of the second power-on and power-off time sequence control unit; the AND circuit is used for outputting the enable signal to the power supply sequence control circuit of the second power-up and power-down sequence control unit when the first connecting end and the second connecting end of the AND circuit input high-level electric signals.
In one embodiment, the power branch comprises an LDO power circuit, a diode D1, a capacitor C1, and a power switch circuit;
the input end of the LDO power circuit is connected with the first connecting end of the power branch circuit, and the output end of the LDO power circuit is connected with the positive connecting end of a diode D1; the negative connection end of the diode D1 is connected with the power switch circuit; one end of the capacitor C1 is connected with the negative connection end of the diode D1, and the other end of the capacitor C1 is grounded; the power supply switching circuit comprises a first connecting end, a second connecting end and a switch control end, wherein the first connecting end of the power supply switching circuit is connected with the negative connecting end of the diode D1, the second connecting end of the power supply switching circuit is connected with the second connecting end of the power supply branch circuit, and the switch control end of the power supply switching circuit is connected with the third connecting end of the power supply branch circuit.
In one embodiment, diode D1 includes a schottky diode.
In an embodiment, when the third connection terminal of the power switch circuit inputs a high level, the first connection terminal and the second connection terminal are turned on.
In one embodiment, the larger the capacitance value of the capacitor C1, the longer the delay time for the second connection terminal of the power switch circuit to power off when the input terminal of the LDO power circuit is powered off.
In one embodiment, the power sequence control circuit comprises an LDO power circuit, a diode D2, a capacitor C2, and a power sequence control chip;
the input end of the LDO power circuit is connected with the first connecting end of the power sequence control circuit, and the output end of the LDO power circuit is connected with the positive connecting end of a diode D2; the negative connection end of the diode D2 is connected with the power supply sequence control chip; one end of the capacitor C2 is connected with the negative connection end of the diode D2, and the other end of the capacitor C2 is grounded; the power supply sequence control chip comprises a power supply input end, an enabling signal connecting end and at least one switch control signal output end, the power supply input end of the power supply sequence control chip is connected with the negative connecting end of the diode D2, the enabling signal connecting end of the power supply sequence control chip is connected with the enabling signal input end of the power supply sequence control circuit, and each switch control signal output end of the power supply sequence control chip is respectively connected with one of the sequence control signal output ends of the power supply sequence control circuit.
In one embodiment, the power sequence control chip model includes LM 3881.
In one embodiment, the power sequence control circuit further includes a capacitor C3, one end of the capacitor C3 is connected to the power sequence control chip, and the other end is grounded; and the capacitor C3 is used for controlling the power supply sequence control chip to sequentially send the delay time of the switch control signals to the power supply branch circuits according to the preset sequence.
In one embodiment, the or circuit includes an or logic chip.
In one embodiment, the AND circuit includes an AND logic chip.
The power-on/power-off timing sequence control device according to the above embodiment includes a first power-on/power-off timing sequence control unit, a second power-on/power-off timing sequence control unit, a power supply monitoring circuit, an or circuit, and an and circuit. The power supply monitoring circuit is used for outputting a first state electric signal or a second state electric signal when the input voltage is higher than a first preset value or the input voltage is lower than a second preset value. The first power-on and power-off time sequence control unit and the second power-on and power-off time sequence control unit respectively comprise a power supply sequence control circuit and at least one power supply branch circuit, the power supply sequence control circuit responds to an enabling signal and sequentially sends a switch control signal to the power supply branch circuits according to a preset sequence, and the power supply branch circuits respond to the switch control signal and convert the power-on power supply into an output power supply to be output. The OR circuit and the AND circuit are used for outputting enable signals to the first power-up and power-down time sequence control unit and the second power-up and power-down time sequence control unit respectively. The power supply monitoring circuit is only used for controlling the output of the power-on and power-off instructions, so that the power-on and power-off time sequence control can be realized without programming devices.
Drawings
FIG. 1 is a schematic diagram of a circuit configuration of a power-on/power-off timing control apparatus according to an embodiment;
FIG. 2 is a schematic diagram of the circuit connections of the power branches in one embodiment;
FIG. 3 is a schematic diagram of the circuit connections of the power sequence control circuit in one embodiment;
FIG. 4 is a schematic diagram illustrating a power-up process of the power-up/power-down timing control apparatus according to an embodiment;
FIG. 5 is a schematic diagram illustrating a lower current flow of the power-on/power-off timing control apparatus according to an embodiment.
Detailed Description
The present invention will be described in further detail with reference to the following detailed description and accompanying drawings. Wherein like elements in different embodiments are numbered with like associated elements. In the following description, numerous details are set forth in order to provide a better understanding of the present application. However, those skilled in the art will readily recognize that some of the features may be omitted or replaced with other elements, materials, methods in different instances. In some instances, certain operations related to the present application have not been shown or described in detail in order to avoid obscuring the core of the present application from excessive description, and it is not necessary for those skilled in the art to describe these operations in detail, so that they may be fully understood from the description in the specification and the general knowledge in the art.
Furthermore, the features, operations, or characteristics described in the specification may be combined in any suitable manner to form various embodiments. Also, the various steps or actions in the method descriptions may be transposed or transposed in order, as will be apparent to one of ordinary skill in the art. Thus, the various sequences in the specification and drawings are for the purpose of describing certain embodiments only and are not intended to imply a required sequence unless otherwise indicated where such sequence must be followed.
The numbering of the components as such, e.g., "first", "second", etc., is used herein only to distinguish the objects as described, and does not have any sequential or technical meaning. The term "connected" and "coupled" when used in this application, unless otherwise indicated, includes both direct and indirect connections (couplings).
The general scheme for controlling the power-on and power-off timing comprises the following steps:
the first scheme is as follows: the power good output of the upper power supply chip is connected with the enable input pin of the lower power supply, and when the upper power supply is successfully electrified, the power good outputs high level to enable the lower power supply. This method does not control the power-down sequence nor the power-up delay time between the power sources.
Scheme II: the control signal is used for controlling the enabling of a plurality of power supplies, and different delay circuits are used for enabling each power supply, so that the power-on and power-off time sequence control is realized. The method can only realize that the power supply which is powered on first is powered off first when powered off, and cannot realize the power off after powered on first.
The third scheme is as follows: the power-on and power-off sequence control chip is used and generally has one enable pin and a plurality of power-on and power-off control signals. When the enable pin is changed from low level to high level, the power-on and power-off control signals of the chip can output high level in sequence, and the time delay between each control signal can be accurately controlled. When the enable pin is changed from high level to low level, the power-on and power-off control signals of the chip output low level in sequence. And the sequence is opposite to the power-on sequence, namely, the control signal with high level is firstly output during power-on, and the control signal with low level is finally output during power-off, so that power-on before power-off is realized. This solution also requires a battery or other backup power source, otherwise the power down sequence cannot be guaranteed. Meanwhile, the number of controllable power supply circuits of one power supply sequence control chip is limited and cannot be expanded.
There are various schemes for implementing the power-up and power-down sequence, such as replacing the delay circuit in scheme two and the power-up and power-down sequence control chip in scheme three with a CPLD, and the like, and these schemes cannot implement accurate control of power-up and power-down sequence and delay without a battery or a standby power supply.
In the embodiment of the present application, the power-on/power-off timing control apparatus includes a first power-on/power-off timing control unit, a second power-on/power-off timing control unit, a power supply monitoring circuit, an or circuit, and an and circuit. The power supply monitoring circuit is used for outputting a first state electric signal or a second state electric signal when the input voltage is higher than a first preset value or lower than a second preset value, wherein the first preset value is larger than the second preset value. The first power-on and power-off time sequence control unit and the second power-on and power-off time sequence control unit respectively comprise a power supply sequence control circuit and at least one power supply branch circuit, the power supply sequence control circuit responds to an enabling signal and sequentially sends a switch control signal to the power supply branch circuits according to a preset sequence, and the power supply branch circuits respond to the switch control signal and convert the power-on power supply into an output power supply to be output. The OR circuit and the AND circuit are used for outputting enable signals to the first power-up and power-down time sequence control unit and the second power-up and power-down time sequence control unit respectively. The power supply monitoring circuit is only used for controlling the output of the power-on and power-off instructions, so that the power-on and power-off time sequence control can be realized without programming devices.
The first embodiment is as follows:
referring to fig. 1, a schematic circuit structure of an embodiment of a power-up/power-down timing control device is shown, where the power-up/power-down timing control device includes a power input terminal, at least two sets of power-up output terminals, a first power-up/power-down timing control unit 1, a second power-up/power-down timing control unit 2, a power monitoring circuit 3, an or circuit 4, and an and circuit 5. The power supply input end is used as an input end of a power-on power supply VCC-IN. The power supply monitoring circuit 3 comprises a first connecting end and a second connecting end, the first connecting end of the power supply monitoring circuit 3 is connected with the power supply input end, and the second connecting end of the power supply monitoring circuit 3 is respectively connected with the OR circuit 4 and the AND circuit 5. The power supply monitoring circuit 3 is used for outputting a first state electric signal through the second connecting end of the power supply monitoring circuit 3 when the power supply input end has electric input, and outputting a second state electric signal through the second connecting end of the power supply monitoring circuit 3 when the power supply input end has no electric input. The first power-on/power-off timing control unit 1 includes a power supply sequence control circuit 10 and at least one power supply branch 11, and the second power-on/power-off timing control unit 2 includes a power supply sequence control circuit 20 and at least one power supply branch 21. The power sequence control circuit 10 includes a first connection terminal, an enable signal input terminal, and sequence control signal output terminals having the same number as the power branches 11. The first connection terminal of the power sequence control circuit 10 is connected to the power input terminal. Each sequential control signal output of the power sequence control circuit 10 is connected to one power branch 11. The enable signal input terminal of the power sequence control circuit 10 is used for inputting an enable signal. The power sequence control circuit 10 is configured to sequentially send the switch control signals to the power branches 11 through the sequence control signal output end according to a preset sequence in response to the enable signal. The power branch 11 includes a first connection end, a second connection end and a third connection end, the first connection end of the power branch 11 is connected with the first connection end of the power sequence control circuit 10, and the second connection end of the power branch 11 is connected with a sequence control signal output end of the power sequence control circuit 10. The third connecting end of the power supply branch 11 of the first power-up and power-down timing sequence control unit 1 is used for being connected with one group of power-up output terminals Vccm, and the third connecting end of the power supply branch 21 of the second power-up and power-down timing sequence control unit 2 is used for being connected with the other group of power-up output terminals Vccn. The power supply branch 11 is configured to convert the power-on power supply into an output power supply in response to the switch control signal, and output the output power supply through a third connection end of the power supply branch 11. The or circuit 4 comprises a first connecting end, a second connecting end and a third connecting end, the first connecting end of the or circuit 4 is connected with the second connecting end of the power supply monitoring circuit 3, the second connecting end of the or circuit 4 is connected with the last sequential control signal output end of the power supply sequential control circuit of the second power-up and power-down sequential control unit 2, and the third connecting end of the or circuit 4 is connected with the enable signal input end of the power supply sequential control circuit 10 of the first power-up and power-down sequential control unit 1. The or circuit 4 is configured to output an enable signal to the power sequence control circuit 10 of the first power-up/power-down timing control unit 1 when at least one of the first connection terminal and the second connection terminal of the or circuit 4 inputs a high-level electrical signal. The fetch and join circuit 5 comprises a first connecting end, a second connecting end and a third connecting end, the first connecting end of the fetch and join circuit 5 is connected with the second connecting end of the power monitoring circuit 3, the second connecting end of the fetch and join circuit 5 is connected with the end-position sequence control signal output end of the power sequence control circuit 10 of the first power-up and power-down time sequence control unit 1, the third connecting end of the fetch and join circuit 5 is connected with the enable signal input end of the power sequence control circuit of the second power-up and power-down time sequence control unit 2, and the fetch and join circuit 5 is used for outputting an enable signal to the power sequence control circuit 20 of the second power-up and power-down time sequence control unit 2 when the first connecting end and the second connecting end of the fetch and join circuit 5 input high and low electric signals.
Referring to fig. 2, a schematic diagram of a circuit connection of a power branch in an embodiment is shown, in which the power branch includes an LDO power circuit, a diode D1, a capacitor C1, and a power switch circuit. The input end of the LDO power supply circuit is connected with the first connecting end of the power branch circuit, and the output end of the LDO power supply circuit is connected with the positive connecting end of the diode D1. The negative connection end of the diode D1 is connected with the power switch circuit, one end of the capacitor C1 is connected with the negative connection end of the diode D1, and the other end of the capacitor C1 is grounded. The power supply switch circuit comprises a first connecting end, a second connecting end and a switch control end, wherein the first connecting end of the power supply switch circuit is connected with the negative connecting end of the diode D1, the second connecting end of the power supply switch circuit is connected with the second connecting end of the power supply branch circuit, and the switch control end of the power supply switch circuit is connected with the third connecting end of the power supply branch circuit. In one embodiment, diode D1 includes a schottky diode. In an embodiment, when the third connection terminal of the power switch circuit inputs a high level, the first connection terminal and the second connection terminal are turned on. In one embodiment, the larger the capacitance of the capacitor C1, the longer the delay time for the second connection terminal of the power switch circuit to power off when the input terminal of the LDO power circuit is powered off.
Referring to fig. 3, a schematic diagram of a circuit connection of a power sequence control circuit in an embodiment is shown, in which the power sequence control circuit includes an LDO power circuit, a diode D2, a capacitor C2, and a power sequence control chip. The input end of the LDO power supply circuit is connected with the first connecting end of the power sequence control circuit, and the output end of the LDO power supply circuit is connected with the positive connecting end of the diode D2. The negative connection end of the diode D2 is connected with the power supply sequence control chip. One end of the capacitor C2 is connected to the negative terminal of the diode D2, and the other end of the capacitor C2 is grounded. The power supply sequence control chip comprises a power supply input end, an enabling signal connecting end and at least one switch control signal output end, the power supply input end of the power supply sequence control chip is connected with the negative connecting end of the diode D2, the enabling signal connecting end of the power supply sequence control chip is connected with the enabling signal input end of the power supply sequence control circuit, and the switch control signal output end of each power supply sequence control chip is respectively connected with the sequence control signal output end of one power supply sequence control circuit. In one embodiment, the power sequence control chip model includes LM 3881. In one embodiment, the power sequence control circuit further includes a capacitor C3, one end of the capacitor C3 is connected to the power sequence control chip, and the other end is grounded. And the capacitor C3 is used for controlling the time delay of the power supply sequence control chip for sequentially sending the switch control signals to the power supply branch circuits according to the preset sequence. In one embodiment, the or circuit includes an or logic chip, and the and circuit includes an and logic chip.
As shown in fig. 1, the power-up and power-down timing control apparatus has m + n power supply branches, that is, m + n power supply branches required to control power-up and power-down timing control, where m and n are integers greater than 1. Referring to fig. 4, a schematic diagram of a power-up flow of the power-up and power-down timing control apparatus in an embodiment includes:
The power supply monitoring circuit monitors the voltage value of the power-on power supply.
When the voltage value of the power-on power supply is higher than the threshold value, the power supply monitoring circuit outputs high level to the OR circuit and the AND circuit.
In step 130, the or circuit outputs a high level.
The OR circuit acquires a high level signal output by the power supply monitoring circuit and also outputs the high level signal to an enabling control end of a power supply sequence control circuit of the first power-on and power-off time sequence control unit.
In step 140, the first power-on/power-off timing control unit outputs in the order of Sm, …, S2, S1.
The power sequence control circuit of the first power-up and power-down timing control unit sequentially outputs high levels to the power branches m, …, the power branch 2, and the power branch 1 in the order of Sm, …, S2, and S1 in response to the high level signal.
The sequence of step 150, VCCm, …, VCC2, VCC1 turns on power.
The power supply branches m and …, the power supply branch 2 and the power supply branch 1 of the first power-up and power-down sequence control unit are sequentially conducted to work, and sequentially output power supplies VCCm and …, a power supply VCC2 and a power supply VCC 1.
In step 160, the AND circuit outputs a high level.
And a power supply branch circuit 1 of the first power-on and power-off time sequence control unit outputs a high-level signal to an AND circuit, two input ends of the AND circuit are both high levels, and the high-level signal is output to a second power-on and power-off time sequence control unit.
In step 170, the second power-up/down timing control unit outputs in the order of Sn, …, S2, S1.
The power sequence control circuit of the second power-up and power-down timing control unit outputs high levels to the power branches n, …, power branch 2, and power branch 1 at a time in the order of Sn, …, S2, and S1 in response to the high level signal.
The sequence of step 180, VCCn, …, VCC2, VCC1 turns on power.
The power supply branches n and …, the power supply branch 2 and the power supply branch 1 of the second power-on and power-off timing sequence control unit are sequentially conducted to work, and power supplies VCCn and …, a power supply VCC2 and a power supply VCC1 are sequentially output.
When the power supply is powered on, the power supply is connected with VCC-IN voltage, the power supply monitoring circuit monitors that the VCC-IN voltage value is higher than a threshold value, and outputs high level voltage to an OR gate circuit and an AND gate circuit, and the OR gate circuit outputs high level voltage to an enabling pin of a power supply sequence control circuit 10 of the first power supply sequence control unit. The power supply sequence control circuit 10 sequentially outputs high level signals (i.e., Sm → … → S2 → S1) from Sm so that the power supplies VCCm, …, VCC2, VCC1 are sequentially turned on. Meanwhile, the S1 output of the power sequence control circuit 10 is connected to the and circuit, and both inputs of the and circuit are at high level, so that the and circuit outputs high level to the enable pin of the power sequence control circuit 20 of the second up-down electrical sequence control circuit, and the power sequence control circuit 20 sequentially outputs high level signals (i.e. Sn → … → S2 → S1) from Sn, so that the power VCCn, …, VCC2, and VCC1 are sequentially turned on. The time delay between S1, S2, …, Sn can be adjusted by the capacitor C3 of the power sequence control circuit 20. This realizes the control of the power-on timing.
Referring to fig. 5, a schematic diagram of a lower current flow of an embodiment of a power-on/power-off timing control apparatus includes:
The power supply monitoring circuit monitors the voltage value of the power-on power supply.
In step 220, the power supply monitoring circuit outputs a low level.
When the voltage value of the power supply is lower than the threshold value, the power supply monitoring circuit outputs low level to the OR circuit and the AND circuit.
In step 230, the AND circuit outputs a low level.
The AND circuit acquires a low level signal output by the power supply monitoring circuit and also outputs the low level signal to an enabling control end of a power supply sequence control circuit of the second power-on and power-off time sequence control unit.
In step 240, the second power-up/down timing control unit outputs a low level according to S1, S2, …, Sn.
The power sequence control circuit of the second power-up and power-down timing control unit sequentially outputs low levels to the power branch 1, the power branch 2, the power branch …, and the power branch n in the order of S1, S2, …, and Sn in response to the high level signal.
The power supply branch 1, the power supply branches 2 and … and the power supply branch n of the second power-on and power-off time sequence control unit are sequentially turned off to stop working, and the output power supply VCC1, the power supplies VCC2 and … and the power supply VCCn are sequentially stopped.
In step 260, the OR circuit outputs a low level.
And a power supply branch 2 of the second power-on and power-off time sequence control unit outputs a low-level signal to an OR circuit, two input ends of the OR circuit are both at low levels, and the low-level signal is output to the first power-on and power-off time sequence control unit.
In step 270, the first power-up/down timing control unit outputs a low level according to S1, S2, …, Sm.
The power sequence control circuit of the first power-up and power-down timing control unit sequentially outputs the low level to the power branch 1, the power branch 2, …, and the power branch m in the order of S1, S2, …, Sm in response to the low level signal.
The power supply branch 1, the power supply branches 2 and … and the power supply branch m of the first power-up and power-down sequence control unit are sequentially turned off to stop working, and the power supply of the output power supply VCC1, the power supplies VCC2 and … and the power supply VCCm are sequentially stopped.
When the power is off, the VCC-IN voltage accessed by the power-on power supply is firstly cut off, the power supply monitoring circuit monitors that the VCC-IN voltage is lower than the threshold value, low level voltage is output to an OR gate circuit and an AND gate circuit, and the AND gate circuit outputs low level to an enabling pin of a power supply sequence control circuit 20 of the second power-on and power-off time sequence control unit. The power supply sequence control circuit 20 sequentially outputs low level signals (i.e., S1 → S2 → … → Sm) from S1, so that the power supplies VCC1, VCC2, …, VCCn are sequentially turned off. Meanwhile, the Sm output of the power sequence control circuit 20 is connected to the or gate circuit, and after the Sm outputs a low level, since both inputs of the or gate circuit are at a low level at this time, the or gate circuit outputs a low level to the enable pin of the power sequence control circuit 10, and the power sequence control circuit 10 sequentially outputs low level signals (i.e., S1 → S2 → … → Sm) from S1, so that the power supplies VCC1, VCC2, …, and VCCm are sequentially turned off. When the power is cut off, the voltage of each power supply branch needs to be maintained within a normal working voltage range, otherwise, the timing of the power cut-off becomes meaningless. Schottky diode D1 and electric capacity C1 of power supply branch road are the voltage that is used for maintaining power supply branch road when cutting off the electricity, and schottky diode D1 prevents that the electric current of power supply branch road's output power from flowing backward to power supply branch road's LDO power supply circuit department, the voltage hold time of the output power of extension power supply branch road, and electric capacity C1 is used for the energy storage, and the power supply voltage is maintained to the load current that is provided by electric capacity C1 when cutting off the electricity, and electric capacity is bigger, and the energy storage is more, and the time of maintaining power supply voltage is more for a long time. When the output voltage of the LDO power supply circuit is reduced to be close to the output voltage of the LDO power supply circuit, the output voltage of the LDO power supply circuit is reduced along with the reduction of the input voltage. When the output voltage of the LDO power supply circuit is reduced to a level where the schottky diode D1 cannot be turned on, the schottky diode D1 enters a cut-off state, and prevents current from flowing back to the output terminal of the LDO. The voltage on the capacitor C1 can be maintained for a longer time because of the reduced back-sink current. And a capacitor with a large enough capacitance value is arranged, so that the voltage maintaining time is longer than the power-off delay time, and the function of the power-off time sequence can be realized. In the embodiment, the power supply monitoring circuit is used for outputting the power-on and power-off instruction, no additional programming device is needed, and even under the condition of no battery or standby power supply, the accurate control of the power-on and power-off time sequence can be realized, including the accurate time delay of each time sequence time, and the number of power supply branch circuit output power supplies controlled by the power-on and power-off time sequence can be conveniently expanded by cascading a plurality of power supply sequence control chips.
In the embodiment of the present application, the power-on/power-off timing control apparatus includes a first power-on/power-off timing control unit, a second power-on/power-off timing control unit, a power supply monitoring circuit, an or circuit, and an and circuit. The power supply monitoring circuit is used for outputting a first state electric signal or a second state electric signal when the input voltage of the power supply is higher than a first preset value or the input voltage is lower than a second preset value. The first power-on and power-off time sequence control unit and the second power-on and power-off time sequence control unit respectively comprise a power supply sequence control circuit and at least one power supply branch circuit, the power supply sequence control circuit responds to an enabling signal and sequentially sends a switch control signal to the power supply branch circuits according to a preset sequence, and the power supply branch circuits respond to the switch control signal and convert the power-on power supply into an output power supply to be output. The OR circuit and the AND circuit are used for outputting enable signals to the first power-up and power-down time sequence control unit and the second power-up and power-down time sequence control unit respectively. The power supply monitoring circuit is only used for controlling the output of the power-on and power-off instructions, so that the power-on and power-off time sequence control can be realized without programming devices.
The present invention has been described in terms of specific examples, which are provided to aid understanding of the invention and are not intended to be limiting. For a person skilled in the art to which the invention pertains, several simple deductions, modifications or substitutions may be made according to the idea of the invention.
Claims (10)
1. A power-on and power-off time sequence control device is characterized by comprising a power supply input end, at least two groups of power-on and power-off output ends, a first power-on and power-off time sequence control unit, a second power-on and power-off time sequence control unit, a power supply monitoring circuit, an OR circuit and an AND circuit;
the power supply input end is used as the input end of a power-on power supply;
the power supply monitoring circuit comprises a first connecting end and a second connecting end, the first connecting end of the power supply monitoring circuit is connected with the power supply input end, and the second connecting end of the power supply monitoring circuit is respectively connected with the OR circuit and the AND circuit; the power supply monitoring circuit is used for outputting a first state electric signal through a second connecting end of the power supply monitoring circuit when the input voltage of the power supply input end is higher than a first preset value, and outputting a second state electric signal through the second connecting end of the power supply monitoring circuit when the input voltage of the power supply input end is lower than a second preset value; the first preset value is larger than the second preset value;
the first power-up and power-down time sequence control unit and the second power-up and power-down time sequence control unit comprise a power supply sequence control circuit and at least one power supply branch circuit; the power supply sequence control circuit comprises a first connecting end, an enabling signal input end and sequence control signal output ends, wherein the number of the sequence control signal output ends is the same as that of the power supply branches; the first connecting end of the power supply sequence control circuit is connected with the power supply input end; each sequential control signal output end of the power sequential control circuit is connected with one power branch; the enable signal input end of the power supply sequence control circuit is used for inputting an enable signal; the power supply sequence control circuit is used for responding to the enabling signal and sequentially sending a switch control signal to the power supply branch circuit according to a preset sequence through the sequence control signal output end; the power supply branch circuit comprises a first connecting end, a second connecting end and a third connecting end, wherein the first connecting end of the power supply branch circuit is connected with the first connecting end of the power supply sequence control circuit, and the second connecting end of the power supply branch circuit is connected with one sequence control signal output end of the power supply sequence control circuit; the third connecting end of the power supply branch of the first power-up and power-down time sequence control unit is used for being connected with one group of power-up output ends, and the third connecting end of the power supply branch of the second power-up and power-down time sequence control unit is used for being connected with the other group of power-up output ends; the power supply branch circuit is used for responding to the switch control signal to convert the power-on power supply into an output power supply and outputting the output power supply through a third connecting end of the power supply branch circuit;
the OR circuit comprises a first connecting end, a second connecting end and a third connecting end; the first connecting end of the OR circuit is connected with the second connecting end of the power supply monitoring circuit, and the second connecting end of the OR circuit is connected with the last order control signal output end of the power supply order control circuit of the second power-up and power-down time sequence control unit; the third connecting end of the OR circuit is connected with an enabling signal input end of a power supply sequence control circuit of the first power-on and power-off time sequence control unit; the OR circuit is used for outputting the enable signal to a power sequence control circuit of the first power-up and power-down sequence control unit when at least one of a first connecting end and a second connecting end of the OR circuit inputs a high-level electric signal;
the fetch and connection circuit comprises a first connection end, a second connection end and a third connection end; the first connecting end of the taking and connecting circuit is connected with the second connecting end of the power supply monitoring circuit, and the second connecting end of the taking and connecting circuit is connected with the last order control signal output end of the power supply order control circuit of the first power-up and power-down time sequence control unit; the third connecting end of the taking and connecting circuit is connected with an enabling signal input end of a power supply sequence control circuit of the second power-on and power-off time sequence control unit; the AND circuit is used for outputting the enable signal to the power supply sequence control circuit of the second power-up and power-down sequence control unit when the first connecting end and the second connecting end of the AND circuit input high-level electric signals.
2. The power-up/down timing control apparatus of claim 1, wherein the power branch comprises an LDO power circuit, a diode D1, a capacitor C1, and a power switch circuit;
the input end of the LDO power circuit is connected with the first connecting end of the power branch circuit, and the output end of the LDO power circuit is connected with the positive connecting end of a diode D1; the negative connection end of the diode D1 is connected with the power switch circuit; one end of the capacitor C1 is connected with the negative connection end of the diode D1, and the other end of the capacitor C1 is grounded; the power supply switching circuit comprises a first connecting end, a second connecting end and a switch control end, wherein the first connecting end of the power supply switching circuit is connected with the negative connecting end of the diode D1, the second connecting end of the power supply switching circuit is connected with the second connecting end of the power supply branch circuit, and the switch control end of the power supply switching circuit is connected with the third connecting end of the power supply branch circuit.
3. The power-on/power-off timing control device as claimed in claim 2, wherein the diode D1 is a schottky diode.
4. The power-up/down timing control apparatus according to claim 2, wherein the first connection terminal and the second connection terminal are turned on when the third connection terminal of the power switching circuit is inputted with a high level.
5. The power-up and power-down timing control apparatus according to claim 2, wherein the larger the capacitance value of the capacitor C1 is, the longer the delay time of the second connection terminal output power-off of the power switch circuit when the input terminal of the LDO power circuit is powered off.
6. The power-up and power-down timing control apparatus of claim 1, wherein the power sequence control circuit comprises an LDO power circuit, a diode D2, a capacitor C2, and a power sequence control chip;
the input end of the LDO power circuit is connected with the first connecting end of the power sequence control circuit, and the output end of the LDO power circuit is connected with the positive connecting end of a diode D2; the negative connection end of the diode D2 is connected with the power supply sequence control chip; one end of the capacitor C2 is connected with the negative connection end of the diode D2, and the other end of the capacitor C2 is grounded; the power supply sequence control chip comprises a power supply input end, an enabling signal connecting end and at least one switch control signal output end, the power supply input end of the power supply sequence control chip is connected with the negative connecting end of the diode D2, the enabling signal connecting end of the power supply sequence control chip is connected with the enabling signal input end of the power supply sequence control circuit, and each switch control signal output end of the power supply sequence control chip is respectively connected with one of the sequence control signal output ends of the power supply sequence control circuit.
7. The power-on and power-off timing control device according to claim 6, wherein the power sequence control chip is of a type LM 3881.
8. The power-on/power-off timing control apparatus of claim 6, wherein the power sequence control circuit further comprises a capacitor C3, one end of the capacitor C3 is connected to the power sequence control chip, and the other end is grounded; and the capacitor C3 is used for controlling the power supply sequence control chip to sequentially send the delay time of the switch control signals to the power supply branch circuits according to the preset sequence.
9. The power-on and power-off timing control device according to claim 1, wherein the or circuit includes an or logic chip.
10. The power-on/power-off timing control device according to claim 1, wherein the and circuit includes an and logic chip.
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| CN113721508B (en) * | 2021-08-24 | 2024-02-27 | 杭州迪普科技股份有限公司 | Power-on and power-off time sequence control device and method |
| CN116501156B (en) * | 2023-05-19 | 2024-01-30 | 亿咖通(湖北)技术有限公司 | Power supply time sequence control method, device, equipment and storage medium |
| CN116700106B (en) * | 2023-06-30 | 2024-04-19 | 合肥申威睿思信息科技有限公司 | Power-on and power-off time sequence control circuit and method |
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