WO2019129134A1

WO2019129134A1 - Power-down timing control circuit, power supply system and power-down timing control method

Info

Publication number: WO2019129134A1
Application number: PCT/CN2018/124304
Authority: WO
Inventors: 张锁成
Original assignee: 中兴通讯股份有限公司
Priority date: 2017-12-29
Filing date: 2018-12-27
Publication date: 2019-07-04
Also published as: CN109992030A; CN109992030B

Abstract

A power-down timing control circuit, a power supply system and a power-down timing control method, the power-down timing control circuit comprising a first voltage source (V1), a second voltage source (V2) and a voltage reference module (T1) connected between the first voltage source (V1) and the second voltage source (V2), wherein the first voltage source (V1) is configured to provide a first voltage; the second voltage source (V2) is configured to provide a second voltage; and the voltage reference module (T1) is configured to automatically adjust the power-down speed of one of the first voltage and the second voltage when a power-down voltage difference between the first voltage and the second voltage is greater than a preset first power-down voltage difference, so that the power-down voltage difference between the first voltage and the second voltage is less than or equal to a preset second power-down voltage difference, wherein the preset second power-down voltage difference is greater than the preset first power-down voltage difference.

Description

Power-down timing control circuit, power supply system, and power-down timing control method

Technical field

The present disclosure relates to the field of electronic technologies, and in particular, to a power-down timing control circuit, a power supply system, and a power-down timing control method.

Background technique

Currently, mainstream integrated chips such as a CPU (Central Processing Unit), an FPGA (Field Programmable Gate Array), and the like are usually simultaneously applied with multiple power supply voltages. For example, multiple power supply voltages can be of different types. The supply voltage may include an IO (Input/Output) voltage, a core voltage, an analog voltage, a digital voltage, and the like. In the process of managing the multi-channel power supply voltage of the chip, there are strict requirements on the power-down timing and the lower voltage difference of each power supply voltage, which needs to ensure these requirements in the power supply design of the periphery of the chip, otherwise it is easy to appear Damage to the chip.

Public content

Embodiments of the present disclosure provide a power down timing control circuit including a first voltage source, a second voltage source, and a voltage reference module connected between the first voltage source and the second voltage source, the A voltage source is configured to provide a first voltage, the second voltage source is configured to provide a second voltage, and the voltage reference module is configured to be a lower voltage between the first voltage source and the second voltage source When the difference is greater than the first preset voltage difference, the power-off speed of one of the first voltage source and the second voltage source is automatically adjusted, such that the first voltage source and the second voltage source The lower voltage difference is less than or equal to the second preset lower voltage difference, wherein the second preset lower voltage difference is greater than the first preset lower voltage difference.

Embodiments of the present disclosure also provide a power supply system including a power down timing control circuit as described above.

Embodiments of the present disclosure also provide a power-down timing control method including: monitoring a lower voltage difference between a first voltage source providing a first voltage and a second voltage source providing a second voltage; comparing the first voltage a lower voltage difference between the source and the second voltage source and a first predetermined lower voltage difference; and a lower voltage difference between the first voltage source and the second voltage source being greater than the first pre- Setting a voltage difference, automatically adjusting a power-off speed of one of the first voltage source and the second voltage source, such that a lower voltage difference between the first voltage source and the second voltage source The voltage difference is less than or equal to the second preset voltage, wherein the second preset voltage difference is greater than the first preset voltage difference.

DRAWINGS

1 is a block diagram showing the structure of a power-down timing control circuit of an embodiment of the present disclosure;

2 is a schematic diagram showing power supply to an integrated chip by a power-down timing control circuit of an embodiment of the present disclosure;

3 is a flow chart showing a power-down timing control method of an embodiment of the present disclosure;

4 shows a kind of lower voltage difference between the first voltage source V1 and the second voltage source V2 when the first voltage source V1 that supplies the first voltage and the second voltage source V2 that supplies the second voltage are simultaneously powered down. Schematic diagram of the ideal state;

FIG. 5 is a diagram showing an example of a lower voltage difference between a first voltage source V1 and a second voltage source V2 implemented by a power-down timing control circuit of an embodiment of the present disclosure;

FIG. 6 is a diagram showing another example of a lower voltage difference between the first voltage source V1 and the second voltage source V2 implemented by the power-down timing control circuit of the embodiment of the present disclosure.

Detailed ways

In order to make the technical solutions and the beneficial effects of the present disclosure more clear and clear, the technical solutions of the present disclosure will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely used to explain the technical solutions of the present disclosure, and are not intended to limit the technical solutions of the present disclosure.

FIG. 1 is a block diagram showing the structure of a power-down timing control circuit of an embodiment of the present disclosure. 2 is a diagram showing power supply to an integrated chip by a power-down timing control circuit of an embodiment of the present disclosure.

As shown in FIGS. 1 and 2, the power-down timing control circuit of the embodiment of the present disclosure includes a first voltage source V1, a second voltage source V2, a voltage dividing circuit, and a voltage reference module T1.

The first voltage source V1 is configured to provide a first voltage, and the second voltage source V2 is configured to provide a second voltage, the first voltage and the second voltage being used to power the integrated chip.

The voltage dividing circuit may include a first resistor R1, a second resistor R2, and a third resistor R3 connected in series, and an end of the first resistor R1 not connected to the second resistor R2 and the first voltage source V1 is connected, and one end of the third resistor R3 not connected to the second resistor R2 is connected to the second voltage source V2, that is, the first resistor R1, the second resistor R2 and the third resistor R3 connected in series Connected between the first voltage source V1 and the second voltage source V2.

The cathode CA of the voltage reference module T1 is connected to a connection point between the first resistor R1 and the second resistor R2, and is connected to the first voltage source V1 through the first resistor R1. The reference terminal Vref of the voltage reference module T1 is connected to a connection point between the second resistor R2 and the third resistor R3, and is connected to the second voltage source V2 through the third resistor R3. The anode AN of the voltage reference module T1 is connected to the second voltage source V2.

In this embodiment, during the power-on of the voltage reference module T1, the reference terminal Vref of the voltage reference module T1 can maintain a reference voltage of a preset voltage value, which is applied to the cathode CA of the voltage reference module T1. When the voltage is higher than the reference voltage maintained by the reference terminal Vref of the voltage reference module T1, the voltage reference module T1 starts to operate, for example, the level of the anode AN of the voltage reference module T1 changes from a high level. Is low. The voltage reference module T1 can be implemented, for example, by a chip TL431 or a similar voltage stabilizing circuit and/or chip.

In this embodiment, when the voltage reference module T1 starts to operate, the current flowing through the first resistor R1 may be greater than 1 mA.

In some embodiments, the power-down timing control circuit of the embodiment of the present disclosure may further include a power switch tube Q1, the first end of the power switch tube Q1 being connected to the cathode CA of the voltage reference module T1, the power The second end of the switch tube Q1 is connected to the first voltage source V1, and the third end of the power switch tube Q1 is connected to the second voltage source V2.

As an example, the power switch tube Q1 may be a PNP transistor, the first end of the power switch tube Q1 is the base of the PNP transistor, and the second end of the power switch tube Q1 is the launch of the PNP transistor. The third end of the power switch tube Q1 is the collector of the PNP transistor.

In this embodiment, the power switch tube Q1 can limit the current flowing into the voltage reference module T1 to reduce the loss of the voltage reference module T1 and ensure the voltage regulation accuracy of the voltage reference module T1.

In some embodiments, the power-down timing control circuit of the embodiment of the present disclosure may further include a fourth resistor R4, the second end of the power switch tube Q1 passes the fourth resistor R4 and the first voltage source V1 connection.

In this embodiment, the fourth resistor R4 and the power switch tube Q1 can limit the current flowing into the voltage reference module T1 to reduce the loss of the voltage reference module T1, and ensure the voltage regulation accuracy of the voltage reference module T1. .

In some embodiments, the power-down timing control circuit of the embodiment of the present disclosure may further include a fifth resistor R5, one end of the fifth resistor R5 is connected to the first voltage source V1, and the fifth resistor is another One end is connected to a second end of the power switch tube Q1 and an end of the first resistor R1 that is not connected to the second resistor R2.

Each of the resistors in the embodiments of the present disclosure may include an adjustable resistor.

As an example, the operation of the power-down sequence control circuit of the embodiment of the present disclosure will be described below with reference to FIGS. 4 to 6.

Assuming that the integrated chip requires the first voltage source V1 and the second voltage source V2 to be simultaneously powered down, the lower voltage difference Vdelta between the first voltage source V1 and the second voltage source V2 cannot exceed 2V at the maximum.

In some embodiments, the initial voltage difference between the first voltage source V1 and the second voltage source V2 may be 1.5V, for example, the first voltage provided by the first voltage source V1 may be the second voltage provided by the second voltage source V2. The voltage is 1.5V, as shown in FIG. 4. If the power-off speed of the first voltage source V1 is greater than the power-off speed of the second voltage source V2, the lower voltage difference between the first voltage source V1 and the second voltage source V2 is Vdelta. Will not exceed the initial differential pressure of 1.5V, and will not exceed 2V.

However, if the first voltage source V1 and the second voltage source V2 are simultaneously powered down, the power-off speed of the second voltage source V2 is greater than the power-off speed of the first voltage source V1, then the first voltage source V1 and the second voltage The lower voltage difference between the sources V2 will gradually increase even if the initial voltage difference between the first voltage source V1 and the second voltage source V2 is less than 1.5V, between the first voltage source V1 and the second voltage source V2 The voltage difference can also exceed 2V.

FIG. 5 is a diagram showing an example of a lower voltage difference between a first voltage source V1 and a second voltage source V2 implemented by a power-down timing control circuit to which an embodiment of the present disclosure is applied.

With the power-down timing control circuit of the embodiment of the present disclosure, for example, the voltage (reference voltage) of the reference terminal Vref of the voltage reference module T1 may be 1.24 V, when the first voltage source V1 and the second voltage source V2 are under When the voltage difference is increased to 1.56V (ie, the first predetermined lower voltage difference), the voltage of the cathode CA of the voltage reference module T1 reaches 1.24V, if the lower voltage difference between the first voltage source V1 and the second voltage source V2 Continue to increase, the voltage reference module T1 starts to work, for example, the voltage of the anode AN of the voltage reference module T1 changes from a high level to a low level, the power switch tube Q1 is turned on, and the power-off speed of the first voltage source V1 is increased. When large and stable, the current flowing through the first resistor R1 is greater than 1 mA. At this time, the power-off speed of the first voltage source V1 follows the power-off speed of the second voltage source V2, and the power-down speed of the first voltage source V1 follows the lower voltage difference between the second voltage source V2 and can remain less than 2V (ie, , the second predetermined lower voltage difference).

In this example, when the lower voltage difference between the first voltage source V1 and the second voltage source V2 is greater than 1.56V, the voltage reference module T1 starts to operate because, in order to secure the first voltage source V1 and the second voltage source The lower voltage difference between V2 does not exceed 2V, and the power-off speed of the first voltage source V1 can be adjusted in advance to ensure that the lower voltage difference between the first voltage source V1 and the second voltage source V2 is not greater than 2V.

With the power-down timing control circuit of the embodiment of the present disclosure, if the power-down speed of the first voltage source V1 is greater than the power-down speed of the second voltage source V2, the lower voltage between the first voltage source V1 and the second voltage source V2 If the difference does not increase further, the voltage of the cathode CA of the voltage reference module T1 cannot reach and exceed the voltage (reference voltage) of the reference terminal Vref of the voltage reference module T1 by 1.24V. Therefore, the voltage reference module T1 does not operate, and the first voltage The lower voltage difference between the source V1 and the second voltage source V2 does not exceed the initial voltage difference between the first voltage source V1 and the second voltage source V2, that is, does not exceed 2V.

It should be understood that the initial differential pressure between the first voltage source V1 and the second voltage source V2 mentioned above, the first predetermined lower voltage difference, the second predetermined lower voltage difference, and the current flowing through the first resistor R1 when stable. The specific values are examples and can be adjusted as needed.

Moreover, according to the specific implementation of the voltage reference module T1, the reference voltage of the reference terminal Vref of the voltage reference module T1 may be different. In this case, for example, the start of the voltage reference module T1 can be controlled by adjusting the resistance of each resistor of the voltage dividing circuit. Working conditions.

The power-down timing control circuit of the embodiment of the present disclosure performs the lower voltage difference adjustment by the voltage reference module, has high precision, and can accurately protect the integrated chip. In addition, the power-down timing control circuit of the embodiment of the present disclosure is implemented by using a discrete device, which is easy to implement, low in cost, and small in occupation area.

Embodiments of the present disclosure also provide a power supply system including a power down timing control circuit of an embodiment of the present disclosure.

The power supply system of the embodiment of the present disclosure performs the lower voltage difference adjustment by the voltage reference module of the embodiment of the present disclosure, and has high precision, and can accurately protect the integrated chip. In addition, the power-down timing control circuit of the embodiment of the present disclosure is implemented by using a discrete device, which is easy to implement, low in cost, and small in occupation area.

As shown in FIG. 3, an embodiment of the present disclosure provides a power-down timing control method that can be implemented by a power-down timing control circuit of an embodiment of the present disclosure. The power-down timing control method may include the following steps S11 to S13.

S11. Monitor a lower voltage difference between the first voltage source that provides the first voltage and the second voltage source that provides the second voltage.

S12. Compare a lower voltage difference between the first voltage source and the second voltage source with a first preset lower voltage difference.

S13. Automatically adjusting the first voltage source and the second voltage when a lower voltage difference between the first voltage source and the second voltage source is greater than the first predetermined lower voltage difference. a power-off speed of one of the sources, such that a lower voltage difference between the first voltage source and the second voltage source is less than or equal to a second predetermined lower voltage difference, wherein the second predetermined lower voltage difference It is greater than the first preset voltage difference.

For example, the above step S11 can be implemented by a voltage dividing circuit. The above steps S12 and S13 can be implemented by a voltage reference module. For a description of the voltage dividing circuit and the voltage reference module, please refer to the description of the power-down timing control circuit of the embodiment of the present disclosure. I won't go into details here.

In this embodiment, the lower voltage difference between the first voltage source and the second voltage source ranges from 1.5V to 2V, and the first predetermined lower voltage difference may be greater than 1.5V and less than 2V. The second preset voltage difference is equal to 2V.

In some embodiments, the above step S13 may include: a lower voltage difference between the first voltage source and the second voltage source is greater than a first predetermined lower voltage difference and the second voltage source is powered off When the speed is greater than the power-off speed of the first voltage source, the power-off speed of the first voltage source is automatically adjusted such that the power-off speed of the first voltage source follows the power-off speed of the second voltage source.

The power-down timing control method of the embodiment of the present disclosure automatically performs the adjustment of the lower voltage difference with high precision, and can accurately protect the integrated chip.

Through the description of the above embodiments and implementations, those skilled in the art can clearly understand that the foregoing embodiments and the methods of the embodiments can be implemented by means of software plus a necessary general hardware platform, and of course, only by hardware. Realized, but in many cases the former is a better implementation. Based on such understanding, portions of the technical solution of the present disclosure that contribute substantially or to the prior art may be embodied in the form of a computer software product that can be stored in a storage medium (eg, ROM/RAM, diskette). And an optical disk, comprising a plurality of executable instructions for causing a terminal device (such as a mobile phone, a computer, a server, an air conditioner, or a network device, etc.) to perform the method described in the embodiments of the present disclosure.

The exemplary embodiments and implementations of the present disclosure have been described above with reference to the drawings, and are not intended to limit the scope of the disclosure. A person skilled in the art can implement the technical solutions of the present disclosure through various modifications without departing from the scope and spirit of the disclosure. For example, the features of the embodiments and the embodiments can be combined in any way to obtain new embodiments and implementations. the way. Any modifications, equivalent substitutions and improvements made by the technical idea of the present disclosure are considered to fall within the scope of the present disclosure.

Claims

A power-down timing control circuit includes a first voltage source, a second voltage source, and a voltage reference module connected between the first voltage source and the second voltage source, the first voltage source configured to provide a first voltage, the second voltage source configured to provide a second voltage,

The voltage reference module is configured to automatically adjust the first voltage source and the ground when a lower voltage difference between the first voltage source and the second voltage source is greater than a first predetermined lower voltage difference a power-off speed of one of the second voltage sources, such that a lower voltage difference between the first voltage source and the second voltage source is less than or equal to a second predetermined lower voltage difference, wherein the second pre- The voltage difference is set to be greater than the first preset voltage difference.
The power-down sequence control circuit of claim 1 further comprising:

a voltage dividing circuit connected between the first voltage source and the second voltage source, the voltage reference module configured to acquire the first voltage source and the second voltage source through the voltage dividing circuit Information about the difference in voltage between them.
The power-down timing control circuit of claim 2, wherein the voltage dividing circuit comprises a resistor in series.
The power-down timing control circuit according to any one of claims 1 to 3, wherein the voltage reference module comprises a voltage reference chip.
The power-down sequence control circuit according to claim 1, wherein the voltage dividing circuit comprises a first resistor, a second resistor, and a third resistor connected in series, and the first resistor is not connected to the second resistor One end of the third resistor is connected to the first voltage source, and one end of the third resistor not connected to the second resistor is connected to the second voltage source;

a cathode of the voltage reference module is connected to a connection point between the first resistor and the second resistor, and is connected to the first voltage source through the first resistor, and a reference end of the voltage reference module is connected And a connection point between the second resistor and the third resistor is connected to the second voltage source through the third resistor, and an anode of the voltage reference module is connected to the second voltage source.
The power-down sequence control circuit of claim 5, further comprising:

a power switch tube, a first end of the power switch tube is connected to a cathode of the voltage reference module, a second end of the power switch tube is connected to the first voltage source, and a third end of the power switch tube Connected to the second voltage source.
The power-down sequence control circuit according to claim 6, wherein the power is different when a lower voltage difference between the first voltage source and the second voltage source is greater than a first preset voltage difference The switch tube is turned on.
The power-down sequence control circuit according to claim 6, further comprising a fourth resistor, wherein the second end of the power switch is connected to the first voltage source through the fourth resistor.
The power-down sequence control circuit according to claim 6, wherein the power switch tube is a PNP transistor, the first end of the power switch tube is a base of the PNP transistor, and the second power switch tube The end is the emitter of the PNP transistor, and the third end of the power switch tube is the collector of the PNP transistor.
The power-down sequence control circuit according to claim 6, further comprising a fifth resistor, one end of the fifth resistor being connected to the first voltage source, and the other end of the fifth resistor being opposite to the power switch tube The second end is connected to an end of the first resistor that is not connected to the second resistor.
The power-down sequence control circuit according to claim 7, wherein when the power switch is turned on, a current flowing through the first resistor is greater than 1 mA.
A power supply system comprising the power-down timing control circuit according to any one of claims 1 to 11.
A power-down timing control method includes:

Monitoring a lower voltage difference between the first voltage source providing the first voltage and the second voltage source providing the second voltage;

Comparing a lower voltage difference between the first voltage source and the second voltage source with a first predetermined lower voltage difference;

Automatically adjusting the first voltage source and the second voltage source if a lower voltage difference between the first voltage source and the second voltage source is greater than the first predetermined lower voltage difference a power-off speed, such that a lower voltage difference between the first voltage source and the second voltage source is less than or equal to a second preset lower voltage difference, wherein the second predetermined lower voltage difference is greater than The first preset voltage difference is described.
The power-down timing control method according to claim 13, wherein a lower voltage difference between the first voltage source and the second voltage source is greater than a first predetermined lower voltage difference and the second voltage source is lower When the electric speed is greater than the power-off speed of the first voltage source, the power-off speed of the first voltage source is automatically adjusted such that the power-off speed of the first voltage source follows the power-off speed of the second voltage source.
The power-down timing control method according to claim 13, wherein a lower voltage difference between the first voltage source and the second voltage source ranges from 1.5V to 2V, and the first preset voltage difference is More than 1.5V and less than 2V, the second preset voltage difference is equal to 2V.