CN103296974A - Self-calibration buffer amplifier in voice coil motor driver and resistor trimming network - Google Patents
Self-calibration buffer amplifier in voice coil motor driver and resistor trimming network Download PDFInfo
- Publication number
- CN103296974A CN103296974A CN2013101520418A CN201310152041A CN103296974A CN 103296974 A CN103296974 A CN 103296974A CN 2013101520418 A CN2013101520418 A CN 2013101520418A CN 201310152041 A CN201310152041 A CN 201310152041A CN 103296974 A CN103296974 A CN 103296974A
- Authority
- CN
- China
- Prior art keywords
- connects
- drain electrode
- source electrode
- grid
- resistance
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Landscapes
- Amplifiers (AREA)
Abstract
The invention relates to a self-calibration buffer amplifier in a voice coil motor driver and a resistor trimming network, which are applied to a voice coil motor lens driver system. The self-calibration buffer amplifier and a self-calibration Class AB buffer amplifier ensure precision of a chip system; direct current power consumption is eliminated or greatly reduced; good system functions are achieved; the chip cost is saved; and with the adoption of the optimized resistor trimming network, the network disorder and network area are reduced, so that the purposes of improving performances of the network and lowering the chip cost are achieved.
Description
Technical field
The present invention relates to self calibration buffer amplifier and resistance finishing networking in a kind of voice coil motor driver, belong to the integrated circuit (IC) design field, be applied in the large scale integrated circuit, especially be applied in the chip system of high accuracy output current.
Background technology
Voice coil motor (Voice Coil Motor) is widely used in electronic product.Be widely used in recent years in smart mobile phone and the plane computer.
As shown in Figure 1, the camera gun position is driven by voice coil motor, and the lens location distance is proportional to the output current of voice coil motor driver.Behind the voice coil motor driver power connection, the electrification reset device is set up initial condition and the bias current/voltage of driver chip, and the signal that chip is started working is delivered to picture signal processing main chip (not in the drawings) by the I2C serial line interface.The picture signal processing main chip sends the instruction of driver output current by the I2C serial line interface to the voice coil motor driver chip, driver is received output current instruction back and by the 10bit Register 10-bit current mode digital-to-analog converter is inserted in this instruction, by this digital to analog converter digital signal is converted to analog signal and passes through resistance R
2Be converted to voltage signal.Buffer amplifier is converted to the voltage signal of node 11 required electric current and delivers to voice coil motor by efferent duct MN0 by the IOUT end by resistance R 1, finishes motor and drives process.Because buffer amplifier has input equivalence imbalance at random, causes between true output current and the desired output current and produces error, this error not only influences control precision, and can produce fixed current output at the zero output current status.Because the voice coil motor most time can be at the zero output current status, the output current of this state can increase the quiescent dissipation of voice coil motor driver, reduces battery service time, brings great inconvenience to application.
A kind of prior art commonly used is the equivalence input imbalance that reduces and eliminate buffer amplifier by self-calibration circuit, and its operation principle as shown in Figure 2.The positive input terminal 21 of buffer amplifier is received the voltage Vref that reference power supply produces, S2 switch opens by switch S 1 when driver powers on for the first time.The negative input end 22 of buffer amplifier forms the unit amplifying circuit by switch S 4, the auto zero comparator, and self calibration controller and oscillator are started working.The input of buffer amplifier is received corresponding auto zero comparator input terminal.The auto zero comparator can be differentiated misalignment signal below the 20uV by the method for auto zero.The self calibration controller progressively changes the calibration device of buffer amplifier under the control of clock, up to the voltage change polarity of auto zero comparator output terminal 26, finish self-calibration process.The self calibration controller ties down the calibration device signal.The input offset voltage of buffer amplifier will be smaller or equal to the resolution of auto zero comparator.Finish disposable self calibration rear drive device with S1, S4 opens, and simultaneously with S2, S3 and S5 connect, and chip is in normal operating conditions.Driver input offset voltage after the calibration will be eliminated or reduce greatly.Thereby reach the system applies requirement.
The position that voice coil motor driver (Lens Driver) provides linear output current to be used to control the voice coil motor camera lens, thus reach automatic focus (Auto Focus) effect.The photographic film position is proportional to the driver output current, and both are linear.High-gain amplifier is used for guaranteeing the good focusing effect.Because the variation amplifier of technology itself has input offset voltage, this offset voltage can be introduced the output offset current of a direct current, influences the precision of output current.The amplifier offset voltage can be introduced direct current when zero code simultaneously.In most cases voice coil motor driver is operated in zero code status, so the amplifier input offset voltage can increase power consumption of driver, thereby reduces the service time of battery power supply system.
Summary of the invention
Self calibration buffer amplifier in a kind of voice coil motor driver provided by the invention and resistance finishing networking is eliminated or has been reduced amplifier input imbalance greatly, has strengthened focusing effect, has prolonged system service time, and has reduced chip cost.
In order to achieve the above object, the invention provides a kind of high-gain self calibration buffer amplifier, this amplifier comprises pre-amplifying stage and the collapsible amplifying stage that circuit connects;
This pre-amplifying stage comprises current source I0, input to pipe MP0 and MP1, and resistance finishing networking;
Current source I0 connects input to the source electrode of pipe MP0 and MP1, the grid of MP0 connects input INM, the grid of MP1 connects input INP, the input IN at resistance finishing networking connects input to the drain electrode of pipe MP0 and MP1, the output OUT ground connection VSS at resistance finishing networking, the Vreg end at resistance finishing networking connects power vd D.
Described resistance finishing networking comprises load resistor network and finishing network controller;
Described load resistor network comprises resistance R and the some cell resistance Ri that is connected on successively between input IN and the output OUT, i=0,1,2 ... N, each cell resistance Ri comprises field effect transistor M Di, i=0,1,2 ... N, MUi, i=0,1,2 ... N and cell resistance Δ R/2
i, i=0,1,2 ... N, the end of the drain electrode series unit resistance R i of field effect transistor M Ui, the source electrode of the source electrode parallel field effect transistor MDi of field effect transistor M Ui, the other end of the drain electrode of field effect transistor M Di cell resistance Ri in parallel;
Described finishing network controller comprises some control switch SUi and SDi, i=0,1,2 ... N, the end of described control switch SUi can select to connect Vreg end or the earth terminal at resistance finishing networking, the other end of control switch SUi connects the grid of field effect transistor M Ui, and the end of described control switch SDi can select to connect Vreg end or the earth terminal at resistance finishing networking, and the other end of control switch SDi connects the grid of field effect transistor M Di.
Described collapsible amplifying stage comprises field effect transistor M P2, MP3, MN0, MN1, MN2, MN3, MP4, MP5, MP6 and MP7, and bias voltage Vnc, Vns and Vpc;
The source electrode of field effect transistor M P2 and MP3 is connected current source I1, the grid of MP2 connects the drain electrode of MP1, the grid of MP3 connects the drain electrode of MP0, the drain electrode of MP2 connects the source electrode of MN0, the drain electrode of MP3 connects the source electrode of MN1, the grid of MN0 and MN1 is connected the positive pole of bias voltage Vns, the grounded drain VSS of MN0, the grounded drain VSS of MN1, the grid of MN2 and MN3 is connected the positive pole of bias voltage Vnc, the drain electrode of MN2 connects the source electrode of MN0, the drain electrode of MN3 connects the source electrode of MN1, and the source electrode of MP4 and MP5 is connected power vd D, and the grid of MP4 and MP5 is connected the drain electrode of MP6, the drain electrode of MP4 connects the source electrode of MP6, the drain electrode of MP5 connects the source electrode of MP7, and the grid of MP6 and MP7 is connected the positive pole of bias voltage Vpc, and the drain electrode of MP6 connects the source electrode of MN2, the drain electrode of MP7 connects the source electrode of MN3, is output OUT.
The present invention also provides a kind of high-gain self calibration buffer amplifier of simplification, and this amplifier comprises input pipe MP0 and MP1, resistance are repaired the networking, and collapsible amplifying stage;
Current source I1 connects input to the source electrode of pipe MP0 and MP1, the grid of MP0 connects input INM, the grid of MP1 connects input INP, the input IN at resistance finishing networking connects the drain electrode of transistor MN0 and MN1, the output OUT ground connection VSS at resistance finishing networking, the Vreg end at resistance finishing networking connects power vd D.
Described resistance finishing networking comprises load resistor network and finishing network controller;
Described load resistor network comprises resistance R and the some cell resistance Ri that is connected on successively between input IN and the output OUT, i=0,1,2 ... N, each cell resistance Ri comprises field effect transistor M Di, i=0,1,2 ... N, MUi, i=0,1,2 ... N and cell resistance Δ R/2
i, i=0,1,2 ... N, the end of the drain electrode series unit resistance R i of field effect transistor M Ui, the source electrode of the source electrode parallel field effect transistor MDi of field effect transistor M Ui, the other end of the drain electrode of field effect transistor M Di cell resistance Ri in parallel;
Described finishing network controller comprises some control switch SUi and SDi, i=0,1,2 ... N, the end of described control switch SUi can select to connect Vreg end or the earth terminal at resistance finishing networking, the other end of control switch SUi connects the grid of field effect transistor M Ui, and the end of described control switch SDi can select to connect Vreg end or the earth terminal at resistance finishing networking, and the other end of control switch SDi connects the grid of field effect transistor M Di.
Described collapsible amplifying stage comprises field effect transistor M P2, MP3, MN0, MN1, MN2, MN3, MP4 and MP5, and bias voltage Vnc, Vns and Vpc;
The grid of field effect transistor M N0 and MN1 is connected the positive pole of bias voltage Vns, the source electrode of MN0 connects the drain electrode of MP0, the source electrode of MN1 connects the drain electrode of MP1, the grid of MN2 and MN3 is connected the positive pole of bias voltage Vnc, the drain electrode of MN2 connects the source electrode of MN0, the drain electrode of MN3 connects the source electrode of MN1, the source electrode of MP2 and MP3 is connected power vd D, the grid of MP2 and MP3 is connected the drain electrode of MP4, the grid of MP4 and MP5 is connected the positive pole of bias voltage Vpc, the drain electrode of MP4 connects the source electrode of MN2, and the drain electrode of MP5 connects the source electrode of MN3, is output OUT.
The present invention also provides a kind of AB class high-gain self calibration buffer amplifier, and this amplifier comprises pre-amplifying stage and the collapsible amplifying stage that circuit connects;
This pre-amplifying stage comprises current source I0, input to pipe MP0 and MP1, and resistance finishing networking;
Current source I0 connects input to the source electrode of pipe MP0 and MP1, the grid of MP0 connects input INM, the grid of MP1 connects input INP, the input IN at resistance finishing networking connects input to the drain electrode of pipe MP0 and MP1, the output OUT ground connection VSS at resistance finishing networking, the Vreg end at resistance finishing networking connects power vd D.
Described resistance finishing networking comprises load resistor network and finishing network controller;
Described load resistor network comprises resistance R and the some cell resistance Ri that is connected on successively between input IN and the output OUT, i=0,1,2 ... N, each cell resistance Ri comprises field effect transistor M Di, i=0,1,2 ... N, MUi, i=0,1,2 ... N and cell resistance Δ R/2
i, i=0,1,2 ... N, the end of the drain electrode series unit resistance R i of field effect transistor M Ui, the source electrode of the source electrode parallel field effect transistor MDi of field effect transistor M Ui, the other end of the drain electrode of field effect transistor M Di cell resistance Ri in parallel;
Described finishing network controller comprises some control switch SUi and SDi, i=0,1,2 ... N, the end of described control switch SUi can select to connect Vreg end or the earth terminal at resistance finishing networking, the other end of control switch SUi connects the grid of field effect transistor M Ui, and the end of described control switch SDi can select to connect Vreg end or the earth terminal at resistance finishing networking, and the other end of control switch SDi connects the grid of field effect transistor M Di.
Described collapsible amplifying stage comprises field effect transistor M P2, MP3, MN0, MN1, MN2, MN3, MP4, MP5, MP6, MP7, AB class bias structure, MP8 and MN4, and bias voltage Vnc, Vns and Vpc;
The source electrode of field effect transistor M P2 and MP3 is connected current source I1, the grid of MP2 connects the drain electrode of MP1, the grid of MP3 connects the drain electrode of MP0, the drain electrode of MP2 connects the source electrode of MN0, the drain electrode of MP3 connects the source electrode of MN1, the grid of MN0 and MN1 is connected the positive pole of bias voltage Vns, the grounded drain VSS of MN0, the grounded drain VSS of MN1, the grid of MN2 and MN3 is connected the positive pole of bias voltage Vnc, the drain electrode of MN2 connects the source electrode of MN0, the drain electrode of MN3 connects the source electrode of MN1, the source electrode of MN2 and MN3 is connected AB class bias structure, the source electrode of MP4 and MP5 is connected power vd D, the grid of MP4 and MP5 is connected the drain electrode of MP6, the drain electrode of MP4 connects the source electrode of MP6, the drain electrode of MP5 connects the source electrode of MP7, the grid of MP6 and MP7 is connected the positive pole of bias voltage Vpc, the drain electrode of MP6 and MP7 is connected AB class bias structure, and the source electrode of MP8 connects power vd D, and the grid of MP8 connects the drain electrode of MP7, the drain electrode of MP8 connects the source electrode of MN4, be output OUT, the grid of MN4 connects the source electrode of MN3, the grounded drain VSS of MN4.
The present invention also provides a kind of AB class high-gain self calibration buffer amplifier of simplification, and this amplifier comprises input pipe MP0 and MP1, resistance are repaired the networking, and collapsible amplifying stage;
Current source I1 connects input to the source electrode of pipe MP0 and MP1, the grid of MP0 connects input INM, the grid of MP1 connects input INP, the input IN at resistance finishing networking connects the drain electrode of transistor MN0 and MN1, the output OUT ground connection VSS at resistance finishing networking, the Vreg end at resistance finishing networking connects power vd D.
Described resistance finishing networking comprises load resistor network and finishing network controller;
Described load resistor network comprises resistance R and the some cell resistance Ri that is connected on successively between input IN and the output OUT, i=0,1,2 ... N, each cell resistance Ri comprises field effect transistor M Di, i=0,1,2 ... N, MUi, i=0,1,2 ... N and cell resistance Δ R/2
i, i=0,1,2 ... N, the end of the drain electrode series unit resistance R i of field effect transistor M Ui, the source electrode of the source electrode parallel field effect transistor MDi of field effect transistor M Ui, the other end of the drain electrode of field effect transistor M Di cell resistance Ri in parallel;
Described finishing network controller comprises some control switch SUi and SDi, i=0,1,2 ... N, the end of described control switch SUi can select to connect Vreg end or the earth terminal at resistance finishing networking, the other end of control switch SUi connects the grid of field effect transistor M Ui, and the end of described control switch SDi can select to connect Vreg end or the earth terminal at resistance finishing networking, and the other end of control switch SDi connects the grid of field effect transistor M Di.
Described collapsible amplifying stage comprises field effect transistor M P2, MP3, MN0, MN1, MN2, MN3, MP4, MP5, AB class bias structure, MP8 and MN4, and bias voltage Vnc, Vns and Vpc;
The grid of field effect transistor M N0 and MN1 is connected the positive pole of bias voltage Vns, the source electrode of MN0 connects the drain electrode of MP0, the source electrode of MN1 connects the drain electrode of MP1, the grid of MN2 and MN3 is connected the positive pole of bias voltage Vnc, the drain electrode of MN2 connects the source electrode of MN0, the drain electrode of MN3 connects the source electrode of MN1, the source electrode of MN2 and MN3 is connected AB class bias structure, the source electrode of MP2 and MP3 is connected power vd D, the grid of MP2 and MP3 is connected the drain electrode of MP4, and the grid of MP4 and MP5 is connected the positive pole of bias voltage Vpc, and the drain electrode of MP4 and MP5 is connected AB class bias structure, the source electrode of MP8 connects power vd D, the grid of MP8 connects the drain electrode of MP5, and the drain electrode of MP8 connects the source electrode of MN4, is output OUT, the grid of MN4 connects the source electrode of MN3, the grounded drain VSS of MN4.
The present invention eliminates or has reduced amplifier input imbalance greatly, has strengthened focusing effect, has prolonged system service time, and has reduced chip cost.
Description of drawings
Fig. 1 is the circuit structure diagram of voice coil motor lens driver in the background technology.
Fig. 2 is the circuit diagram of the self-calibration circuit in the voice coil motor lens driver in the background technology.
Fig. 3 is the circuit diagram of the high-gain self calibration buffer amplifier among the present invention.
Fig. 4 is the circuit diagram at the resistance finishing networking of the self calibration buffer amplifier among the present invention.
Fig. 5 is the circuit diagram of the high-gain self calibration buffer amplifier of a kind of simplification among the present invention.
Fig. 6 is the circuit diagram of the AB class high-gain self calibration buffer amplifier among the present invention.
Fig. 7 is the circuit diagram of the AB class high-gain self calibration buffer amplifier of a kind of simplification among the present invention.
Embodiment
Following according to Fig. 2～Fig. 7, specify preferred embodiment of the present invention.
As shown in Figure 3, the invention provides a kind of high-gain self calibration buffer amplifier, this amplifier comprises pre-amplifying stage and the collapsible amplifying stage that circuit connects.
This pre-amplifying stage comprises current source I0, input to pipe MP0 and MP1, and resistance finishing networking.
Current source I0 connects input to the source electrode of pipe MP0 and MP1, the grid of MP0 connects input INM, the grid of MP1 connects input INP, as shown in Figure 4, the input IN at resistance finishing networking connects input to the drain electrode of pipe MP0 and MP1, the output OUT ground connection VSS at resistance finishing networking, the Vreg end at resistance finishing networking connects power vd D.
In the present embodiment, the Vreg end connects the output of linear voltage regulator.
This collapsible amplifying stage comprises field effect transistor M P2, MP3, MN0, MN1, MN2, MN3, MP4, MP5, MP6 and MP7, and bias voltage Vnc, Vns and Vpc.
The source electrode of field effect transistor M P2 and MP3 is connected current source I1, the grid of MP2 connects the drain electrode of MP1, the grid of MP3 connects the drain electrode of MP0, the drain electrode of MP2 connects the source electrode of MN0, the drain electrode of MP3 connects the source electrode of MN1, the grid of MN0 and MN1 is connected the positive pole of bias voltage Vns, the grounded drain VSS of MN0, the grounded drain VSS of MN1, the grid of MN2 and MN3 is connected the positive pole of bias voltage Vnc, the drain electrode of MN2 connects the source electrode of MN0, the drain electrode of MN3 connects the source electrode of MN1, and the source electrode of MP4 and MP5 is connected power vd D, and the grid of MP4 and MP5 is connected the drain electrode of MP6, the drain electrode of MP4 connects the source electrode of MP6, the drain electrode of MP5 connects the source electrode of MP7, and the grid of MP6 and MP7 is connected the positive pole of bias voltage Vpc, and the drain electrode of MP6 connects the source electrode of MN2, the drain electrode of MP7 connects the source electrode of MN3, is output OUT.
Described resistance finishing networking comprises load resistor network and finishing network controller.
As shown in Figure 4, described load resistor network comprises resistance R and the some cell resistance Ri(i=0 that is connected on successively between input IN and the output OUT, 1,2 ... N) each cell resistance Ri comprises field effect transistor M Di(i=0,1,2 ... N), MUi(i=0,1,2 ... N) and cell resistance Δ R/2
i(i=0,1,2 ... N), the end of the drain electrode series unit resistance R i of field effect transistor M Ui, the source electrode of the source electrode parallel field effect transistor MDi of field effect transistor M Ui, the other end of the drain electrode of field effect transistor M Di cell resistance Ri in parallel.
Described finishing network controller comprises some control switch SUi and SDi(i=0,1,2 ... N), the end of described control switch SUi can select to connect Vreg end or the earth terminal at resistance finishing networking, the other end of control switch SUi connects the grid of field effect transistor M Ui, the end of described control switch SDi can select to connect Vreg end or the earth terminal at resistance finishing networking, and the other end of control switch SDi connects the grid of field effect transistor M Di.
Some control switch SU in the described finishing network controller
iAnd SD
iControl (as shown in Figure 2) by the self calibration controller, as shown in Figure 3, the self calibration controller sends control bit br
i(i=0,1,2 ... N) and bl
i(i=0,1,2 ... N) come control switch SU respectively
iAnd SD
i, control bit br
iAnd bl
iValue be 0 or 1, as control bit br
iAnd bl
iValue be 0 o'clock, switch S U
iAnd SD
iGround connection is as control bit br
iAnd bl
iValue be 1 o'clock, switch S U
iAnd SD
iConnect high potential.
When self calibration begins, make switch S U0, SU1 ... SUN ground connection, field effect transistor M U0, MU1 ... MUN ends; Make switch S D0, SD1 ... SDN meets high potential Vreg, field effect transistor M D0, and MD1 ... MDN connects.Resistance finishing networking total resistance value is Rm=R+N*Ron+ Σ bmi* (Δ R/2
i), wherein, m=r or l, i=0 ... N, Ron are field effect transistor M U0, MU1 ... MUN and MD0, MD1 ... the conduction resistance value of MDN.The finishing resistance value is with Δ R/2
NBe minimum unit, 2 systems increase.The resolution at this resistance finishing networking is by the pre-amplifying stage bias current I0 among Fig. 3 and the first decision of minimum finishing unit of resistance, and offset voltage is Δ V ≈ (I0/2) * (Δ R/2 under first approximation
N), we choose minimum resolution smaller or equal to the resolution of the auto zero comparator among Fig. 2 generally speaking.The offset voltage adjusting range is I0* Δ R*(1-1/2
N), this scope generally is taken as the maximum equivalent input offset voltage of buffer amplifier.Self-calibration process is from least unit unit, and when first clock, switch S UN receives high potential Vreg, turn-on field effect crystal switch MUN simultaneously with switch S DN ground connection, ends field effect transistor switch MDN, because MUN and MDN are measure-alike, whole finishing network resistance value increases Δ R/2
N, the offset voltage of introducing Δ V is in order to offset the prime amplifier input to the imbalance of pipe.If the output polarity of auto zero comparator is constant, the buffer amplifier offset voltage need continue finishing, the finishing controller is done linear search under the clock control afterwards, finish self-calibration process up to auto zero comparator change in polarity, the self calibration controller ties down SU0, SU1 ... SUN and SD0, SD1 ... the corresponding state of SDN.Buffer amplifier input equivalence imbalance is finished within the resolution of auto zero comparator.Organize the MOS switch of same size to pipe MU0 and MD0 by in finishing unit, introducing N, MU1 and MD1, MUN and MDN can eliminate the internal resistance of MOS switch to the influence of finishing source resistance value under first approximation, therefore can reduce the size of MOS switch greatly, thereby reduce chip area.The MOS switch can be introduced corresponding switch internal resistance imbalance to pipe, chooses switch the size of metal-oxide-semiconductor is made the resistance value Δ R/2 of corresponding internal resistance imbalance much smaller than the minimum resistance source
N, to guarantee the minimum resolution at finishing networking.Supply voltage in system's chips has bigger excursion usually, and the internal resistance of MOS switching tube will influence finishing resolution and the error at resistance networking with mains voltage variations.For guaranteeing that there is higher Power Supply Rejection Ratio at the resistance networking, the present invention receives a stable voltage source V reg with the turning-on voltage of MOS switch, and this burning voltage is produced by the linear voltage regulator of chip internal, and magnitude of voltage generally is slightly less than chip minimum power source voltage value.Resistance finishing networking among the present invention will reduce chip area, and good Power Supply Rejection Ratio is arranged simultaneously.
Prime amplifier can not only provide the input mistuning calibration function of buffer amplifier, the gain that can also improve buffer amplifier.The gain of whole buffer amplifier can be satisfied requirement of system design up to more than the 100dB.The equivalence input imbalance of collapsible amplifying stage is reduced by pre-amplifying stage, and decrease is directly proportional with the gain of pre-amplifying stage.The equivalence input imbalance of buffer amplifier is determined the imbalance of managing MP0 and MP1 by the input of pre-amplifying stage substantially.The size that changes load resistance Rr or Rl by the finishing network controller can realize self-calibration function easily.
The self calibration of buffer amplifier is to compensate input to the imbalance of pipe by the ohmic load that changes prime amplifier one end.Changing the input resistance value need insert switching device in the resistance networking, the switching device that is made of field-effect transistor has internal resistance, and internal resistance is relevant with switching voltage with temperature, eliminate switch internal resistance influence and can realize by reducing the switch internal resistance value usually, but thereby this method increases product cost with a large amount of increase chip areas.
Therefore, the present invention also provides a kind of high-gain self calibration buffer amplifier of simplification, and as shown in Figure 5, this amplifier comprises input pipe MP0 and MP1, resistance are repaired the networking, and collapsible amplifying stage.
Current source I1 connects input to the source electrode of pipe MP0 and MP1, the grid of MP0 connects input INM, the grid of MP1 connects input INP, the input IN at resistance finishing networking connects the drain electrode of transistor MN0 and MN1, the output OUT ground connection VSS at resistance finishing networking, the Vreg end at resistance finishing networking connects power vd D.
This collapsible amplifying stage comprises field effect transistor M P2, MP3, MN0, MN1, MN2, MN3, MP4 and MP5, and bias voltage Vnc, Vns and Vpc.
The grid of field effect transistor M N0 and MN1 is connected the positive pole of bias voltage Vns, the source electrode of MN0 connects the drain electrode of MP0, the source electrode of MN1 connects the drain electrode of MP1, the grid of MN2 and MN3 is connected the positive pole of bias voltage Vnc, the drain electrode of MN2 connects the source electrode of MN0, the drain electrode of MN3 connects the source electrode of MN1, the source electrode of MP2 and MP3 is connected power vd D, the grid of MP2 and MP3 is connected the drain electrode of MP4, the grid of MP4 and MP5 is connected the positive pole of bias voltage Vpc, the drain electrode of MP4 connects the source electrode of MN2, and the drain electrode of MP5 connects the source electrode of MN3, is output OUT.
Described resistance finishing networking comprises load resistor network and finishing network controller.
As shown in Figure 4, described load resistor network comprises resistance R and the some cell resistance Ri(i=0 that is connected on successively between input IN and the output OUT, 1,2 ... N, each cell resistance Ri comprises field effect transistor M Di(i=0,1,2 ... N, MUi(i=0,1,2 ... N) and cell resistance Δ R/2
i(i=0,1,2 ... N), the end of the drain electrode series unit resistance R i of field effect transistor M Ui, the source electrode of the source electrode parallel field effect transistor MDi of field effect transistor M Ui, the other end of the drain electrode of field effect transistor M Di cell resistance Ri in parallel.
Described finishing network controller comprises some control switch SUi and SDi(i=0,1,2 ... N), the end of described control switch SUi can select to connect Vreg end or the earth terminal at resistance finishing networking, the other end of control switch SUi connects the grid of field effect transistor M Ui, the end of described control switch SDi can select to connect Vreg end or the earth terminal at resistance finishing networking, and the other end of control switch SDi connects the grid of field effect transistor M Di.
The high-gain self calibration buffer amplifier of this simplification adopts collapsible amplifier architecture, compares the buffer amplifier of Fig. 3, this structure decrease pre-amplifying stage, thereby reduced chip area owing to remove pre-amplifying stage, the whole amplifier gain reduces, but still can reach system requirements.Because resistance is repaired the networking places MN0 and MN1 source end, form source end degeneracy, can reduce imbalance and the noise contribution of MN0 and MN1.The whole amplifier imbalance is still determined by the imbalance of input to pipe MP0 and MP1.Source end degeneracy has improved the voltage of node 511 and 512, and finishing network resistance value can not be too big.511 and 512 too high node voltages will force input that pipe MP0 and MP1 are operated in outside the saturation region, make amplifier lose efficacy.Therefore the finishing scope of this structure is littler than the amplifier finishing scope of Fig. 3.The self-calibration process of this amplifier is identical with preceding described principle.
When the lens driver output current hour, the voltage of node 12 is lower among Fig. 1 because efferent duct MN0 size is very big, the voltage of node 10 can be lower in some technologies, the output stage N field effect transistor end of buffer amplifier can be operated in non-saturated region.As shown in Figure 3, when dropping to less than this situation of 0.3V(, output OUT voltage can occur in low temperature environment, when low output current and shock processing processing procedure), MN1 and MN3 are forced to be operated in non-saturated region, amplifier gain descends, with producing new equivalent offset voltage, make driver under this type of situation, output current be arranged, not only influencing system accuracy can increase chip power-consumption simultaneously.
For solving this type of problem, the present invention also provides a kind of AB class high-gain self calibration buffer amplifier, and as shown in Figure 6, this amplifier comprises pre-amplifying stage and the collapsible amplifying stage that circuit connects.
This pre-amplifying stage comprises current source I0, input to pipe MP0 and MP1, and resistance finishing networking.
Current source I0 connects input to the source electrode of pipe MP0 and MP1, the grid of MP0 connects input INM, the grid of MP1 connects input INP, the input IN at resistance finishing networking connects input to the drain electrode of pipe MP0 and MP1, the output OUT ground connection VSS at resistance finishing networking, the Vreg end at resistance finishing networking connects power vd D.
This collapsible amplifying stage comprises field effect transistor M P2, MP3, MN0, MN1, MN2, MN3, MP4, MP5, MP6, MP7, AB class bias structure, MP8 and MN4, and bias voltage Vnc, Vns and Vpc.
The source electrode of field effect transistor M P2 and MP3 is connected current source I1, the grid of MP2 connects the drain electrode of MP1, the grid of MP3 connects the drain electrode of MP0, the drain electrode of MP2 connects the source electrode of MN0, the drain electrode of MP3 connects the source electrode of MN1, the grid of MN0 and MN1 is connected the positive pole of bias voltage Vns, the grounded drain VSS of MN0, the grounded drain VSS of MN1, the grid of MN2 and MN3 is connected the positive pole of bias voltage Vnc, the drain electrode of MN2 connects the source electrode of MN0, the drain electrode of MN3 connects the source electrode of MN1, the source electrode of MN2 and MN3 is connected AB class bias structure, the source electrode of MP4 and MP5 is connected power vd D, the grid of MP4 and MP5 is connected the drain electrode of MP6, the drain electrode of MP4 connects the source electrode of MP6, the drain electrode of MP5 connects the source electrode of MP7, the grid of MP6 and MP7 is connected the positive pole of bias voltage Vpc, the drain electrode of MP6 and MP7 is connected AB class bias structure, and the source electrode of MP8 connects power vd D, and the grid of MP8 connects the drain electrode of MP7, the drain electrode of MP8 connects the source electrode of MN4, be output OUT, the grid of MN4 connects the source electrode of MN3, the grounded drain VSS of MN4.
Described resistance finishing networking comprises load resistor network and finishing network controller.
As shown in Figure 4, described load resistor network comprises resistance R and the some cell resistance Ri(i=0 that is connected on successively between input IN and the output OUT, 1,2 ... N) each cell resistance Ri comprises field effect transistor M Di(i=0,1,2 ... N), MUi(i=0,1,2 ... N) and cell resistance Δ R/2
i(i=0,1,2 ... N), the end of the drain electrode series unit resistance R i of field effect transistor M Ui, the source electrode of the source electrode parallel field effect transistor MDi of field effect transistor M Ui, the other end of the drain electrode of field effect transistor M Di cell resistance Ri in parallel.
Described finishing network controller comprises some control switch SUi and SDi(i=0,1,2 ... N), the end of described control switch SUi can select to connect Vreg end or the earth terminal at resistance finishing networking, the other end of control switch SUi connects the grid of field effect transistor M Ui, the end of described control switch SDi can select to connect Vreg end or the earth terminal at resistance finishing networking, and the other end of control switch SDi connects the grid of field effect transistor M Di.
The output of this AB class high-gain self calibration buffer amplifier can be operated in positive-negative power voltage, even output OUT is reduced to zero, the self calibration buffer amplifier still can keep very high gain, thereby guarantees driver operate as normal when low output voltage.
The present invention also provides a kind of AB class high-gain self calibration buffer amplifier of simplification, and as shown in Figure 7, this amplifier comprises input pipe MP0 and MP1, resistance are repaired the networking, and collapsible amplifying stage.
Current source I1 connects input to the source electrode of pipe MP0 and MP1, the grid of MP0 connects input INM, the grid of MP1 connects input INP, the input IN at resistance finishing networking connects the drain electrode of transistor MN0 and MN1, the output OUT ground connection VSS at resistance finishing networking, the Vreg end at resistance finishing networking connects power vd D.
This collapsible amplifying stage comprises field effect transistor M P2, MP3, MN0, MN1, MN2, MN3, MP4, MP5, AB class bias structure, MP8 and MN4, and bias voltage Vnc, Vns and Vpc.
The grid of field effect transistor M N0 and MN1 is connected the positive pole of bias voltage Vns, the source electrode of MN0 connects the drain electrode of MP0, the source electrode of MN1 connects the drain electrode of MP1, the grid of MN2 and MN3 is connected the positive pole of bias voltage Vnc, the drain electrode of MN2 connects the source electrode of MN0, the drain electrode of MN3 connects the source electrode of MN1, the source electrode of MN2 and MN3 is connected AB class bias structure, the source electrode of MP2 and MP3 is connected power vd D, the grid of MP2 and MP3 is connected the drain electrode of MP4, and the grid of MP4 and MP5 is connected the positive pole of bias voltage Vpc, and the drain electrode of MP4 and MP5 is connected AB class bias structure, the source electrode of MP8 connects power vd D, the grid of MP8 connects the drain electrode of MP5, and the drain electrode of MP8 connects the source electrode of MN4, is output OUT, the grid of MN4 connects the source electrode of MN3, the grounded drain VSS of MN4.
Described resistance finishing networking comprises load resistor network and finishing network controller.
As shown in Figure 4, described load resistor network comprises resistance R and the some cell resistance Ri(i=0 that is connected on successively between input IN and the output OUT, 1,2 ... N) each cell resistance Ri comprises field effect transistor M Di(i=0,1,2 ... N), MUi(i=0,1,2 ... N) and cell resistance Δ R/2
i(i=0,1,2 ... N), the end of the drain electrode series unit resistance R i of field effect transistor M Ui, the source electrode of the source electrode parallel field effect transistor MDi of field effect transistor M Ui, the other end of the drain electrode of field effect transistor M Di cell resistance Ri in parallel.
Described finishing network controller comprises some control switch SUi and SDi(i=0,1,2 ... N), the end of described control switch SUi can select to connect Vreg end or the earth terminal at resistance finishing networking, the other end of control switch SUi connects the grid of field effect transistor M Ui, the end of described control switch SDi can select to connect Vreg end or the earth terminal at resistance finishing networking, and the other end of control switch SDi connects the grid of field effect transistor M Di.
The present invention can be applied in the voice coil motor lens driver system, the present invention has solved the accuracy problem of chip system by self calibration buffer amplifier and self calibration AB class buffer amplifier, eliminate or reduced dc power greatly, thereby reach good systemic-function, and save chip cost.The present invention utilizes the resistance finishing networking of optimization to reduce networking imbalance and networking area, thereby reaches the purpose that improves network performance and reduce chip cost.
Although content of the present invention has been done detailed introduction by above preferred embodiment, will be appreciated that above-mentioned description should not be considered to limitation of the present invention.After those skilled in the art have read foregoing, for multiple modification of the present invention with to substitute all will be apparent.Therefore, protection scope of the present invention should be limited to the appended claims.
Claims (10)
1. a high-gain self calibration buffer amplifier is characterized in that, this amplifier comprises pre-amplifying stage and the collapsible amplifying stage that circuit connects;
This pre-amplifying stage comprises current source I0, input to pipe MP0 and MP1, and resistance finishing networking;
Current source I0 connects input to the source electrode of pipe MP0 and MP1, the grid of MP0 connects input INM, the grid of MP1 connects input INP, the input IN at resistance finishing networking connects input to the drain electrode of pipe MP0 and MP1, the output OUT ground connection VSS at resistance finishing networking, the Vreg end at resistance finishing networking connects power vd D.
2. high-gain self calibration buffer amplifier as claimed in claim 1 is characterized in that, described resistance finishing networking comprises load resistor network and finishing network controller;
Described load resistor network comprises resistance R and the some cell resistance Ri that is connected on successively between input IN and the output OUT, i=0,1,2 ... N, each cell resistance Ri comprises field effect transistor M Di, i=0,1,2 ... N, MUi, i=0,1,2 ... N and cell resistance Δ R/2
i, i=0,1,2 ... N, the end of the drain electrode series unit resistance R i of field effect transistor M Ui, the source electrode of the source electrode parallel field effect transistor MDi of field effect transistor M Ui, the other end of the drain electrode of field effect transistor M Di cell resistance Ri in parallel;
Described finishing network controller comprises some control switch SUi and SDi, i=0,1,2 ... N, the end of described control switch SUi can select to connect Vreg end or the earth terminal at resistance finishing networking, the other end of control switch SUi connects the grid of field effect transistor M Ui, and the end of described control switch SDi can select to connect Vreg end or the earth terminal at resistance finishing networking, and the other end of control switch SDi connects the grid of field effect transistor M Di.
3. high-gain self calibration buffer amplifier as claimed in claim 2, it is characterized in that, described collapsible amplifying stage comprises field effect transistor M P2, MP3, MN0, MN1, MN2, MN3, MP4, MP5, MP6 and MP7, and bias voltage Vnc, Vns and Vpc;
The source electrode of field effect transistor M P2 and MP3 is connected current source I1, the grid of MP2 connects the drain electrode of MP1, the grid of MP3 connects the drain electrode of MP0, the drain electrode of MP2 connects the source electrode of MN0, the drain electrode of MP3 connects the source electrode of MN1, the grid of MN0 and MN1 is connected the positive pole of bias voltage Vns, the grounded drain VSS of MN0, the grounded drain VSS of MN1, the grid of MN2 and MN3 is connected the positive pole of bias voltage Vnc, the drain electrode of MN2 connects the source electrode of MN0, the drain electrode of MN3 connects the source electrode of MN1, and the source electrode of MP4 and MP5 is connected power vd D, and the grid of MP4 and MP5 is connected the drain electrode of MP6, the drain electrode of MP4 connects the source electrode of MP6, the drain electrode of MP5 connects the source electrode of MP7, and the grid of MP6 and MP7 is connected the positive pole of bias voltage Vpc, and the drain electrode of MP6 connects the source electrode of MN2, the drain electrode of MP7 connects the source electrode of MN3, is output OUT.
4. the high-gain self calibration buffer amplifier of a simplification is characterized in that, this amplifier comprises input pipe MP0 and MP1, resistance are repaired the networking, and collapsible amplifying stage;
Current source I1 connects input to the source electrode of pipe MP0 and MP1, the grid of MP0 connects input INM, the grid of MP1 connects input INP, the input IN at resistance finishing networking connects the drain electrode of transistor MN0 and MN1, the output OUT ground connection VSS at resistance finishing networking, the Vreg end at resistance finishing networking connects power vd D.
5. the high-gain self calibration buffer amplifier of simplification as claimed in claim 4 is characterized in that, described resistance finishing networking comprises load resistor network and finishing network controller;
Described load resistor network comprises resistance R and the some cell resistance Ri that is connected on successively between input IN and the output OUT, i=0,1,2 ... N, each cell resistance Ri comprises field effect transistor M Di, i=0,1,2 ... N, MUi, i=0,1,2 ... N and cell resistance Δ R/2
i, i=0,1,2 ... N, the end of the drain electrode series unit resistance R i of field effect transistor M Ui, the source electrode of the source electrode parallel field effect transistor MDi of field effect transistor M Ui, the other end of the drain electrode of field effect transistor M Di cell resistance Ri in parallel;
Described finishing network controller comprises some control switch SUi and SDi, i=0,1,2 ... N, the end of described control switch SUi can select to connect Vreg end or the earth terminal at resistance finishing networking, the other end of control switch SUi connects the grid of field effect transistor M Ui, and the end of described control switch SDi can select to connect Vreg end or the earth terminal at resistance finishing networking, and the other end of control switch SDi connects the grid of field effect transistor M Di.
6. the high-gain self calibration buffer amplifier of simplification as claimed in claim 5 is characterized in that, described collapsible amplifying stage comprises field effect transistor M P2, MP3, MN0, MN1, MN2, MN3, MP4 and MP5, and bias voltage Vnc, Vns and Vpc;
The grid of field effect transistor M N0 and MN1 is connected the positive pole of bias voltage Vns, the source electrode of MN0 connects the drain electrode of MP0, the source electrode of MN1 connects the drain electrode of MP1, the grid of MN2 and MN3 is connected the positive pole of bias voltage Vnc, the drain electrode of MN2 connects the source electrode of MN0, the drain electrode of MN3 connects the source electrode of MN1, the source electrode of MP2 and MP3 is connected power vd D, the grid of MP2 and MP3 is connected the drain electrode of MP4, the grid of MP4 and MP5 is connected the positive pole of bias voltage Vpc, the drain electrode of MP4 connects the source electrode of MN2, and the drain electrode of MP5 connects the source electrode of MN3, is output OUT.
7. an AB class high-gain self calibration buffer amplifier is characterized in that, this amplifier comprises pre-amplifying stage and the collapsible amplifying stage that circuit connects;
This pre-amplifying stage comprises current source I0, input to pipe MP0 and MP1, and resistance finishing networking;
Current source I0 connects input to the source electrode of pipe MP0 and MP1, the grid of MP0 connects input INM, the grid of MP1 connects input INP, the input IN at resistance finishing networking connects input to the drain electrode of pipe MP0 and MP1, the output OUT ground connection VSS at resistance finishing networking, the Vreg end at resistance finishing networking connects power vd D; Described resistance finishing networking comprises load resistor network and finishing network controller;
Described load resistor network comprises resistance R and the some cell resistance Ri that is connected on successively between input IN and the output OUT, i=0,1,2 ... N, individual cell resistance Ri comprises field effect transistor M Di, i=0,1,2 ... N, MUi, i=0,1,2 ... N and cell resistance Δ R/2
i, i=0,1,2 ... N, the end of the drain electrode series unit resistance R i of field effect transistor M Ui, the source electrode of the source electrode parallel field effect transistor MDi of field effect transistor M Ui, the other end of the drain electrode of field effect transistor M Di cell resistance Ri in parallel;
Described finishing network controller comprises some control switch SUi and SDi, i=0,1,2 ... N, the end of described control switch SUi can select to connect Vreg end or the earth terminal at resistance finishing networking, the other end of control switch SUi connects the grid of field effect transistor M Ui, and the end of described control switch SDi can select to connect Vreg end or the earth terminal at resistance finishing networking, and the other end of control switch SDi connects the grid of field effect transistor M Di.
8. AB class high-gain self calibration buffer amplifier as claimed in claim 7, it is characterized in that, described collapsible amplifying stage comprises field effect transistor M P2, MP3, MN0, MN1, MN2, MN3, MP4, MP5, MP6, MP7, AB class bias structure, MP8 and MN4, and bias voltage Vnc, Vns and Vpc;
The source electrode of field effect transistor M P2 and MP3 is connected current source I1, the grid of MP2 connects the drain electrode of MP1, the grid of MP3 connects the drain electrode of MP0, the drain electrode of MP2 connects the source electrode of MN0, the drain electrode of MP3 connects the source electrode of MN1, the grid of MN0 and MN1 is connected the positive pole of bias voltage Vns, the grounded drain VSS of MN0, the grounded drain VSS of MN1, the grid of MN2 and MN3 is connected the positive pole of bias voltage Vnc, the drain electrode of MN2 connects the source electrode of MN0, the drain electrode of MN3 connects the source electrode of MN1, the source electrode of MN2 and MN3 is connected AB class bias structure, the source electrode of MP4 and MP5 is connected power vd D, the grid of MP4 and MP5 is connected the drain electrode of MP6, the drain electrode of MP4 connects the source electrode of MP6, the drain electrode of MP5 connects the source electrode of MP7, the grid of MP6 and MP7 is connected the positive pole of bias voltage Vpc, the drain electrode of MP6 and MP7 is connected AB class bias structure, and the source electrode of MP8 connects power vd D, and the grid of MP8 connects the drain electrode of MP7, the drain electrode of MP8 connects the source electrode of MN4, be output OUT, the grid of MN4 connects the source electrode of MN3, the grounded drain VSS of MN4.
9. the AB class high-gain self calibration buffer amplifier of a simplification is characterized in that, this amplifier comprises input pipe MP0 and MP1, resistance are repaired the networking, and collapsible amplifying stage;
Current source I1 connects input to the source electrode of pipe MP0 and MP1, the grid of MP0 connects input INM, the grid of MP1 connects input INP, the input IN at resistance finishing networking connects the drain electrode of transistor MN0 and MN1, the output OUT ground connection VSS at resistance finishing networking, the Vreg end at resistance finishing networking connects power vd D;
Described resistance finishing networking comprises load resistor network and finishing network controller;
Described load resistor network comprises resistance R and the some cell resistance Ri that is connected on successively between input IN and the output OUT, i=0,1,2 ... N, each cell resistance Ri comprises field effect transistor M Di, i=0,1,2 ... N, MUi, i=0,1,2 ... N and cell resistance Δ R/2
i, i=0,1,2 ... N, the end of the drain electrode series unit resistance R i of field effect transistor M Ui, the source electrode of the source electrode parallel field effect transistor MDi of field effect transistor M Ui, the other end of the drain electrode of field effect transistor M Di cell resistance Ri in parallel;
Described finishing network controller comprises some control switch SUi and SDi, i=0,1,2 ... N, the end of described control switch SUi can select to connect Vreg end or the earth terminal at resistance finishing networking, the other end of control switch SUi connects the grid of field effect transistor M Ui, and the end of described control switch SDi can select to connect Vreg end or the earth terminal at resistance finishing networking, and the other end of control switch SDi connects the grid of field effect transistor M Di.
10. the AB class high-gain self calibration buffer amplifier of simplification as claimed in claim 9, it is characterized in that, described collapsible amplifying stage comprises field effect transistor M P2, MP3, MN0, MN1, MN2, MN3, MP4, MP5, AB class bias structure, MP8 and MN4, and bias voltage Vnc, Vns and Vpc;
The grid of field effect transistor M N0 and MN1 is connected the positive pole of bias voltage Vns, the source electrode of MN0 connects the drain electrode of MP0, the source electrode of MN1 connects the drain electrode of MP1, the grid of MN2 and MN3 is connected the positive pole of bias voltage Vnc, the drain electrode of MN2 connects the source electrode of MN0, the drain electrode of MN3 connects the source electrode of MN1, the source electrode of MN2 and MN3 is connected AB class bias structure, the source electrode of MP2 and MP3 is connected power vd D, the grid of MP2 and MP3 is connected the drain electrode of MP4, and the grid of MP4 and MP5 is connected the positive pole of bias voltage Vpc, and the drain electrode of MP4 and MP5 is connected AB class bias structure, the source electrode of MP8 connects power vd D, the grid of MP8 connects the drain electrode of MP5, and the drain electrode of MP8 connects the source electrode of MN4, is output OUT, the grid of MN4 connects the source electrode of MN3, the grounded drain VSS of MN4.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310152041.8A CN103296974B (en) | 2013-04-27 | 2013-04-27 | Self calibration buffer amplifier in voice coil motor driver and resistance finishing networking |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201310152041.8A CN103296974B (en) | 2013-04-27 | 2013-04-27 | Self calibration buffer amplifier in voice coil motor driver and resistance finishing networking |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN103296974A true CN103296974A (en) | 2013-09-11 |
| CN103296974B CN103296974B (en) | 2015-12-09 |
Family
ID=49097400
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201310152041.8A Active CN103296974B (en) | 2013-04-27 | 2013-04-27 | Self calibration buffer amplifier in voice coil motor driver and resistance finishing networking |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN103296974B (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106444948A (en) * | 2016-11-01 | 2017-02-22 | 无锡思泰迪半导体有限公司 | Voice coil motor driving chip offset current and maximum output current correction method |
| CN108718196A (en) * | 2018-08-01 | 2018-10-30 | 武汉韦尔半导体有限公司 | A kind of amplifier imbalance self-calibration circuit applied to voice coil motor driving chip |
| CN110277966A (en) * | 2019-05-09 | 2019-09-24 | 上海类比半导体技术有限公司 | A kind of self-calibration circuit and calibration method |
| CN114637354A (en) * | 2022-03-28 | 2022-06-17 | 杭州红芯微电子信息科技有限公司 | Trimming circuit for operational amplifier circuit |
Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20020079854A1 (en) * | 2000-11-29 | 2002-06-27 | Yasushi Kitamura | Automatic gain adjustment for voice call motor back EMF monitor |
| US20050168862A1 (en) * | 2003-12-12 | 2005-08-04 | Samsung Electronics Co., Ltd. | Hard disk drive calibration method and apparatus |
| US20080198499A1 (en) * | 2007-02-21 | 2008-08-21 | Stmicroelectronics, Inc. | Continuous mode velocity control of voice coil motor |
| CN201781461U (en) * | 2010-08-19 | 2011-03-30 | 美凌微电子(上海)有限公司 | High-gain class AB operational amplifier for quiescent current accuracy control |
| CN201813423U (en) * | 2010-09-17 | 2011-04-27 | 惠州Tcl移动通信有限公司 | Mobile terminal with automatic focusing function and driving circuit thereof |
| CN202503479U (en) * | 2012-03-16 | 2012-10-24 | 聚辰半导体(上海)有限公司 | A class AB operational amplifier with high gain and a high power supply rejection ration |
| CN102983825A (en) * | 2012-11-16 | 2013-03-20 | 上海贝岭股份有限公司 | Category D amplifier chip |
-
2013
- 2013-04-27 CN CN201310152041.8A patent/CN103296974B/en active Active
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20020079854A1 (en) * | 2000-11-29 | 2002-06-27 | Yasushi Kitamura | Automatic gain adjustment for voice call motor back EMF monitor |
| US20050168862A1 (en) * | 2003-12-12 | 2005-08-04 | Samsung Electronics Co., Ltd. | Hard disk drive calibration method and apparatus |
| US20080198499A1 (en) * | 2007-02-21 | 2008-08-21 | Stmicroelectronics, Inc. | Continuous mode velocity control of voice coil motor |
| CN201781461U (en) * | 2010-08-19 | 2011-03-30 | 美凌微电子(上海)有限公司 | High-gain class AB operational amplifier for quiescent current accuracy control |
| CN201813423U (en) * | 2010-09-17 | 2011-04-27 | 惠州Tcl移动通信有限公司 | Mobile terminal with automatic focusing function and driving circuit thereof |
| CN202503479U (en) * | 2012-03-16 | 2012-10-24 | 聚辰半导体(上海)有限公司 | A class AB operational amplifier with high gain and a high power supply rejection ration |
| CN102983825A (en) * | 2012-11-16 | 2013-03-20 | 上海贝岭股份有限公司 | Category D amplifier chip |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106444948A (en) * | 2016-11-01 | 2017-02-22 | 无锡思泰迪半导体有限公司 | Voice coil motor driving chip offset current and maximum output current correction method |
| CN106444948B (en) * | 2016-11-01 | 2017-12-12 | 无锡思泰迪半导体有限公司 | A kind of voice coil motor driving chip offset current and maximum output current bearing calibration |
| CN108718196A (en) * | 2018-08-01 | 2018-10-30 | 武汉韦尔半导体有限公司 | A kind of amplifier imbalance self-calibration circuit applied to voice coil motor driving chip |
| CN108718196B (en) * | 2018-08-01 | 2023-08-08 | 武汉韦尔半导体有限公司 | Operational amplifier offset self-calibration circuit applied to voice coil motor driving chip |
| CN110277966A (en) * | 2019-05-09 | 2019-09-24 | 上海类比半导体技术有限公司 | A kind of self-calibration circuit and calibration method |
| CN110277966B (en) * | 2019-05-09 | 2023-03-14 | 上海类比半导体技术有限公司 | Self-calibration circuit and calibration method |
| CN114637354A (en) * | 2022-03-28 | 2022-06-17 | 杭州红芯微电子信息科技有限公司 | Trimming circuit for operational amplifier circuit |
Also Published As
| Publication number | Publication date |
|---|---|
| CN103296974B (en) | 2015-12-09 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US9134743B2 (en) | Low-dropout voltage regulator | |
| US9575499B2 (en) | Low-dropout voltage regulator | |
| KR102352890B1 (en) | Dc-dc converter having circuits for controlling volatge of flying capacitor and therefore voltage controlling method | |
| CN106558987B (en) | Low quiescent current linear regulator circuit | |
| US9323263B2 (en) | Low dropout regulator with hysteretic control | |
| CN108718196B (en) | Operational amplifier offset self-calibration circuit applied to voice coil motor driving chip | |
| US8866341B2 (en) | Voltage regulator | |
| US10474174B2 (en) | Programmable supply generator | |
| US20090051329A1 (en) | Method and charge-up circuit capable of adjusting charge-up current | |
| CN106292824A (en) | low-dropout regulator circuit | |
| US20100264896A1 (en) | Voltage regulator circuit | |
| KR102225712B1 (en) | Voltage regulator | |
| US10571942B2 (en) | Overcurrent limiting circuit, overcurrent limiting method, and power supply circuit | |
| US9484809B2 (en) | Apparatus and methods for low voltage high PSRR systems | |
| EP3300235B1 (en) | Voltage regulator | |
| KR101387300B1 (en) | LDO(Low Drop Out Regulator) having phase margin compensation means and phase margin compensation method using the LDO | |
| CN103296974B (en) | Self calibration buffer amplifier in voice coil motor driver and resistance finishing networking | |
| KR20030029443A (en) | Regulator circuit and control method thereof | |
| KR20160026558A (en) | Voltage regulator of low-drop-output and rf switch controll device having the same | |
| US20190305683A1 (en) | Boost and ldo hybrid converter with dual-loop control | |
| US20150061623A1 (en) | Voltage regulator of low-drop-output type and operation method of the same | |
| US7759905B2 (en) | Linear battery charger | |
| US9823678B1 (en) | Method and apparatus for low drop out voltage regulation | |
| US20160103464A1 (en) | Powering of a Charge with a Floating Node | |
| CN109557969B (en) | Multi-phase voltage regulator and method for operating a multi-phase voltage regulator |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CP03 | Change of name, title or address | ||
| CP03 | Change of name, title or address |
Address after: 201203 No. 12, Lane 647, Songtao Road, Shanghai China (Shanghai) Free Trade Pilot Area Patentee after: Juchen Semiconductor Co., Ltd. Address before: 201203 No. 12, Lane 647, Songtao Road, Zhangjiang High-tech Park, Pudong New Area, Shanghai Patentee before: Giantec Semiconductor Inc. |