CN103296974B - Self calibration buffer amplifier in voice coil motor driver and resistance finishing networking - Google Patents
Self calibration buffer amplifier in voice coil motor driver and resistance finishing networking Download PDFInfo
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- CN103296974B CN103296974B CN201310152041.8A CN201310152041A CN103296974B CN 103296974 B CN103296974 B CN 103296974B CN 201310152041 A CN201310152041 A CN 201310152041A CN 103296974 B CN103296974 B CN 103296974B
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Abstract
Self calibration buffer amplifier in a kind of voice coil motor driver and resistance finishing networking, be applied in voice coil motor lens driver system, the present invention solves the accuracy problem of chip system by self calibration buffer amplifier and self calibration AB class buffer amplifier, eliminate or greatly reduce DC power, thus reach good systemic-function, and save chip cost, utilize resistance finishing reduction networking, the networking imbalance and networking area optimized, thus reach the object improving network performance and reduce chip cost.
Description
Technical field
The present invention relates to the self calibration buffer amplifier in a kind of voice coil motor driver and resistance finishing networking, belong to integrated circuit (IC) design field, be applied in large scale integrated circuit, be especially applied in the chip system of high accuracy output current.
Background technology
Voice coil motor (VoiceCoilMotor) is widely used in electronic product.Be widely used in recent years in smart mobile phone and surface computer.
As shown in Figure 1, camera gun position is driven by voice coil motor, and lens location distance is proportional to the output current of voice coil motor driver.After voice coil motor driver power supply is connected, electrification reset device sets up initial condition and the bias current/voltage of driver chip, and the signal of being started working by chip delivers to picture signal processing main chip (not in the drawings) by I2C serial line interface.Picture signal processing main chip sends the instruction of driver output current by I2C serial line interface to voice coil motor driver chip, by 10bit Register, 10-bit current mode digital-to-analog converter is inserted in this instruction after driver receives output current instruction, by this digital to analog converter digital signal is converted to analog signal and by resistance R
2be converted to voltage signal.The voltage signal of node 11 is converted to required electric current by resistance R1 and delivers to voice coil motor by efferent duct MN0 by IOUT end by buffer amplifier, completes motor and drives process.Because buffer amplifier has stochastic inputs equivalence imbalance, cause between true output current and required output current and produce error, this error not only affects control precision, and can produce fixed current output at zero output current status.Because voice coil motor most time can at zero output current status, the output current of this state can increase the quiescent dissipation of voice coil motor driver, reduces service time of battery, brings great inconvenience to application.
A kind of conventional prior art is the equivalent inpnt imbalance being reduced and eliminate buffer amplifier by self-calibration circuit, and its operation principle as shown in Figure 2.When driver first time powers on, the positive input terminal 21 of buffer amplifier receives the voltage Vref of reference power supply generation by switch S 1, S2 switch opens.The negative input end 22 of buffer amplifier forms unit amplifying circuit by switch S 4, auto zero comparator, and self calibration controller and oscillator are started working.The input of buffer amplifier receives corresponding auto zero comparator input terminal.Auto zero comparator can differentiate the misalignment signal of below 20uV by the method for auto zero.Self calibration controller progressively changes the calibration device of buffer amplifier under the control of clock, until the voltage of auto zero comparator output terminal 26 changes polarity, completes self-calibration process.Self calibration controller ties down calibration device signal.The input offset voltage of buffer amplifier will be less than or equal to the resolution of auto zero comparator.Complete disposable self calibration rear drive device S1, S4 to be opened, S2, S3 and S5 are connected, chip is in normal operating conditions simultaneously.Driver input offset voltage after calibration is by elimination or reduce greatly.Thus reach system application requirement.
Voice coil motor driver (LensDriver) provides linear output current for controlling the position of voice coil motor camera lens, thus reaches automatic focus (AutoFocus) effect.Photographic film position is proportional to driver output current, and both are linear.High-gain amplifier is used for ensureing good focusing effect.Because the change amplifier of technique itself has input offset voltage, this offset voltage can introduce the output offset current of a direct current, affects the precision of output current.Offset voltage of amplifier can introduce direct current when zero code simultaneously.In most cases voice coil motor driver is operated in zero code status, and therefore amplifier input offset voltage can increase power consumption of driver, thus reduces the service time of battery power supply system.
Summary of the invention
Self calibration buffer amplifier in a kind of voice coil motor driver provided by the invention and resistance finishing networking, eliminate or greatly reduce amplifier input imbalance, enhance focusing effect, extend system service time, and decrease chip cost.
In order to achieve the above object, the invention provides a kind of high-gain self calibration buffer amplifier, this amplifier comprises the pre-amplification stage of circuit connection and collapsible amplifying stage;
This pre-amplification stage comprises current source I0, inputs pipe MP0 and MP1, and resistance finishing networking;
Current source I0 connects the source electrode of input to pipe MP0 and MP1, the grid of MP0 connects input INM, the grid of MP1 connects input INP, the input IN at resistance finishing networking connects the drain electrode of input to pipe MP0 and MP1, the output OUT ground connection VSS at resistance finishing networking, the Vreg end at resistance finishing networking connects power vd D.
Described resistance finishing networking comprises load resistor network and finishing network controller;
Described load resistor network comprises and is connected on resistance R between input IN and output OUT and some cell resistance Ri, i=0 successively, 1,2 ... N, each cell resistance Ri comprises field effect transistor M Di, i=0, and 1,2 ... N, MUi, i=0,1,2 ... N, and cell resistance Δ R/2
i, i=0,1,2 ... one end of the drain series cell resistance Ri of N, field effect transistor M Ui, the source electrode of the sources connected in parallel field effect transistor M Di of field effect transistor M Ui, the other end of the drain electrode parallel units resistance Ri of field effect transistor M Di;
Described finishing network controller comprises some control switch SUi and SDi, i=0,1,2 ... N, one end of described control switch SUi can select contact resistance to repair Vreg end or the earth terminal at networking, the other end of control switch SUi connects the grid of field effect transistor M Ui, and one end of described control switch SDi can select contact resistance to repair Vreg end or the earth terminal at networking, and the other end of control switch SDi connects the grid of field effect transistor M Di.
Described collapsible amplifying stage comprises field effect transistor M P2, MP3, MN0, MN1, MN2, MN3, MP4, MP5, MP6 and MP7, and bias voltage Vnc, Vns and Vpc;
Field effect transistor M P2 is connected current source I1 with the source electrode of MP3, the grid of MP2 connects the drain electrode of MP1, the grid of MP3 connects the drain electrode of MP0, the drain electrode of MP2 connects the source electrode of MN0, the drain electrode of MP3 connects the source electrode of MN1, the grid of MN0 with MN1 is connected the positive pole of bias voltage Vns, the grounded drain VSS of MN0, the grounded drain VSS of MN1, the grid of MN2 with MN3 is connected the positive pole of bias voltage Vnc, the drain electrode of MN2 connects the source electrode of MN0, the drain electrode of MN3 connects the source electrode of MN1, the source electrode of MP4 with MP5 is connected power vd D, the grid of MP4 with MP5 is connected the drain electrode of MP6, the drain electrode of MP4 connects the source electrode of MP6, the drain electrode of MP5 connects the source electrode of MP7, the grid of MP6 with MP7 is connected the positive pole of bias voltage Vpc, the drain electrode of MP6 connects the source electrode of MN2, the drain electrode of MP7 connects the source electrode of MN3, for output OUT.
The present invention also provides a kind of high-gain self calibration buffer amplifier of simplification, and this amplifier comprises input to pipe MP0 and MP1, resistance finishing networking, and collapsible amplifying stage;
Current source I1 connects the source electrode of input to pipe MP0 and MP1, the grid of MP0 connects input INM, the grid of MP1 connects input INP, the input IN at resistance finishing networking connects the drain electrode of transistor MN0 and MN1, the output OUT ground connection VSS at resistance finishing networking, the Vreg end at resistance finishing networking connects power vd D.
Described resistance finishing networking comprises load resistor network and finishing network controller;
Described load resistor network comprises and is connected on resistance R between input IN and output OUT and some cell resistance Ri, i=0 successively, 1,2 ... N, each cell resistance Ri comprises field effect transistor M Di, i=0, and 1,2 ... N, MUi, i=0,1,2 ... N, and cell resistance Δ R/2
i, i=0,1,2 ... one end of the drain series cell resistance Ri of N, field effect transistor M Ui, the source electrode of the sources connected in parallel field effect transistor M Di of field effect transistor M Ui, the other end of the drain electrode parallel units resistance Ri of field effect transistor M Di;
Described finishing network controller comprises some control switch SUi and SDi, i=0,1,2 ... N, one end of described control switch SUi can select contact resistance to repair Vreg end or the earth terminal at networking, the other end of control switch SUi connects the grid of field effect transistor M Ui, and one end of described control switch SDi can select contact resistance to repair Vreg end or the earth terminal at networking, and the other end of control switch SDi connects the grid of field effect transistor M Di.
Described collapsible amplifying stage comprises field effect transistor M P2, MP3, MN0, MN1, MN2, MN3, MP4 and MP5, and bias voltage Vnc, Vns and Vpc;
Field effect transistor M N0 is connected the positive pole of bias voltage Vns with the grid of MN1, the source electrode of MN0 connects the drain electrode of MP0, the source electrode of MN1 connects the drain electrode of MP1, the grid of MN2 with MN3 is connected the positive pole of bias voltage Vnc, the drain electrode of MN2 connects the source electrode of MN0, the drain electrode of MN3 connects the source electrode of MN1, the source electrode of MP2 with MP3 is connected power vd D, the grid of MP2 with MP3 is connected the drain electrode of MP4, the grid of MP4 with MP5 is connected the positive pole of bias voltage Vpc, the drain electrode of MP4 connects the source electrode of MN2, and the drain electrode of MP5 connects the source electrode of MN3, is output OUT.
The present invention also provides a kind of AB class high-gain self calibration buffer amplifier, and this amplifier comprises the pre-amplification stage of circuit connection and collapsible amplifying stage;
This pre-amplification stage comprises current source I0, inputs pipe MP0 and MP1, and resistance finishing networking;
Current source I0 connects the source electrode of input to pipe MP0 and MP1, the grid of MP0 connects input INM, the grid of MP1 connects input INP, the input IN at resistance finishing networking connects the drain electrode of input to pipe MP0 and MP1, the output OUT ground connection VSS at resistance finishing networking, the Vreg end at resistance finishing networking connects power vd D.
Described resistance finishing networking comprises load resistor network and finishing network controller;
Described load resistor network comprises and is connected on resistance R between input IN and output OUT and some cell resistance Ri, i=0 successively, 1,2 ... N, each cell resistance Ri comprises field effect transistor M Di, i=0, and 1,2 ... N, MUi, i=0,1,2 ... N, and cell resistance Δ R/2
i, i=0,1,2 ... one end of the drain series cell resistance Ri of N, field effect transistor M Ui, the source electrode of the sources connected in parallel field effect transistor M Di of field effect transistor M Ui, the other end of the drain electrode parallel units resistance Ri of field effect transistor M Di;
Described finishing network controller comprises some control switch SUi and SDi, i=0,1,2 ... N, one end of described control switch SUi can select contact resistance to repair Vreg end or the earth terminal at networking, the other end of control switch SUi connects the grid of field effect transistor M Ui, and one end of described control switch SDi can select contact resistance to repair Vreg end or the earth terminal at networking, and the other end of control switch SDi connects the grid of field effect transistor M Di.
Described collapsible amplifying stage comprises field effect transistor M P2, MP3, MN0, MN1, MN2, MN3, MP4, MP5, MP6, MP7, AB class bias structure, MP8 and MN4, and bias voltage Vnc, Vns and Vpc;
Field effect transistor M P2 is connected current source I1 with the source electrode of MP3, the grid of MP2 connects the drain electrode of MP1, the grid of MP3 connects the drain electrode of MP0, the drain electrode of MP2 connects the source electrode of MN0, the drain electrode of MP3 connects the source electrode of MN1, the grid of MN0 with MN1 is connected the positive pole of bias voltage Vns, the grounded drain VSS of MN0, the grounded drain VSS of MN1, the grid of MN2 with MN3 is connected the positive pole of bias voltage Vnc, the drain electrode of MN2 connects the source electrode of MN0, the drain electrode of MN3 connects the source electrode of MN1, the source electrode of MN2 with MN3 is connected AB class bias structure, the source electrode of MP4 with MP5 is connected power vd D, the grid of MP4 with MP5 is connected the drain electrode of MP6, the drain electrode of MP4 connects the source electrode of MP6, the drain electrode of MP5 connects the source electrode of MP7, the grid of MP6 with MP7 is connected the positive pole of bias voltage Vpc, the drain electrode of MP6 with MP7 is connected AB class bias structure, the source electrode of MP8 connects power vd D, the grid of MP8 connects the drain electrode of MP7, the drain electrode of MP8 connects the source electrode of MN4, for output OUT, the grid of MN4 connects the source electrode of MN3, the grounded drain VSS of MN4.
The present invention also provides a kind of AB class high-gain self calibration buffer amplifier of simplification, and this amplifier comprises input to pipe MP0 and MP1, resistance finishing networking, and collapsible amplifying stage;
Current source I1 connects the source electrode of input to pipe MP0 and MP1, the grid of MP0 connects input INM, the grid of MP1 connects input INP, the input IN at resistance finishing networking connects the drain electrode of transistor MN0 and MN1, the output OUT ground connection VSS at resistance finishing networking, the Vreg end at resistance finishing networking connects power vd D.
Described resistance finishing networking comprises load resistor network and finishing network controller;
Described load resistor network comprises and is connected on resistance R between input IN and output OUT and some cell resistance Ri, i=0 successively, 1,2 ... N, each cell resistance Ri comprises field effect transistor M Di, i=0, and 1,2 ... N, MUi, i=0,1,2 ... N, and cell resistance Δ R/2
i, i=0,1,2 ... one end of the drain series cell resistance Ri of N, field effect transistor M Ui, the source electrode of the sources connected in parallel field effect transistor M Di of field effect transistor M Ui, the other end of the drain electrode parallel units resistance Ri of field effect transistor M Di;
Described finishing network controller comprises some control switch SUi and SDi, i=0,1,2 ... N, one end of described control switch SUi can select contact resistance to repair Vreg end or the earth terminal at networking, the other end of control switch SUi connects the grid of field effect transistor M Ui, and one end of described control switch SDi can select contact resistance to repair Vreg end or the earth terminal at networking, and the other end of control switch SDi connects the grid of field effect transistor M Di.
Described collapsible amplifying stage comprises field effect transistor M P2, MP3, MN0, MN1, MN2, MN3, MP4, MP5, AB class bias structure, MP8 and MN4, and bias voltage Vnc, Vns and Vpc;
Field effect transistor M N0 is connected the positive pole of bias voltage Vns with the grid of MN1, the source electrode of MN0 connects the drain electrode of MP0, the source electrode of MN1 connects the drain electrode of MP1, the grid of MN2 with MN3 is connected the positive pole of bias voltage Vnc, the drain electrode of MN2 connects the source electrode of MN0, the drain electrode of MN3 connects the source electrode of MN1, the source electrode of MN2 with MN3 is connected AB class bias structure, the source electrode of MP2 with MP3 is connected power vd D, the grid of MP2 with MP3 is connected the drain electrode of MP4, the grid of MP4 with MP5 is connected the positive pole of bias voltage Vpc, the drain electrode of MP4 with MP5 is connected AB class bias structure, the source electrode of MP8 connects power vd D, the grid of MP8 connects the drain electrode of MP5, the drain electrode of MP8 connects the source electrode of MN4, for output OUT, the grid of MN4 connects the source electrode of MN3, the grounded drain VSS of MN4.
The present invention eliminates or greatly reduces amplifier input imbalance, enhances focusing effect, extends system service time, and decrease chip cost.
Accompanying drawing explanation
Fig. 1 is the circuit structure diagram of voice coil motor lens driver in background technology.
Fig. 2 is the circuit diagram of the self-calibration circuit in background technology in voice coil motor lens driver.
Fig. 3 is the circuit diagram of the high-gain self calibration buffer amplifier in the present invention.
Fig. 4 is the circuit diagram at the resistance finishing networking of self calibration buffer amplifier in the present invention.
Fig. 5 is the circuit diagram of the high-gain self calibration buffer amplifier of a kind of simplification in the present invention.
Fig. 6 is the circuit diagram of the AB class high-gain self calibration buffer amplifier in the present invention.
Fig. 7 is the circuit diagram of the AB class high-gain self calibration buffer amplifier of a kind of simplification in the present invention.
Embodiment
Following according to Fig. 2 ~ Fig. 7, illustrate preferred embodiment of the present invention.
As shown in Figure 3, the invention provides a kind of high-gain self calibration buffer amplifier, this amplifier comprises the pre-amplification stage of circuit connection and collapsible amplifying stage.
This pre-amplification stage comprises current source I0, inputs pipe MP0 and MP1, and resistance finishing networking.
Current source I0 connects the source electrode of input to pipe MP0 and MP1, the grid of MP0 connects input INM, the grid of MP1 connects input INP, as shown in Figure 4, the input IN at resistance finishing networking connects the drain electrode of input to pipe MP0 and MP1, the output OUT ground connection VSS at resistance finishing networking, the Vreg end at resistance finishing networking connects power vd D.
In the present embodiment, Vreg holds the output of connecting linear pressurizer.
This collapsible amplifying stage comprises field effect transistor M P2, MP3, MN0, MN1, MN2, MN3, MP4, MP5, MP6 and MP7, and bias voltage Vnc, Vns and Vpc.
Field effect transistor M P2 is connected current source I1 with the source electrode of MP3, the grid of MP2 connects the drain electrode of MP1, the grid of MP3 connects the drain electrode of MP0, the drain electrode of MP2 connects the source electrode of MN0, the drain electrode of MP3 connects the source electrode of MN1, the grid of MN0 with MN1 is connected the positive pole of bias voltage Vns, the grounded drain VSS of MN0, the grounded drain VSS of MN1, the grid of MN2 with MN3 is connected the positive pole of bias voltage Vnc, the drain electrode of MN2 connects the source electrode of MN0, the drain electrode of MN3 connects the source electrode of MN1, the source electrode of MP4 with MP5 is connected power vd D, the grid of MP4 with MP5 is connected the drain electrode of MP6, the drain electrode of MP4 connects the source electrode of MP6, the drain electrode of MP5 connects the source electrode of MP7, the grid of MP6 with MP7 is connected the positive pole of bias voltage Vpc, the drain electrode of MP6 connects the source electrode of MN2, the drain electrode of MP7 connects the source electrode of MN3, for output OUT.
Described resistance finishing networking comprises load resistor network and finishing network controller.
As shown in Figure 4, described load resistor network comprises and is connected on resistance R between input IN and output OUT and some cell resistance Ri(i=0 successively, 1,2 ... N) each cell resistance Ri comprises field effect transistor M Di(i=0,1,2 ... N), MUi(i=0,1,2 ... and cell resistance Δ R/2 N)
i(i=0,1,2 ... N), one end of the drain series cell resistance Ri of field effect transistor M Ui, the source electrode of the sources connected in parallel field effect transistor M Di of field effect transistor M Ui, the other end of the drain electrode parallel units resistance Ri of field effect transistor M Di.
Described finishing network controller comprises some control switch SUi and SDi(i=0,1,2 ... N), one end of described control switch SUi can select contact resistance to repair Vreg end or the earth terminal at networking, the other end of control switch SUi connects the grid of field effect transistor M Ui, one end of described control switch SDi can select contact resistance to repair Vreg end or the earth terminal at networking, and the other end of control switch SDi connects the grid of field effect transistor M Di.
Some control switch SU in described finishing network controller
iand SD
iundertaken controlling (as shown in Figure 2) by self calibration controller, as shown in Figure 3, self calibration controller sends control bit br
i(i=0,1,2 ... and bl N)
i(i=0,1,2 ... N) control switch SU is distinguished
iand SD
i, control bit br
iand bl
ivalue be 0 or 1, as control bit br
iand bl
ivalue when being 0, switch S U
iand SD
iground connection, as control bit br
iand bl
ivalue when being 1, switch S U
iand SD
iconnect high potential.
When self calibration starts, make switch S U0, SU1 ... SUN ground connection, field effect transistor M U0, MU1 ... MUN ends; Make switch S D0, SD1 ... SDN meets high potential Vreg, field effect transistor M D0, MD1 ... MDN connects.Resistance finishing networking total resistance value is Rm=R+N*Ron+ Σ bmi* (Δ R/2
i), wherein, m=r or l, i=0 ... N, Ron are field effect transistor M U0, MU1 ... MUN and MD0, MD1 ... the conduction resistance value of MDN.Finishing resistance value is with Δ R/2
nfor minimum unit, 2 systems increase.The resolution at this resistance finishing networking is determined by the pre-amplification stage bias current I0 in Fig. 3 and minimum finishing unit of resistance unit, and under first approximation, offset voltage is Δ V ≈ (I0/2) * (Δ R/2
n), generally we choose the resolution that minimum resolution is less than or equal to the auto zero comparator in Fig. 2.Offset voltage adjusting range is I0* Δ R*(1-1/2
n), this scope is generally taken as the maximum equivalent input offset voltage of buffer amplifier.Self-calibration process is from least unit unit, and when first clock, switch S UN receives high potential Vreg, turn-on field effect crystal switch MUN, simultaneously by switch S DN ground connection, makes field effect transistor switch MDN end, because MUN and MDN is measure-alike, whole finishing network resistance value increases Δ R/2
n, introduce the offset voltage of Δ V, in order to offset the imbalance of prime amplifier input to pipe.If the output polarity of auto zero comparator is constant, buffer amplifier offset voltage needs to continue finishing, repair controller under clock control afterwards and do linear search, until auto zero comparator change in polarity completes self-calibration process, self calibration controller ties down SU0, SU1 ... SUN and SD0, SD1 ... the corresponding state of SDN.Buffer amplifier input equivalence imbalance is finished within the resolution of auto zero comparator.By introducing MOS Switch Controller pipe MU0 and MD0 of N group same size in finishing unit, MU1 and MD1, MUN and MDN can eliminate the impact of MOS switch internal resistance on finishing source resistance value under first approximation, therefore can reduce the size of MOS switch greatly, thus reduce chip area.MOS Switch Controller pipe can introduce the imbalance of corresponding switch internal resistance, and the size choosing Switch Controller metal-oxide-semiconductor makes corresponding internal resistance lack of proper care much smaller than the resistance value Δ R/2 in minimum resistance source
n, to ensure the minimum resolution of repairing networking.The supply voltage of chip has larger excursion usually in systems in which, and the internal resistance of MOS switching tube, with mains voltage variations, will affect finishing resolution and the error of resistance network.For ensureing that resistance network has higher Power Supply Rejection Ratio, the turning-on voltage of MOS switch is received a stable voltage source V reg by the present invention, and this burning voltage is produced by the linear voltage regulator of chip internal, and magnitude of voltage is generally slightly less than chip minimum power source voltage value.Resistance finishing networking in the present invention will reduce chip area, have good Power Supply Rejection Ratio simultaneously.
Prime amplifier can not only provide the input mistuning calibration function of buffer amplifier, can also improve the gain of buffer amplifier.The gain of whole buffer amplifier up to more than 100dB, can meet requirement of system design.The equivalent inpnt imbalance of collapsible amplifying stage is reduced by pre-amplification stage, and decrease is directly proportional to the gain of pre-amplification stage.The equivalent inpnt imbalance of buffer amplifier is determined the imbalance of pipe MP0 and MP1 by the input of pre-amplification stage substantially.The size being changed load resistance Rr or Rl by finishing network controller can realize self-calibration function easily.
The self calibration of buffer amplifier compensates the imbalance of input to pipe by the ohmic load of change prime amplifier one end.Change input resistance value to need switching device to access in resistance network, the switching device be made up of field-effect transistor has internal resistance, and internal resistance is relevant with switching voltage with temperature, eliminate switch internal resistance impact usually can to realize by reducing switch internal resistance value, but a large amount of increase chip areas is increased product cost by the method.
Therefore, the present invention also provides a kind of high-gain self calibration buffer amplifier of simplification, and as shown in Figure 5, this amplifier comprises input to pipe MP0 and MP1, resistance finishing networking, and collapsible amplifying stage.
Current source I1 connects the source electrode of input to pipe MP0 and MP1, the grid of MP0 connects input INM, the grid of MP1 connects input INP, the input IN at resistance finishing networking connects the drain electrode of transistor MN0 and MN1, the output OUT ground connection VSS at resistance finishing networking, the Vreg end at resistance finishing networking connects power vd D.
This collapsible amplifying stage comprises field effect transistor M P2, MP3, MN0, MN1, MN2, MN3, MP4 and MP5, and bias voltage Vnc, Vns and Vpc.
Field effect transistor M N0 is connected the positive pole of bias voltage Vns with the grid of MN1, the source electrode of MN0 connects the drain electrode of MP0, the source electrode of MN1 connects the drain electrode of MP1, the grid of MN2 with MN3 is connected the positive pole of bias voltage Vnc, the drain electrode of MN2 connects the source electrode of MN0, the drain electrode of MN3 connects the source electrode of MN1, the source electrode of MP2 with MP3 is connected power vd D, the grid of MP2 with MP3 is connected the drain electrode of MP4, the grid of MP4 with MP5 is connected the positive pole of bias voltage Vpc, the drain electrode of MP4 connects the source electrode of MN2, and the drain electrode of MP5 connects the source electrode of MN3, is output OUT.
Described resistance finishing networking comprises load resistor network and finishing network controller.
As shown in Figure 4, described load resistor network comprises and is connected on resistance R between input IN and output OUT and some cell resistance Ri(i=0 successively, 1,2 ... N, each cell resistance Ri comprises field effect transistor M Di(i=0, and 1,2 ... N, MUi(i=0,1,2 ... and cell resistance Δ R/2 N)
i(i=0,1,2 ... N), one end of the drain series cell resistance Ri of field effect transistor M Ui, the source electrode of the sources connected in parallel field effect transistor M Di of field effect transistor M Ui, the other end of the drain electrode parallel units resistance Ri of field effect transistor M Di.
Described finishing network controller comprises some control switch SUi and SDi(i=0,1,2 ... N), one end of described control switch SUi can select contact resistance to repair Vreg end or the earth terminal at networking, the other end of control switch SUi connects the grid of field effect transistor M Ui, one end of described control switch SDi can select contact resistance to repair Vreg end or the earth terminal at networking, and the other end of control switch SDi connects the grid of field effect transistor M Di.
The high-gain self calibration buffer amplifier of this simplification, adopts collapsible amplifier architecture, compares the buffer amplifier of Fig. 3, this construction reduce pre-amplification stage, thus reduce chip area, owing to removing pre-amplification stage, whole amplifier gain reduces, but still can reach system requirements.Be placed in MN0 and MN1 source owing to resistance to be repaired networking, form source degeneracy, imbalance and the noise contribution of MN0 and MN1 can be reduced.Whole amplifier imbalance is still determined the imbalance of pipe MP0 and MP1 by input.Source degeneracy improves the voltage of node 511 and 512, and finishing network resistance value can not be too large.Too high 511 and 512 node voltages will force input to be operated in outside saturation region to pipe MP0 and MP1, and amplifier was lost efficacy.Therefore the finishing scope of this structure is less than the amplifier finishing scope of Fig. 3.The self-calibration process of this amplifier is identical with front described principle.
When lens driver output current is less, the voltage of Fig. 1 interior joint 12 is lower, and because efferent duct MN0 size is very large, the voltage of node 10 can be lower in some techniques, and the output stage N field effect transistor end of buffer amplifier can be operated in non-saturated region.As shown in Figure 3, when output OUT voltage drop can occur in low temperature environment to being less than this situation of 0.3V(, when low output current and shock processing processing procedure), MN1 and MN3 is forced to be operated in non-saturated region, amplifier gain declines, to produce new equivalent offset voltage, make driver have output current in such cases, not only influential system precision can increase chip power-consumption simultaneously.
For solving problems, the present invention also provides a kind of AB class high-gain self calibration buffer amplifier, and as shown in Figure 6, this amplifier comprises the pre-amplification stage of circuit connection and collapsible amplifying stage.
This pre-amplification stage comprises current source I0, inputs pipe MP0 and MP1, and resistance finishing networking.
Current source I0 connects the source electrode of input to pipe MP0 and MP1, the grid of MP0 connects input INM, the grid of MP1 connects input INP, the input IN at resistance finishing networking connects the drain electrode of input to pipe MP0 and MP1, the output OUT ground connection VSS at resistance finishing networking, the Vreg end at resistance finishing networking connects power vd D.
This collapsible amplifying stage comprises field effect transistor M P2, MP3, MN0, MN1, MN2, MN3, MP4, MP5, MP6, MP7, AB class bias structure, MP8 and MN4, and bias voltage Vnc, Vns and Vpc.
Field effect transistor M P2 is connected current source I1 with the source electrode of MP3, the grid of MP2 connects the drain electrode of MP1, the grid of MP3 connects the drain electrode of MP0, the drain electrode of MP2 connects the source electrode of MN0, the drain electrode of MP3 connects the source electrode of MN1, the grid of MN0 with MN1 is connected the positive pole of bias voltage Vns, the grounded drain VSS of MN0, the grounded drain VSS of MN1, the grid of MN2 with MN3 is connected the positive pole of bias voltage Vnc, the drain electrode of MN2 connects the source electrode of MN0, the drain electrode of MN3 connects the source electrode of MN1, the source electrode of MN2 with MN3 is connected AB class bias structure, the source electrode of MP4 with MP5 is connected power vd D, the grid of MP4 with MP5 is connected the drain electrode of MP6, the drain electrode of MP4 connects the source electrode of MP6, the drain electrode of MP5 connects the source electrode of MP7, the grid of MP6 with MP7 is connected the positive pole of bias voltage Vpc, the drain electrode of MP6 with MP7 is connected AB class bias structure, the source electrode of MP8 connects power vd D, the grid of MP8 connects the drain electrode of MP7, the drain electrode of MP8 connects the source electrode of MN4, for output OUT, the grid of MN4 connects the source electrode of MN3, the grounded drain VSS of MN4.
Described resistance finishing networking comprises load resistor network and finishing network controller.
As shown in Figure 4, described load resistor network comprises and is connected on resistance R between input IN and output OUT and some cell resistance Ri(i=0 successively, 1,2 ... N) each cell resistance Ri comprises field effect transistor M Di(i=0,1,2 ... N), MUi(i=0,1,2 ... and cell resistance Δ R/2 N)
i(i=0,1,2 ... N), one end of the drain series cell resistance Ri of field effect transistor M Ui, the source electrode of the sources connected in parallel field effect transistor M Di of field effect transistor M Ui, the other end of the drain electrode parallel units resistance Ri of field effect transistor M Di.
Described finishing network controller comprises some control switch SUi and SDi(i=0,1,2 ... N), one end of described control switch SUi can select contact resistance to repair Vreg end or the earth terminal at networking, the other end of control switch SUi connects the grid of field effect transistor M Ui, one end of described control switch SDi can select contact resistance to repair Vreg end or the earth terminal at networking, and the other end of control switch SDi connects the grid of field effect transistor M Di.
The output of this AB class high-gain self calibration buffer amplifier can be operated in positive-negative power voltage, even if output OUT is reduced to zero, self calibration buffer amplifier still can keep very high gain, thus ensures that driver normally works when low output voltage.
The present invention also provides a kind of AB class high-gain self calibration buffer amplifier of simplification, and as shown in Figure 7, this amplifier comprises input to pipe MP0 and MP1, resistance finishing networking, and collapsible amplifying stage.
Current source I1 connects the source electrode of input to pipe MP0 and MP1, the grid of MP0 connects input INM, the grid of MP1 connects input INP, the input IN at resistance finishing networking connects the drain electrode of transistor MN0 and MN1, the output OUT ground connection VSS at resistance finishing networking, the Vreg end at resistance finishing networking connects power vd D.
This collapsible amplifying stage comprises field effect transistor M P2, MP3, MN0, MN1, MN2, MN3, MP4, MP5, AB class bias structure, MP8 and MN4, and bias voltage Vnc, Vns and Vpc.
Field effect transistor M N0 is connected the positive pole of bias voltage Vns with the grid of MN1, the source electrode of MN0 connects the drain electrode of MP0, the source electrode of MN1 connects the drain electrode of MP1, the grid of MN2 with MN3 is connected the positive pole of bias voltage Vnc, the drain electrode of MN2 connects the source electrode of MN0, the drain electrode of MN3 connects the source electrode of MN1, the source electrode of MN2 with MN3 is connected AB class bias structure, the source electrode of MP2 with MP3 is connected power vd D, the grid of MP2 with MP3 is connected the drain electrode of MP4, the grid of MP4 with MP5 is connected the positive pole of bias voltage Vpc, the drain electrode of MP4 with MP5 is connected AB class bias structure, the source electrode of MP8 connects power vd D, the grid of MP8 connects the drain electrode of MP5, the drain electrode of MP8 connects the source electrode of MN4, for output OUT, the grid of MN4 connects the source electrode of MN3, the grounded drain VSS of MN4.
Described resistance finishing networking comprises load resistor network and finishing network controller.
As shown in Figure 4, described load resistor network comprises and is connected on resistance R between input IN and output OUT and some cell resistance Ri(i=0 successively, 1,2 ... N) each cell resistance Ri comprises field effect transistor M Di(i=0,1,2 ... N), MUi(i=0,1,2 ... and cell resistance Δ R/2 N)
i(i=0,1,2 ... N), one end of the drain series cell resistance Ri of field effect transistor M Ui, the source electrode of the sources connected in parallel field effect transistor M Di of field effect transistor M Ui, the other end of the drain electrode parallel units resistance Ri of field effect transistor M Di.
Described finishing network controller comprises some control switch SUi and SDi(i=0,1,2 ... N), one end of described control switch SUi can select contact resistance to repair Vreg end or the earth terminal at networking, the other end of control switch SUi connects the grid of field effect transistor M Ui, one end of described control switch SDi can select contact resistance to repair Vreg end or the earth terminal at networking, and the other end of control switch SDi connects the grid of field effect transistor M Di.
The present invention can be applied in voice coil motor lens driver system, the present invention solves the accuracy problem of chip system by self calibration buffer amplifier and self calibration AB class buffer amplifier, eliminate or greatly reduce DC power, thus reach good systemic-function, and save chip cost.The present invention utilizes resistance finishing reduction networking, networking imbalance and the networking area of optimization, thus reaches the object improving network performance and reduce chip cost.
Although content of the present invention has done detailed introduction by above preferred embodiment, will be appreciated that above-mentioned description should not be considered to limitation of the present invention.After those skilled in the art have read foregoing, for multiple amendment of the present invention and substitute will be all apparent.Therefore, protection scope of the present invention should be limited to the appended claims.
Claims (6)
1. a high-gain self calibration buffer amplifier, is characterized in that, this amplifier comprises the pre-amplification stage of circuit connection and collapsible amplifying stage;
This pre-amplification stage comprises current source I0, inputs pipe MP0 and MP1, and resistance finishing networking;
Current source I0 connects the source electrode of input to pipe MP0 and MP1, the grid of MP0 connects input INM, the grid of MP1 connects input INP, the input IN at resistance finishing networking connects the drain electrode of input to pipe MP0 and MP1, the output OUT ground connection VSS at resistance finishing networking, the Vreg end at resistance finishing networking connects power vd D;
Described resistance finishing networking comprises load resistor network and finishing network controller;
Described load resistor network comprises and is connected on resistance R between input IN and output OUT and some cell resistance Ri, i=0 successively, 1,2 ... N, each cell resistance Ri comprises field effect transistor M Di, i=0,1,2 ... N, MUi, i=0,1,2 ... N, and cell resistance Δ R/2
i, i=0,1,2 ... the drain series cell resistance Δ R/2 of N, field effect transistor M Ui
ione end, the source electrode of the sources connected in parallel field effect transistor M Di of field effect transistor M Ui, the drain electrode parallel units resistance Δ R/2 of field effect transistor M Di
ithe other end;
Described finishing network controller comprises some control switch SUi and SDi, i=0,1,2 ... N, one end of described control switch SUi can select contact resistance to repair Vreg end or the earth terminal at networking, the other end of control switch SUi connects the grid of field effect transistor M Ui, and one end of described control switch SDi can select contact resistance to repair Vreg end or the earth terminal at networking, and the other end of control switch SDi connects the grid of field effect transistor M Di.
2. high-gain self calibration buffer amplifier as claimed in claim 1, it is characterized in that, described collapsible amplifying stage comprises field effect transistor M P2, MP3, MN0, MN1, MN2, MN3, MP4, MP5, MP6 and MP7, and bias voltage Vnc, Vns and Vpc;
Field effect transistor M P2 is connected current source I1 with the source electrode of MP3, the grid of MP2 connects the drain electrode of MP1, the grid of MP3 connects the drain electrode of MP0, the drain electrode of MP2 connects the source electrode of MN0, the drain electrode of MP3 connects the source electrode of MN1, the grid of MN0 with MN1 is connected the positive pole of bias voltage Vns, the grounded drain VSS of MN0, the grounded drain VSS of MN1, the grid of MN2 with MN3 is connected the positive pole of bias voltage Vnc, the drain electrode of MN2 connects the source electrode of MN0, the drain electrode of MN3 connects the source electrode of MN1, the source electrode of MP4 with MP5 is connected power vd D, the grid of MP4 with MP5 is connected the drain electrode of MP6, the drain electrode of MP4 connects the source electrode of MP6, the drain electrode of MP5 connects the source electrode of MP7, the grid of MP6 with MP7 is connected the positive pole of bias voltage Vpc, the drain electrode of MP6 connects the source electrode of MN2, the drain electrode of MP7 connects the source electrode of MN3, for output OUT.
3. the high-gain self calibration buffer amplifier simplified, is characterized in that, this amplifier comprises input to pipe MP0 and MP1, resistance finishing networking, and collapsible amplifying stage;
Current source I1 connects the source electrode of input to pipe MP0 and MP1, the drain electrode of MP0 with MP1 is connected collapsible amplifying stage, the grid of MP0 connects input INM, the grid of MP1 connects input INP, the input IN at resistance finishing networking connects the drain electrode of transistor MN0 and MN1, the output OUT ground connection VSS at resistance finishing networking, the Vreg end at resistance finishing networking connects power vd D;
Described resistance finishing networking comprises load resistor network and finishing network controller;
Described load resistor network comprises and is connected on resistance R between input IN and output OUT and some cell resistance Ri, i=0 successively, 1,2 ... N, each cell resistance Ri comprises field effect transistor M Di, i=0,1,2 ... N, MUi, i=0,1,2 ... N, and cell resistance Δ R/2
i, i=0,1,2 ... the drain series cell resistance Δ R/2 of N, field effect transistor M Ui
ione end, the source electrode of the sources connected in parallel field effect transistor M Di of field effect transistor M Ui, the drain electrode parallel units resistance Δ R/2 of field effect transistor M Di
ithe other end;
Described finishing network controller comprises some control switch SUi and SDi, i=0,1,2 ... N, one end of described control switch SUi can select contact resistance to repair Vreg end or the earth terminal at networking, the other end of control switch SUi connects the grid of field effect transistor M Ui, and one end of described control switch SDi can select contact resistance to repair Vreg end or the earth terminal at networking, and the other end of control switch SDi connects the grid of field effect transistor M Di.
4. the high-gain self calibration buffer amplifier simplified as claimed in claim 3, it is characterized in that, described collapsible amplifying stage comprises field effect transistor M P2, MP3, MN0, MN1, MN2, MN3, MP4 and MP5, and bias voltage Vnc, Vns and Vpc;
Field effect transistor M N0 is connected the positive pole of bias voltage Vns with the grid of MN1, the source electrode of MN0 connects the drain electrode of MP0, the source electrode of MN1 connects the drain electrode of MP1, the grid of MN2 with MN3 is connected the positive pole of bias voltage Vnc, the drain electrode of MN2 connects the source electrode of MN0, the drain electrode of MN3 connects the source electrode of MN1, the source electrode of MP2 with MP3 is connected power vd D, the grid of MP2 with MP3 is connected the drain electrode of MP4, the grid of MP4 with MP5 is connected the positive pole of bias voltage Vpc, the drain electrode of MP4 connects the source electrode of MN2, and the drain electrode of MP5 connects the source electrode of MN3, is output OUT.
5. an AB class high-gain self calibration buffer amplifier, is characterized in that, this amplifier comprises the pre-amplification stage of circuit connection and collapsible amplifying stage;
This pre-amplification stage comprises current source I0, inputs pipe MP0 and MP1, and resistance finishing networking;
Current source I0 connects the source electrode of input to pipe MP0 and MP1, the grid of MP0 connects input INM, the grid of MP1 connects input INP, the input IN at resistance finishing networking connects the drain electrode of input to pipe MP0 and MP1, the output OUT ground connection VSS at resistance finishing networking, the Vreg end at resistance finishing networking connects power vd D;
Described resistance finishing networking comprises load resistor network and finishing network controller;
Described load resistor network comprises and is connected on resistance R between input IN and output OUT and some cell resistance Ri, i=0 successively, 1,2 ... N, each cell resistance Ri comprises field effect transistor M Di, i=0,1,2 ... N, MUi, i=0,1,2 ... N, and cell resistance Δ R/2
i, i=0,1,2 ... the drain series cell resistance Δ R/2 of N, field effect transistor M Ui
ione end, the source electrode of the sources connected in parallel field effect transistor M Di of field effect transistor M Ui, the drain electrode parallel units resistance Δ R/2 of field effect transistor M Di
ithe other end;
Described finishing network controller comprises some control switch SUi and SDi, i=0,1,2 ... N, one end of described control switch SUi can select contact resistance to repair Vreg end or the earth terminal at networking, the other end of control switch SUi connects the grid of field effect transistor M Ui, and one end of described control switch SDi can select contact resistance to repair Vreg end or the earth terminal at networking, and the other end of control switch SDi connects the grid of field effect transistor M Di;
Described collapsible amplifying stage comprises field effect transistor M P2, MP3, MN0, MN1, MN2, MN3, MP4, MP5, MP6, MP7, AB class bias structure, MP8 and MN4, and bias voltage Vnc, Vns and Vpc;
Field effect transistor M P2 is connected current source I1 with the source electrode of MP3, the grid of MP2 connects the drain electrode of MP1, the grid of MP3 connects the drain electrode of MP0, the drain electrode of MP2 connects the source electrode of MN0, the drain electrode of MP3 connects the source electrode of MN1, the grid of MN0 with MN1 is connected the positive pole of bias voltage Vns, the grounded drain VSS of MN0, the grounded drain VSS of MN1, the grid of MN2 with MN3 is connected the positive pole of bias voltage Vnc, the drain electrode of MN2 connects the source electrode of MN0, the drain electrode of MN3 connects the source electrode of MN1, the source electrode of MN2 with MN3 is connected AB class bias structure, the source electrode of MP4 with MP5 is connected power vd D, the grid of MP4 with MP5 is connected the drain electrode of MP6, the drain electrode of MP4 connects the source electrode of MP6, the drain electrode of MP5 connects the source electrode of MP7, the grid of MP6 with MP7 is connected the positive pole of bias voltage Vpc, the drain electrode of MP6 with MP7 is connected AB class bias structure, the source electrode of MP8 connects power vd D, the grid of MP8 connects the drain electrode of MP7, the drain electrode of MP8 connects the source electrode of MN4, for output OUT, the grid of MN4 connects the source electrode of MN3, the grounded drain VSS of MN4.
6. the AB class high-gain self calibration buffer amplifier simplified, is characterized in that, this amplifier comprises input to pipe MP0 and MP1, resistance finishing networking, and collapsible amplifying stage;
Current source I1 connects the source electrode of input to pipe MP0 and MP1, the grid of MP0 connects input INM, the grid of MP1 connects input INP, the input IN at resistance finishing networking connects the drain electrode of transistor MN0 and MN1, the output OUT ground connection VSS at resistance finishing networking, the Vreg end at resistance finishing networking connects power vd D;
Described resistance finishing networking comprises load resistor network and finishing network controller;
Described load resistor network comprises and is connected on resistance R between input IN and output OUT and some cell resistance Ri, i=0 successively, 1,2 ... N, each cell resistance Ri comprises field effect transistor M Di, i=0,1,2 ... N, MUi, i=0,1,2 ... N, and cell resistance Δ R/2
i, i=0,1,2 ... the drain series cell resistance Δ R/2 of N, field effect transistor M Ui
ione end, the source electrode of the sources connected in parallel field effect transistor M Di of field effect transistor M Ui, the drain electrode parallel units resistance Δ R/2 of field effect transistor M Di
ithe other end;
Described finishing network controller comprises some control switch SUi and SDi, i=0,1,2 ... N, one end of described control switch SUi can select contact resistance to repair Vreg end or the earth terminal at networking, the other end of control switch SUi connects the grid of field effect transistor M Ui, and one end of described control switch SDi can select contact resistance to repair Vreg end or the earth terminal at networking, and the other end of control switch SDi connects the grid of field effect transistor M Di;
Described collapsible amplifying stage comprises field effect transistor M P2, MP3, MN0, MN1, MN2, MN3, MP4, MP5, AB class bias structure, MP8 and MN4, and bias voltage Vnc, Vns and Vpc;
Field effect transistor M N0 is connected the positive pole of bias voltage Vns with the grid of MN1, the source electrode of MN0 connects the drain electrode of MP0, the source electrode of MN1 connects the drain electrode of MP1, the grid of MN2 with MN3 is connected the positive pole of bias voltage Vnc, the drain electrode of MN2 connects the source electrode of MN0, the drain electrode of MN3 connects the source electrode of MN1, the source electrode of MN2 with MN3 is connected AB class bias structure, the source electrode of MP2 with MP3 is connected power vd D, the grid of MP2 with MP3 is connected the drain electrode of MP4, the grid of MP4 with MP5 is connected the positive pole of bias voltage Vpc, the drain electrode of MP4 with MP5 is connected AB class bias structure, the source electrode of MP8 connects power vd D, the grid of MP8 connects the drain electrode of MP5, the drain electrode of MP8 connects the source electrode of MN4, for output OUT, the grid of MN4 connects the source electrode of MN3, the grounded drain VSS of MN4.
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| CN106444948B (en) * | 2016-11-01 | 2017-12-12 | 无锡思泰迪半导体有限公司 | A kind of voice coil motor driving chip offset current and maximum output current bearing calibration |
| CN108718196B (en) * | 2018-08-01 | 2023-08-08 | 武汉韦尔半导体有限公司 | Operational amplifier offset self-calibration circuit applied to voice coil motor driving chip |
| CN110277966B (en) * | 2019-05-09 | 2023-03-14 | 上海类比半导体技术有限公司 | Self-calibration circuit and calibration method |
| CN114637354A (en) * | 2022-03-28 | 2022-06-17 | 杭州红芯微电子信息科技有限公司 | Trimming circuit for operational amplifier circuit |
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| US20020079854A1 (en) * | 2000-11-29 | 2002-06-27 | Yasushi Kitamura | Automatic gain adjustment for voice call motor back EMF monitor |
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| CN201781461U (en) * | 2010-08-19 | 2011-03-30 | 美凌微电子(上海)有限公司 | High-gain class AB operational amplifier for quiescent current accuracy control |
| CN201813423U (en) * | 2010-09-17 | 2011-04-27 | 惠州Tcl移动通信有限公司 | Mobile terminal with automatic focusing function and driving circuit thereof |
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Address after: 201203 No. 12, Lane 647, Songtao Road, Shanghai China (Shanghai) Free Trade Pilot Area Patentee after: Juchen Semiconductor Co., Ltd. Address before: 201203 No. 12, Lane 647, Songtao Road, Zhangjiang High-tech Park, Pudong New Area, Shanghai Patentee before: Giantec Semiconductor Inc. |