CN113708606B - PMOS access switch control circuit - Google Patents
PMOS access switch control circuit Download PDFInfo
- Publication number
- CN113708606B CN113708606B CN202110954122.4A CN202110954122A CN113708606B CN 113708606 B CN113708606 B CN 113708606B CN 202110954122 A CN202110954122 A CN 202110954122A CN 113708606 B CN113708606 B CN 113708606B
- Authority
- CN
- China
- Prior art keywords
- circuit
- voltage
- pmos
- pmos tube
- charge pump
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Classifications
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/08—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02J—CIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
- H02J7/00—Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries
- H02J7/007—Regulation of charging or discharging current or voltage
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M3/00—Conversion of dc power input into dc power output
- H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
- H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
- H02M3/10—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
- H02M3/145—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
- H02M3/155—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
- H02M3/156—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02J—CIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
- H02J2207/00—Indexing scheme relating to details of circuit arrangements for charging or depolarising batteries or for supplying loads from batteries
- H02J2207/20—Charging or discharging characterised by the power electronics converter
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
- Y02B40/00—Technologies aiming at improving the efficiency of home appliances, e.g. induction cooking or efficient technologies for refrigerators, freezers or dish washers
Abstract
The invention provides a PMOS access switch control circuit, comprising: the voltage clamping circuit, the charge pump voltage regulating circuit and the first PMOS tube are connected in series; the first end of the voltage clamping circuit, the input end of the charge pump voltage regulating circuit and the source electrode of the first PMOS tube are all connected with a power supply; the second end of the voltage clamping circuit and the output end of the charge pump voltage regulating circuit are both connected with the grid electrode of the first PMOS tube; and the drain electrode of the first PMOS tube is connected with the equipment to be charged. According to the invention, the voltage regulating circuit of the charge pump is arranged, so that the normal work of the PMOS tube can be ensured when the output voltage is lower than the grid-source voltage of the PMOS tube, and the power supply efficiency of the charger is further improved.
Description
Technical Field
The invention relates to the field of power supply control, in particular to a PMOS (P-channel metal oxide semiconductor) access switch control circuit.
Background
At present, the popularity of the rapid charging technology in portable intelligent mobile electronics such as smart phones, notebook computers, tablet computers and the like is higher and higher, especially, the USB PPS (Universal Serial Bus Programmable Power Supply) supports 20mV continuous voltage regulation in a range of 3.3V to 21V, and can support a battery direct charging technology.
When the adapter supports the USB PPS specification, the protocol requirement must support 20mV step continuous voltage regulation in the range of 3.3V to 21V. When the communication of the quick charging protocol between the adapter and the charging equipment is unsuccessful, the adapter must output zero potential, and when the charging equipment successfully communicates and applies for a power demand, the adapter can output a corresponding power according to the application of the charging equipment. Therefore, the output terminal of the USB PD adapter generally has a pass switch for controlling the power supply path.
The power supply path is typically implemented using either PMOS or NMOS. When a PMOS is used as a power path switch, as shown in fig. 1 in the prior art, when the PMOS is turned on, the gate voltage of the PMOS is pulled down, and meanwhile, a clamping circuit is added to ensure that the gate-source voltage is within the safe operating voltage range of the PMOS. If the PMOS gate-source voltage is 5V for normal operation, the gate-source voltage will be clamped to around 5V. If the charging equipment supports USB PPS, and simultaneously sends out a voltage application between 3.3V and 5V, the adapter outputs 3.3V to 5V according to the equipment application. When the charger outputs a voltage in a range of 3.3-5.0V, such as 3.3V, the gate voltage of the PMOS transistor can only be pulled to ground in the conventional method, and VGS =3.3V. When VGS =3.3V, the internal resistance of the PMOS transistor is increased due to the low gate-source voltage, which increases the power consumption of the PMOS channel, thereby reducing the power supply efficiency of the charger, even causing the charger to generate heat seriously, and causing the system to fail to work normally.
Disclosure of Invention
The invention aims to provide a PMOS (P-channel metal oxide semiconductor) access switch control circuit which can ensure that a PMOS (P-channel metal oxide semiconductor) tube works normally when the output voltage is lower than the grid-source voltage of the PMOS tube, thereby improving the power supply efficiency of a charger.
In order to achieve the purpose, the invention provides the following scheme:
a PMOS pass switch control circuit, comprising:
the voltage clamping circuit, the charge pump voltage regulating circuit and the first PMOS tube are connected in series;
the first end of the voltage clamping circuit, the input end of the charge pump voltage regulating circuit and the source electrode of the first PMOS tube are all connected with a power supply;
the second end of the voltage clamping circuit and the output end of the charge pump voltage regulating circuit are both connected with the grid electrode of the first PMOS tube;
and the drain electrode of the first PMOS tube is connected with the equipment to be charged.
Optionally, the voltage clamping circuit specifically includes:
n second PMOS tubes;
the grid electrode and the drain electrode of the ith second PMOS tube are both connected with the source electrode of the (i + 1) th second PMOS tube; i =1,.., n;
the source electrode of the 1 st second PMOS tube is used as the first end of the voltage clamping circuit and is connected with the power supply; and the grid electrode and the drain electrode of the nth second PMOS tube are connected as the second end of the voltage clamping circuit and are respectively connected with the output end of the charge pump voltage regulating circuit and the grid electrode of the first PMOS tube.
Optionally, the voltage regulating circuit of the charge pump specifically includes:
the device comprises an input voltage detection circuit, a PMOS gate drive circuit, a negative voltage charge pump and an additional voltage linear converter;
the input end of the input voltage detection circuit and the first input end of the additional voltage linear converter are connected as the input end of the charge pump voltage regulating circuit to be connected with the power supply;
the output end of the input voltage detection circuit is respectively connected with the second input end of the additional voltage linear converter, the input end of the PMOS gate drive circuit and the control end of the negative voltage charge pump;
the output end of the additional voltage linear converter is connected with the first port of the negative voltage charge pump;
the second port and the third port of the negative-voltage charge pump are both grounded;
and a fourth port of the negative-voltage charge pump is connected with the output end of the PMOS gate drive circuit, and is used as the output end of the charge pump voltage regulating circuit to be connected with the gate of the first PMOS tube.
Optionally, the input voltage detection circuit specifically includes:
a first resistor, a second resistor and a first operational amplifier;
the first end of the first resistor and the first end of the second resistor are connected with the positive input end of the first operational amplifier;
a second end of the first resistor is used as an input end of the input voltage detection circuit and is connected with the power supply;
the second end of the second resistor is grounded;
a negative input end of the first operational amplifier inputs a reference voltage; the output end of the first operational amplifier is used as the output end of the input voltage detection circuit and is respectively connected with the second input end of the additional voltage linear converter, the input end of the PMOS gate drive circuit and the control end of the negative voltage charge pump.
Optionally, the negative voltage charge pump specifically includes:
the first switch, the second switch, the third switch, the fourth switch and the flying capacitor;
the first end of the first switch and the first end of the second switch are both connected with the first end of the flying capacitor;
the first end of the third switch and the first end of the fourth switch are both connected with the second end of the flying capacitor;
the second end of the first switch is connected with the first port;
a second end of the second switch is connected with the second port;
a second end of the third switch is connected with the third port;
and the second end of the fourth switch is connected with the fourth port.
Optionally, the PMOS gate driving circuit specifically includes:
a pull-up circuit and a pull-down circuit;
the first end of the pull-up circuit is used as the input end of the PMOS grid electrode driving circuit and the output end of the input voltage detection circuit; the second end of the pull-up circuit is used as the output end of the PMOS gate drive circuit and is respectively connected with the gate of the first PMOS tube and the first end of the pull-down circuit; the second terminal of the pull-down circuit is grounded.
Optionally, the pull-up circuit specifically includes:
the first phase inverter and the third PMOS tube;
a power supply end of the first inverter is connected with a source electrode of the third PMOS tube to serve as a first end of the pull-up circuit, and the first end of the pull-up circuit is connected with a source electrode of the first PMOS tube; the input end of the first phase inverter is connected with the switch control signal of the first PMOS tube;
the output end of the first phase inverter is connected with the grid electrode of the third PMOS tube;
and the drain electrode of the third PMOS tube is used as the second end of the pull-up circuit and is connected with the first end of the pull-down circuit.
Optionally, the pull-down circuit specifically includes:
the fourth PMOS tube, the first NMOS tube and the second phase inverter;
the source electrode of the fourth PMOS tube is used as the first end of the pull-down circuit and is connected with the drain electrode of the third PMOS tube; the grid electrode of the fourth PMOS tube inputs a clamping level; the drain electrode of the fourth PMOS tube is connected with the drain electrode of the first NMOS tube;
the source electrode of the first NMOS tube is used as the second end of the pull-down circuit and grounded; the grid electrode of the first NMOS tube is connected with the output end of the second phase inverter;
and the input end of the second phase inverter is connected with the switch control signal of the first PMOS tube.
According to the specific embodiment provided by the invention, the invention discloses the following technical effects:
the invention provides a PMOS access switch control circuit, comprising: the invention provides a PMOS access switch control circuit, comprising: the charge pump voltage regulating circuit comprises a voltage clamping circuit, a charge pump voltage regulating circuit and a first PMOS (P-channel metal oxide semiconductor) tube; the first end of the voltage clamping circuit, the input end of the charge pump voltage regulating circuit and the source electrode of the first PMOS tube are all connected with a power supply; the second end of the voltage clamping circuit and the output end of the charge pump voltage regulating circuit are both connected with the grid electrode of the first PMOS tube; and the drain electrode of the first PMOS tube is connected with the equipment to be charged. According to the invention, the voltage regulating circuit of the charge pump is arranged, so that the normal work of the PMOS tube can be ensured when the output voltage is lower than the grid-source voltage of the PMOS tube, and the power supply efficiency of the charger is further improved.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings needed to be used in the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings without inventive exercise.
FIG. 1 is a prior art PMOS pass switch control circuit;
FIG. 2 is a PMOS pass switch control circuit in an embodiment of the invention;
FIG. 3 is a first circuit diagram of an additional voltage linear converter in an embodiment of the present invention;
FIG. 4 is a second circuit diagram of an additional voltage linear converter in an embodiment of the present invention;
FIG. 5 is a circuit diagram of a negative charge pump according to an embodiment of the present invention; FIG. 5 (a) is a control diagram of a negative voltage charge pump switch in an embodiment of the present invention; FIG. 5 (b) is a circuit diagram of a negative charge pump switch in an embodiment of the present invention;
FIG. 6 is a diagram of a PMOS gate driver circuit according to an embodiment of the present invention;
FIG. 7 is a circuit diagram of an input voltage detection circuit according to an embodiment of the present invention;
FIG. 8 is a diagram of a voltage clamp circuit in an embodiment of the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
The invention aims to provide a PMOS (P-channel metal oxide semiconductor) access switch control circuit which can ensure that a PMOS (P-channel metal oxide semiconductor) tube works normally when the output voltage is lower than the grid-source voltage of the PMOS tube, thereby improving the power supply efficiency of a charger.
In order to make the aforementioned objects, features and advantages of the present invention more comprehensible, the present invention is described in detail with reference to the accompanying drawings and the detailed description thereof.
Fig. 2 is a PMOS pass switch control circuit in an embodiment of the present invention, and as shown in fig. 2, the present invention provides a PMOS pass switch control circuit, including:
the voltage clamping circuit, the charge pump voltage regulating circuit and the first PMOS tube are connected in series;
the first end of the voltage clamping circuit, the input end of the charge pump voltage regulating circuit and the source electrode of the first PMOS tube are connected with a power supply;
the second end of the voltage clamping circuit and the output end of the charge pump voltage regulating circuit are both connected with the grid electrode of the first PMOS tube;
and the drain electrode of the first PMOS tube is connected with the equipment to be charged.
Fig. 8 is a diagram of a voltage clamping circuit according to an embodiment of the present invention, and as shown in fig. 8, the voltage clamping circuit provided in the present invention specifically includes:
n second PMOS tubes;
the grid electrode and the drain electrode of the ith second PMOS tube are both connected with the source electrode of the (i + 1) th second PMOS tube; i =1, n;
the source electrode of the 1 st second PMOS tube is used as the first end of the voltage clamping circuit and is connected with the power supply; and the grid electrode and the drain electrode of the nth second PMOS tube are connected as the second end of the voltage clamping circuit and are respectively connected with the output end of the charge pump voltage regulating circuit and the grid electrode of the first PMOS tube.
Wherein, the charge pump voltage regulating circuit specifically includes:
the device comprises an input voltage detection circuit, a PMOS gate drive circuit, a negative voltage charge pump and an additional voltage linear converter;
the input end of the input voltage detection circuit and the first input end of the additional voltage linear converter are connected as the input end of the charge pump voltage regulation circuit to be connected with the power supply;
the output end of the input voltage detection circuit is respectively connected with the second input end of the additional voltage linear converter, the input end of the PMOS gate drive circuit and the control end of the negative voltage charge pump;
the output end of the additional voltage linear converter is connected with the first port of the negative voltage charge pump;
the second port and the third port of the negative-pressure charge pump are both grounded;
and the fourth port of the negative voltage charge pump is connected with the output end of the PMOS gate drive circuit, and is used as the output end of the charge pump voltage regulation circuit to be connected with the gate of the first PMOS tube.
Fig. 7 is an input voltage detection circuit diagram in an embodiment of the present invention, and as shown in fig. 7, the input voltage detection circuit in the present invention specifically includes:
the circuit comprises a first resistor R1, a second resistor R2 and a first operational amplifier;
the first end of the first resistor and the first end of the second resistor are connected with the positive input end of the first operational amplifier;
the second end of the first resistor is used as the input end of the input voltage detection circuit and is connected with the power supply;
the second end of the second resistor is grounded;
a negative input end of the first operational amplifier inputs a reference voltage; the output end of the first operational amplifier is used as the output end of the input voltage detection circuit and is respectively connected with the second input end of the additional voltage linear converter, the input end of the PMOS gate drive circuit and the control end of the negative voltage charge pump.
Fig. 5 is a circuit diagram of a negative charge pump according to an embodiment of the present invention, and fig. 5 (a) is a control diagram of a negative charge pump switch according to an embodiment of the present invention; FIG. 5 (b) is a circuit diagram of a negative charge pump switch in an embodiment of the present invention; as shown in fig. 5, the negative voltage charge pump specifically includes:
the device comprises a first switch S1, a second switch S2, a third switch S3, a fourth switch S4 and a flying capacitor;
the first end of the first switch and the first end of the second switch are both connected with the first end of the flying capacitor;
the first end of the third switch and the first end of the fourth switch are both connected with the second end of the flying capacitor;
the second end of the first switch is connected with the control end;
the second end of the second switch is connected with the second port;
the second end of the third switch is connected with the third port;
and the second end of the fourth switch is connected with the fourth port.
Fig. 6 is a diagram of a PMOS gate driver circuit according to an embodiment of the invention, and as shown in fig. 6, the PMOS gate driver circuit according to the invention specifically includes:
a pull-up circuit and a pull-down circuit;
the first end of the pull-up circuit is used as the input end of the PMOS grid electrode driving circuit and the output end of the input voltage detection circuit; the second end of the pull-up circuit is used as the output end of the PMOS gate drive circuit and is respectively connected with the gate of the first PMOS tube and the first end of the pull-down circuit; the second terminal of the pull-down circuit is grounded.
Specifically, the pull-up circuit specifically includes:
a first phase inverter and a third PMOS tube M1;
the power supply end of the first inverter and the source electrode of the third PMOS tube are connected as the first end of the pull-up circuit and connected with the source electrode of the first PMOS tube; the input end of the first phase inverter is connected with the switch control signal of the first PMOS tube;
the output end of the first phase inverter is connected with the grid electrode of the third PMOS tube;
the drain electrode of the third PMOS tube is used as the second end of the pull-up circuit and is connected with the first end of the pull-down circuit.
The pull-down circuit specifically comprises:
a fourth PMOS tube M2, a first NMOS tube M3 and a second phase inverter;
a source electrode of the fourth PMOS tube is used as a first end of the pull-down circuit and is connected with a drain electrode of the third PMOS tube; the grid electrode of the fourth PMOS tube inputs a clamping level; the drain electrode of the fourth PMOS tube is connected with the drain electrode of the first NMOS tube;
the source electrode of the first NMOS tube is used as the second end of the pull-down circuit and is grounded; the grid electrode of the first NMOS tube is connected with the output end of the second phase inverter;
the input end of the second phase inverter is connected with the switch control signal of the first PMOS tube.
In addition, specific circuit diagrams of the additional voltage linear converter in the present invention are shown in fig. 3-4.
Specifically, in order to solve the disadvantages of the conventional PMOS pass switch control circuit, the present invention provides a pass control method and circuit for controlling the gate-source voltage of the PMOS transistor of the pass to be a constant value by using a charge pump according to the variation of the input voltage. Through the circuit, when the transmitted input power supply voltage VIN is low, the grid-source voltage of the channel PMOS tube can be kept at a certain voltage value, so that the internal resistance of the channel PMOS tube in the process of transmitting low power supply voltage is effectively reduced, the system efficiency is improved, and the system heating is reduced.
As shown in fig. 2, a detection circuit of the input power VIN, an LDO as an additional voltage linear converter, and a negative voltage charge pump are added on the basis of the conventional PMOS gate driving circuit and VGS clamping circuit.
The voltage clamping circuit is a circuit commonly used in the industry, and generally, a Zener diode can be used, the reverse breakdown voltage of the Zener diode is selected to be close to the maximum normal working voltage of a PMOS (P-channel metal oxide semiconductor) grid source, and the reverse breakdown voltage of the Zener diode can be used for realizing the function of the clamping circuit. The output of the PMOS gate drive circuit is connected to the PMOS gate, while one end is connected to the input voltage detection circuit. The PMOS gate driver circuit is also commonly used in the industry, and as shown in fig. 6, the PMOS transistor can be turned off and on by pulling up the PMOS gate and pulling down the NMOS gate. The input voltage detection circuit is connected to an input power VIN, the output of the input voltage detection circuit is connected to the additional voltage linear converter, meanwhile, the output of the input voltage detection circuit is connected to the PMOS gate drive circuit and the negative voltage charge pump, and a VIN detection signal is sent to the additional voltage linear converter, the PMOS gate drive circuit and the negative voltage charge pump. The input voltage detection circuit is a general circuit in the industry, and can detect the input voltage by using a divider resistor and a comparator. The control end of the additional voltage linear converter is connected to the input voltage detection circuit, the input end of the additional voltage linear converter is connected to VIN, and the output end of the additional voltage linear converter is connected to the negative voltage charge pump. The negative charge pump has a positive input connected to the output of the additional voltage linear converter and a negative output connected to the PMOS gate.
Assuming that the normal voltage of the grid source opening of the PMOS tube is VGS SET (typically 5V or 10V etc. are possible). When the input voltage detection circuit detects VIN>VGS SET At this time, the additional voltage linear converter is turned off and the negative voltage charge pump is turned off. The PMOS access switch control circuit works in the same way as the conventional control circuit, and the PMOS grid electrode is pulled down and pulled up by the PMOS grid electrode driving circuit to control the conduction and the disconnection of the PMOS tube. The gate-source voltage clamping circuit may be implemented with a corresponding reverse breakdown voltage zener diode. For example, the gate-source voltage of PMOS is 5V, and the reverse breakdown voltage is about 5VThe voltage clamping circuit ensures that VGS does not exceed VGS SET . When the input voltage detection circuit detects VIN<VGS SET When the voltage source voltage is reduced, the pull-down circuit of the PMOS gate drive circuit is turned off, the additional voltage linear converter starts to work, and VLDO = VGS is generated from VIN according to the change of VIN SET VIN and VLDO to a negative charge pump. The output end of the negative voltage charge pump is connected to the grid of the PMOS, the negative voltage charge pump receives the VLDO, and is controlled by the input voltage detection circuit to start working, and the grid is driven to VLDO = - (VGS) by the negative voltage charge pump SET -VIN), thereby achieving VGS = VIN + VLDO = VGS SET . The negative charge pump is shown in fig. 5, and the process of driving the gate to a negative potential is as follows: in the first phase, switches S1 and S3 are closed and S2 and S4 are open. The upper plate of the flying capacitor is connected to the output of the LDO by S1, and the lower plate is connected to the ground by S3. Thus the capacitor is charged by the LDO and the voltage difference across the capacitor equals VLDO. In the second phase, switches S1 and S3 are open and S2 and S4 are closed. The capacitor top plate is connected to ground by S2, the capacitor bottom plate is connected to output terminal VOUT by S4, and the charge pump output terminal VOUT is connected to the gate of the PMOS pass switch. Because the voltage at the two ends of the capacitor is kept unchanged, the upper pole plate of the capacitor is connected to the ground end, and the charge pump outputs negative voltage-VLDO at the VOUT end. The input VIN of the negative voltage charge pump is the output VLDO of the additional linear converter, wherein VLDO = VGS SET -VIN. The gate of the PMOS transistor will be driven to a negative potential- (VGS) SET -VIN). Therefore, the difference between the PMOS gate-source voltages is VGS = VIN + (VGS) SET -VIN)＝VGS SET . Thereby ensuring that the PMOS grid source voltage is maintained at VGS SET Therefore, the PMOS on-resistance is not increased along with the reduction of VIN.
Fig. 3 is a basic principle schematic of the additional voltage linear converter referred to in the present invention. When VIN is detected<VGS SET When VIN is found<VGS SET The circuit starts to operate. The voltage difference detection circuit detects VIN and VGS SET Is output simultaneously with a sum of VIN and VGS SET Voltage VR proportional to the difference of (1) as the subsequent stage LD O I.e. VR = K × (VGS) SET -VIN). Wherein K is a proportionality coefficient, and the subsequent LDO is from VIN according to VRProducing VLDO = VGS SET -VIN. The principle of LDO is well known and will not be described here.
FIG. 4 is a detailed description of FIG. 3, based on the principle of using an operational amplifier to convert VGS SET Conversion to one and VGS SET The proportional current is converted into a current source through a PMOS mirror image
Is applied to a resistor R to generate a sum VGS SET A proportional voltage. Meanwhile, VIN is converted into a current proportional to VIN by another operational amplifier, and then the current is converted into a current by PMOS current mirror and primary NMOS current mirror
And then to the same resistor terminal as the current source Isource. Thereby, a sum VGS can be generated on the resistor SET Voltage VR, VR = R × (Isource-Isink), i.e. VR = K × (VGS), proportional to the difference in VIN SET -VIN). The VR is transmitted to a later LDO, and the later LDO amplifies the VR to 1/K times to obtain VLDO = VGS SET -VIN。
Fig. 7 is an implementation of an input voltage detection circuit. The input voltage is divided by two resistors, and then the divided voltage signal is connected to the positive input end of a comparator, and the negative input end of the comparator is connected to a reference voltage for comparison, so that whether the input voltage is higher than VGS or not is detected SET . When VIN > VGS SET At time, the comparator outputs a high signal. When VIN is less than VGS SET When so, the comparator outputs a high signal. The voltage detection circuit is a well-known technology in the industry and has various implementation modes.
The simplest way of voltage clamping is to use a zener diode, implemented with a zener diode reverse breakdown voltage. When the voltage applied to the two ends of the Zener diode exceeds the reverse breakdown voltage of the Zener diode, the Zener diode breaks down in the reverse direction, and the voltage drop of the two ends is clamped at the reverse breakdown voltage. Such as the zener diode shown in fig. 6, functions as a PMOS gate-source voltage clamp. In addition, as shown in fig. 8, a plurality of MOS transistors may be connected in series to realize a clamping function of the PMOS gate-source voltage. The MOS tubes can be connected in series by NMOS or PMOS. In addition, the voltage clamping circuit can be realized by adopting a mode of connecting a diode or a triode in series, and the realization modes are all known in the industry of the voltage clamping circuit.
Further, simplification can be made on the basis of fig. 2, and the same purpose can be achieved. Wherein the additional voltage linear converter can be a general LDO with a fixed output voltage. For example, if the normal operation start-up voltage of PMOS is VGS SET Such as VGS SET =5V, the LDO voltage may be set to a fixed 3V. When the input voltage VIN is less than VGS SET When the LDO output is fixed 3V, VLDO =3V. The negative charge pump starts to work, pumping the gate voltage to a negative potential with VLDO =3V. Meanwhile, a Zener diode with reverse breakdown voltage of about 5V-6V is selected as a voltage clamping circuit. The gate-source voltage is clamped at the breakdown voltage of the zener diode due to the clamping zener diode, so the charge pump cannot pump the gate voltage to-3V. Therefore, the VGS voltage can be kept under a larger voltage difference, and the reduction of the PMOS internal resistance is ensured. The method is simple to realize, but the Zener diode is in a breakdown state, so that the Zener diode leaks electricity when in breakdown, and the power consumption of the whole circuit is increased.
Further, when VIN<VGS SET When the PMOS is turned on, the gate voltage of the PMOS needs to be driven to a negative voltage, and the pull-down path of the gate driving circuit shown in fig. 6 needs to be turned off, because the gate voltage is a negative potential, the PMOS transistor M2 shown in fig. 6 should be connected in series by two back-to-back PMOS transistors, so as to prevent the pull-down path from being turned off. This is also a technique well known in the art.
Furthermore, the charge pump has a plurality of structures, the control method is variable, and the same function can be realized by slightly changing the structure. Modifications to the details of the charge pump circuit, or to the details of the LDO circuit, which are based on the present invention, are well within the scope of the basic principles set forth in this patent.
The embodiments in the present description are described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments are referred to each other. Meanwhile, for a person skilled in the art, according to the idea of the present invention, the specific embodiments and the application range may be changed. In view of the above, the present disclosure should not be construed as limiting the invention.
Claims (7)
1. A PMOS pass switch control circuit, the circuit comprising:
the voltage clamping circuit, the charge pump voltage regulating circuit and the first PMOS tube are connected in series;
the first end of the voltage clamping circuit, the input end of the charge pump voltage regulating circuit and the source electrode of the first PMOS tube are all connected with a power supply;
the second end of the voltage clamping circuit and the output end of the charge pump voltage regulating circuit are both connected with the grid electrode of the first PMOS tube;
the drain electrode of the first PMOS tube is connected with the equipment to be charged;
the charge pump voltage regulating circuit specifically includes:
the device comprises an input voltage detection circuit, a PMOS gate drive circuit, a negative voltage charge pump and an additional voltage linear converter;
the input end of the input voltage detection circuit and the first input end of the additional voltage linear converter are connected as the input end of the charge pump voltage regulating circuit to be connected with the power supply;
the output end of the input voltage detection circuit is respectively connected with the second input end of the additional voltage linear converter, the input end of the PMOS gate drive circuit and the control end of the negative voltage charge pump;
the output end of the additional voltage linear converter is connected with the first port of the negative voltage charge pump;
the second port and the third port of the negative voltage charge pump are grounded;
and a fourth port of the negative-voltage charge pump is connected with the output end of the PMOS gate drive circuit, and is used as the output end of the charge pump voltage regulating circuit to be connected with the gate of the first PMOS tube.
2. The PMOS path switch control circuit of claim 1, wherein said voltage clamp circuit comprises:
n second PMOS tubes;
the grid electrode and the drain electrode of the ith second PMOS tube are both connected with the source electrode of the (i + 1) th second PMOS tube; i =1,.., n;
the source electrode of the 1 st second PMOS tube is used as the first end of the voltage clamping circuit and is connected with the power supply; and the grid electrode and the drain electrode of the nth second PMOS tube are connected as the second end of the voltage clamping circuit and are respectively connected with the output end of the charge pump voltage regulating circuit and the grid electrode of the first PMOS tube.
3. The PMOS pass switch control circuit of claim 1, wherein said input voltage detection circuit specifically comprises:
a first resistor, a second resistor and a first operational amplifier;
the first end of the first resistor and the first end of the second resistor are connected with the positive input end of the first operational amplifier;
a second end of the first resistor is used as an input end of the input voltage detection circuit and is connected with the power supply;
the second end of the second resistor is grounded;
a negative input end of the first operational amplifier inputs a reference voltage; the output end of the first operational amplifier is used as the output end of the input voltage detection circuit and is respectively connected with the second input end of the additional voltage linear converter, the input end of the PMOS gate drive circuit and the control end of the negative voltage charge pump.
4. The PMOS pass-switch control circuit of claim 1, wherein said negative charge pump further comprises:
the first switch, the second switch, the third switch, the fourth switch and the flying capacitor;
the first end of the first switch and the first end of the second switch are both connected with the first end of the flying capacitor;
the first end of the third switch and the first end of the fourth switch are both connected with the second end of the flying capacitor;
the second end of the first switch is connected with the first port;
a second end of the second switch is connected with the second port;
a second end of the third switch is connected with the third port;
and the second end of the fourth switch is connected with the fourth port.
5. The PMOS pass-switch control circuit of claim 1, wherein said PMOS gate driver circuit specifically comprises:
a pull-up circuit and a pull-down circuit;
the first end of the pull-up circuit is used as the input end of the PMOS grid electrode driving circuit and is connected with the output end of the input voltage detection circuit; the second end of the pull-up circuit is used as the output end of the PMOS grid electrode driving circuit and is respectively connected with the grid electrode of the first PMOS tube and the first end of the pull-down circuit; the second terminal of the pull-down circuit is grounded.
6. The PMOS pass-switch control circuit of claim 5, wherein the pull-up circuit specifically comprises:
the first phase inverter and the third PMOS tube;
an input end of the first inverter is used as a first end of the pull-up circuit and is connected with an output end of the input voltage detection circuit;
the power supply end of the first inverter is connected with the source electrode of the third PMOS tube as the power supply end and is connected with the source electrode of the first PMOS tube; the input end of the first phase inverter is connected with the switch control signal of the first PMOS tube;
the output end of the first phase inverter is connected with the grid electrode of the third PMOS tube;
and the drain electrode of the third PMOS tube is used as the second end of the pull-up circuit and is connected with the first end of the pull-down circuit.
7. The PMOS pass-switch control circuit of claim 6, wherein the pull-down circuit specifically comprises:
the fourth PMOS tube, the first NMOS tube and the second phase inverter;
the source electrode of the fourth PMOS tube is used as the first end of the pull-down circuit and is connected with the drain electrode of the third PMOS tube; the grid electrode of the fourth PMOS tube inputs a clamping level; the drain electrode of the fourth PMOS tube is connected with the drain electrode of the first NMOS tube;
the source electrode of the first NMOS tube is used as the second end of the pull-down circuit and grounded; the grid electrode of the first NMOS tube is connected with the output end of the second phase inverter;
and the input end of the second phase inverter is connected with the switch control signal of the first PMOS tube.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110954122.4A CN113708606B (en) | 2021-08-19 | 2021-08-19 | PMOS access switch control circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110954122.4A CN113708606B (en) | 2021-08-19 | 2021-08-19 | PMOS access switch control circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN113708606A CN113708606A (en) | 2021-11-26 |
| CN113708606B true CN113708606B (en) | 2022-11-04 |
Family
ID=78653622
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202110954122.4A Active CN113708606B (en) | 2021-08-19 | 2021-08-19 | PMOS access switch control circuit |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN113708606B (en) |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN114759647B (en) * | 2022-05-27 | 2023-03-24 | 电子科技大学 | Flying capacitor pre-charging circuit |
| CN115987266B (en) * | 2023-01-16 | 2023-11-28 | 深圳市思远半导体有限公司 | Switching circuit, control method and chip of NMOS switching tube |
| CN116405016A (en) * | 2023-06-09 | 2023-07-07 | 芯天下技术股份有限公司 | Low-voltage PMOS switch circuit, system, control method and control device |
| CN116418328B (en) * | 2023-06-09 | 2023-09-19 | 拓尔微电子股份有限公司 | Shutdown control circuit, battery management system and battery pack |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106406418A (en) * | 2015-07-28 | 2017-02-15 | 株式会社电装 | Switching element driving circuit |
| CN110943718A (en) * | 2019-12-26 | 2020-03-31 | 电子科技大学 | Output stage circuit of high-side switch |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8487689B2 (en) * | 2010-01-06 | 2013-07-16 | Aptus Power Semiconductor | Load switch system driven by a charge pump |
| CN108539964B (en) * | 2018-08-08 | 2018-11-20 | 上海颛芯企业管理咨询合伙企业（有限合伙） | The driving circuit and its device of power switch tube |
| CN112910235B (en) * | 2021-01-21 | 2022-02-11 | 中国电子科技集团公司第五十八研究所 | Voltage-adjustable clamping protection circuit |
-
2021
- 2021-08-19 CN CN202110954122.4A patent/CN113708606B/en active Active
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106406418A (en) * | 2015-07-28 | 2017-02-15 | 株式会社电装 | Switching element driving circuit |
| CN110943718A (en) * | 2019-12-26 | 2020-03-31 | 电子科技大学 | Output stage circuit of high-side switch |
Also Published As
| Publication number | Publication date |
|---|---|
| CN113708606A (en) | 2021-11-26 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN113708606B (en) | PMOS access switch control circuit | |
| US9052728B2 (en) | Start-up circuit and method thereof | |
| US20210067033A1 (en) | Differential sensing and maintenance of flying capacitor voltage in a switched-mode power supply circuit | |
| CN113708607B (en) | NMOS (N-channel metal oxide semiconductor) access switch control circuit | |
| US10770912B2 (en) | Charging device and control method thereof | |
| US20110095729A1 (en) | Charging circuit and charging method | |
| JP2012502354A (en) | Adaptive feedback and power control in USB devices | |
| US20190207513A1 (en) | Output current boosting of capacitor-drop power supplies | |
| CN103383581A (en) | Voltage regulation device with transient response reinforce mechanism | |
| CN105356742A (en) | High-efficiency charge pump | |
| US20050275375A1 (en) | Battery charger using a depletion mode transistor to serve as a current source | |
| US11038420B2 (en) | Charge pump transient response optimization by controlled flying capacitor discharge during bypass to switching mode transition | |
| WO2009040340A1 (en) | Single inductor power supply system with extremely high psrr for dual supply active matrix oled displays | |
| US20170279285A1 (en) | Charging device and control method thereof | |
| US10418906B2 (en) | High efficiency primary and secondary bias flyback converter with dual outputs | |
| US20170117727A1 (en) | Energy storage device and control method thereof | |
| US20240055992A1 (en) | Three-level buck converter configurable for two-level buck converter mode operation | |
| US10649513B2 (en) | Energy regulation circuit and operation system utilizing the same | |
| CN109412436B (en) | Synchronous rectification control chip and circuit | |
| JP2007189771A (en) | Power unit | |
| JP5189335B2 (en) | CHARGE CONTROL CIRCUIT AND ELECTRONIC DEVICE USING THE SAME | |
| CN112987843B (en) | Bootstrap driving circuit, driving method and wireless charging system | |
| CN116260339A (en) | Synchronous rectification controller applied to power converter and starting method of synchronous rectification controller in starting stage | |
| CN114301280A (en) | Drive circuit of NMOS switch and electronic equipment | |
| CN113629828A (en) | PD charging circuit and charging method capable of automatically compensating line loss |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| CB02 | Change of applicant information | ||
| CB02 | Change of applicant information |
Address after: 519000 room 1401-1405, building 4, No. 101, University Road, Tangjiawan Town, Xiangzhou District, Zhuhai City, Guangdong Province Applicant after: Zhuhai Zhirong Technology Co.,Ltd. Address before: 519000 room 1505, building 3, 101 University Road, Tangjiawan Town, high tech Zone, Zhuhai City, Guangdong Province Applicant before: ZHUHAI SMART WARE TECHNOLOGY CO.,LTD. |
|
| GR01 | Patent grant | ||
| GR01 | Patent grant |