CN220985374U - Dual-power supply circuit, electronic circuit and equipment - Google Patents
Dual-power supply circuit, electronic circuit and equipment Download PDFInfo
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- CN220985374U CN220985374U CN202322466822.6U CN202322466822U CN220985374U CN 220985374 U CN220985374 U CN 220985374U CN 202322466822 U CN202322466822 U CN 202322466822U CN 220985374 U CN220985374 U CN 220985374U
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- 230000001052 transient effect Effects 0.000 claims description 7
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- 101100112673 Rattus norvegicus Ccnd2 gene Proteins 0.000 description 27
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Abstract
The utility model provides a dual-power supply circuit, an electronic circuit and equipment, which comprise a main power supply; a secondary power supply; the first MOS tube has a first end coupled to the output end of the main power supply, a grid electrode grounded, and a second end coupled to the voltage output end; the second end of the second MOS tube is coupled to the output end of the auxiliary power supply, and the first end of the second MOS tube is coupled to the voltage output end; the first end of the third MOS tube is coupled to the output end of the auxiliary power supply, and the grid electrode of the third MOS tube is coupled to the output end of the main power supply; a fourth MOS tube, the second end of which is coupled to the grid electrode of the second MOS tube, the grid electrode of which is coupled to the second end of the third MOS tube, and the first end of which is grounded; the first resistive unit is coupled between the voltage output end and the grid electrode of the second MOS tube; the first MOS tube to the fourth MOS tube are all used for being controlled to be correspondingly switched on or switched off according to the power supply condition of the main power supply and the auxiliary power supply so as to realize automatic switching between the power supply of the main power supply and the power supply of the auxiliary power supply, and absolute values of the switching threshold voltages of the first MOS tube to the third MOS tube are all in a first range.
Description
Technical Field
The present utility model relates to the field of power supplies, and in particular, to a dual-power supply circuit, an electronic circuit, and an apparatus
Background
At present, electronic devices are increasingly used in production and life, and in order to meet the demands of production and life, many electronic devices need uninterrupted power supply; such as emergency lights, smart door locks, etc. Therefore, the electronic apparatus is commonly provided with a backup power source or a backup battery (hereinafter, collectively referred to as a secondary power source) in addition to the primary power source.
In the prior art, when the dual-power supply circuit automatically switches between a main power supply and a secondary power supply, devices such as an integrated chip, a large capacitor and the like are usually used, so that the circuit design is complex, and the cost is high; meanwhile, the problem that the power supply voltage output after power supply switching does not meet the power supply requirement due to incomplete switching-on and switching-off of a switching tube exists in the prior art.
Disclosure of utility model
The utility model provides a dual-power supply circuit, an electronic circuit and equipment; the automatic switching between the main power supply and the auxiliary power supply is realized on the basis of simple structure and low cost.
According to a first aspect of the present utility model there is provided a dual supply circuit comprising:
a main power supply for providing a first power supply voltage;
a secondary power supply for providing a second power supply voltage;
The first end of the first MOS tube is coupled to the output end of the main power supply, the grid electrode of the first MOS tube is grounded, and the second end of the first MOS tube is coupled to the voltage output end;
The second end of the second MOS tube is coupled to the output end of the auxiliary power supply, and the first end of the second MOS tube is coupled to the voltage output end;
The first end of the third MOS tube is coupled to the output end of the auxiliary power supply, and the grid electrode of the third MOS tube is coupled to the output end of the main power supply;
the second end of the fourth MOS tube is coupled to the grid electrode of the second MOS tube, the grid electrode of the fourth MOS tube is coupled to the second end of the third MOS tube, and the first end of the fourth MOS tube is grounded;
The first resistive unit is coupled between the voltage output end and the grid electrode of the second MOS tube and is used for stabilizing the grid electrode voltage of the second MOS tube;
If only the main power supply outputs the first power supply voltage, the first MOS tube is turned on, the second MOS tube, the third MOS tube and the fourth MOS tube are turned off, the voltage output end is powered by the main power supply, and a first output voltage is output;
If the main power supply and the auxiliary power supply respectively output the first power supply voltage and the second power supply voltage, the first MOS tube is conducted, the second MOS tube, the third MOS tube and the fourth MOS tube are all turned off, the voltage output end is powered by the main power supply, and the first output voltage is output;
if only the auxiliary power supply outputs the second power supply voltage, the first MOS tube is turned off, the second MOS tube, the third MOS tube and the fourth MOS tube are all turned on, the voltage output end is powered by the auxiliary power supply, and a second output voltage is output;
The first MOS tube and the third MOS tube are PMOS tubes; the fourth MOS tube is an NMOS tube; ;
The absolute value of the on threshold voltage of the first MOS tube to the absolute value of the on threshold voltage of the third MOS tube are all in a first range.
Optionally, the first range includes at least 1V-2.4V.
Optionally, the dual-power supply circuit further comprises a second resistive unit, a third resistive unit and a fourth resistive unit; the second resistive unit is coupled between the grid electrode of the first MOS tube and the ground end; the third resistive unit is coupled between the main power supply and the ground; the fourth resistive unit is coupled between the secondary power supply and ground; wherein the second resistive cell to the fourth resistive cell each function as a pull-down resistor.
Optionally, each of the first to fourth resistive units includes a single resistor.
Optionally, each of the first resistive unit to the fourth resistive unit includes a resistive network; the resistor network is formed by connecting a plurality of resistors in series and parallel.
Optionally, the dual-power supply circuit further comprises a first anti-surge component and a second anti-surge component; the first anti-surge assembly is coupled between the main power supply and ground; the second anti-surge assembly is coupled between the secondary power supply and ground; the first anti-surge component and the second anti-surge component are jointly used for protecting components from being influenced by transient pulses generated in the power supply switching process of the main power supply and the auxiliary power supply.
Optionally, the first anti-surge component and the second anti-surge component each include at least one of a transient suppression diode and a varistor.
Optionally, the dual-power supply circuit further comprises a first diode; the anode and the cathode of the first diode are respectively coupled to the output end of the main power supply and the first end of the first MOS tube; and the first diode is used for preventing the power supply current from flowing backward to the main power supply if only the auxiliary power supply supplies power.
According to a second aspect of the present utility model there is provided an electronic circuit comprising the dual supply circuit of the first aspect of the present utility model and optionally provided.
According to a third aspect of the utility model there is provided a device comprising the electronic circuit provided by the second aspect of the utility model.
The dual-power supply circuit provided by the utility model can realize automatic switching between main power supply and auxiliary power supply only through the first MOS tube, the second MOS tube, the third MOS tube, the fourth MOS tube and the first resistive unit, and has a simple structure and low cost compared with the prior art. Meanwhile, the absolute value of the on threshold voltage of the first MOS tube is set to be in a first range, so that the first MOS tube, the second MOS tube and the third MOS tube can be thoroughly turned on or turned off when power supply switching between a main power supply and an auxiliary power supply is performed.
Drawings
The utility model will be described in further detail with reference to the drawings and the detailed description.
Fig. 1 is a circuit configuration diagram of a dual-power supply circuit according to an embodiment of the present utility model;
Fig. 2 is a second circuit configuration diagram of a dual-power supply circuit according to an embodiment of the present utility model;
fig. 3 is a circuit configuration diagram of a dual-power supply circuit according to an embodiment of the present utility model.
Reference numerals:
Vin 1-main power supply;
Vin 2-secondary power supply;
Vout-voltage output;
q1-a first MOS tube;
Q2-a second MOS tube;
q3-a third MOS tube;
q4-a fourth MOS tube;
R1-a first resistive element;
R2-a second resistive element;
R3-a third resistive element;
R4-fourth resistive element;
D1-a first diode;
TVS 1-a first anti-surge component;
TVS 2-second anti-surge component.
Detailed Description
The following description of the embodiments of the present utility model will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present utility model, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the utility model without making any inventive effort, are intended to be within the scope of the utility model. The terms "first," "second," "third," "fourth" and the like in the description and in the claims and in the above drawings, if any, are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used may be interchanged where appropriate such that the embodiments of the utility model described herein may be implemented in sequences other than those illustrated or otherwise described herein. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.
Referring to fig. 1, an embodiment of the present utility model provides a dual-power supply circuit, which includes:
a main power source Vin1 for providing a first power source voltage;
a secondary power supply Vin2 for supplying a second power supply voltage;
The first MOS tube Q1, its first end couples to the output end of the said main power Vin1, the grid of the said first MOS tube Q1 is grounded, the second end of the said first MOS tube Q1 couples to voltage output end Vout;
A second end of the second MOS transistor Q2 is coupled to the output end of the secondary power source Vin2, and a first end of the second MOS transistor Q2 is coupled to the voltage output end Vout;
a first end of the third MOS transistor Q3 is coupled to the output end of the secondary power supply Vin2, and a gate of the third MOS transistor Q3 is coupled to the output end of the primary power supply Vin 1;
a second end of the fourth MOS transistor Q4 is coupled to the gate of the second MOS transistor Q2, the gate of the fourth MOS transistor Q4 is coupled to the second end of the third MOS transistor Q3, and the first end of the fourth MOS transistor Q4 is grounded;
a first resistive unit R1 coupled between the voltage output terminal Vout and the gate of the second MOS transistor Q2, where the first resistive unit R1 is configured to stabilize the gate voltage of the second MOS transistor Q2;
if only the main power supply Vin1 outputs the first power supply voltage, the first MOS transistor Q1 is turned on, the second MOS transistor Q2, the third MOS transistor Q3, and the fourth MOS transistor Q4 are turned off, and the voltage output terminal Vout is powered by the main power supply Vin1 and outputs a first output voltage;
If the main power source Vin1 and the auxiliary power source Vin2 respectively output the first power source voltage and the second power source voltage, the first MOS transistor Q1 is turned on, the second MOS transistor Q2, the third MOS transistor Q3 and the fourth MOS transistor Q4 are turned off, the voltage output terminal Vout is powered by the main power source Vin1, and the first output voltage is output;
If only the secondary power supply Vin2 outputs the second power supply voltage, the first MOS transistor Q1 is turned off, the second MOS transistor Q2, the third MOS transistor Q3, and the fourth MOS transistor Q4 are all turned on, and the voltage output terminal Vout is powered by the secondary power supply Vin2 and outputs a second output voltage;
the first MOS tube Q1 to the third MOS tube Q3 are PMOS tubes; the fourth MOS transistor Q4 is an NMOS transistor; ;
The absolute value of the on threshold voltage of the first MOS transistor Q1 to the absolute value of the on threshold voltage of the third MOS transistor Q3 are all within a first range.
Referring to fig. 1, the embodiment of the present utility model thoroughly realizes automatic switching of power supply between a main power source Vin1 and a secondary power source Vin2 on the basis of low cost and simple structure through the above technical scheme.
The principle is as follows:
If only the main power source Vin1 outputs the first power voltage, the source of the first MOS transistor Q1 is at a high level because of being connected to the main power source Vin1, the gate thereof is at a low level because of being grounded, and the first MOS transistor Q1 is a PMOS transistor, so that the first MOS transistor Q1 is fully turned on; the gate of the third MOS transistor Q3 is at a high level because of the connection with the main power source Vin1, the source thereof is at a low level because of the connection with the auxiliary power source Vin2, and the third MOS transistor Q3 is a PMOS transistor, so that the third MOS transistor Q3 is turned off; the gate of the fourth MOS transistor Q4 is connected to the drain of the third MOS transistor Q3, so that the source thereof is in a high-resistance state, and the source thereof is in a low-level state because of being grounded, so that the fourth MOS transistor Q4 is also turned off; the gate of the second MOS transistor Q2 is connected to the drain of the fourth MOS transistor Q4, so that the source of the second MOS transistor Q2 is connected to the gate thereof through the first component, and therefore, the voltage difference between the gate and the source of the second MOS transistor Q2 is almost 0, and the second MOS transistor Q2 is also turned off. As can be seen from the above, the second MOS transistor Q2 to the fourth MOS transistor Q4 are turned off, and only the first MOS transistor Q1 is turned on, so that the main power source Vin1 outputs a first output voltage to supply power to the subsequent device through the drain electrode of the first MOS transistor Q1.
If the main power source Vin1 and the auxiliary power source Vin2 output the first power voltage and the second power voltage respectively, the first MOS transistor Q1 is turned on as above, and the gate and the source of the third MOS transistor Q3 are both high because they are connected to the main power source Vin1 and the auxiliary power source Vin2 respectively, so that the voltage difference between the gate and the source of the third MOS transistor Q3 is almost 0, and the third MOS transistor Q3 is turned off; the fourth MOS transistor Q4 and the second MOS transistor Q2 are turned off as above. At this time, the second MOS transistor Q2 to the fourth MOS transistor Q4 are all turned off. As can be seen from the above, only the first MOS transistor Q1 is turned on, so the main power source Vin1 outputs the first output voltage to supply power to the subsequent device through the drain of the first MOS transistor Q1.
If only the secondary power source Vin2 outputs the second power voltage, the gate and the source of the first MOS transistor Q1 are both low because of the ground terminal and the primary power source Vin1, and therefore the voltage difference between the gate and the source of the first MOS transistor Q1 is almost 0, so that the first MOS transistor Q1 is turned off; the gate of the third MOS transistor Q3 is at a low level because of the connection with the main power source Vin1, the source thereof is at a high level because of the connection with the auxiliary power source Vin2, and the third MOS transistor Q3 is a PMOS transistor, so that the third MOS transistor Q3 is turned on; because the third MOS transistor Q3 is turned on, the gate of the fourth MOS transistor Q4 is also at a high level, the source of the fourth MOS transistor Q4 is at a low level because of the ground, and because the fourth MOS transistor Q4 is an NMOS transistor, the fourth MOS transistor Q4 is turned on; because the fourth MOS transistor Q4 is turned on, the gate of the second MOS transistor Q2 is pulled down to the ground; the first resistive unit R1 is configured to isolate the gate and the source of the second MOS transistor Q2 at this time, because the secondary power Vin2 outputs the second power voltage, the body diode of the second MOS transistor Q2 is turned on to accumulate a potential at the source of the second MOS transistor Q2 until the second MOS transistor Q2 is turned on. From the above, the second MOS transistor Q2 to the fourth MOS transistor Q4 are all turned on, and only the first MOS transistor Q1 is turned off, so that the secondary power Vin2 outputs a second output voltage to supply power to the subsequent device through the source of the second MOS transistor Q2.
In summary, by controlling the on-off of the first MOS transistor Q1 to the fourth MOS transistor Q4, the automatic switching between the power supplied by the main power source Vin1 and the power supplied by the auxiliary power source Vin2 is realized.
As a specific embodiment, the first range includes at least 1V to 2.4V. The beneficial effects that it has are: so as to ensure that the first MOS transistor Q1 to the third MOS transistor Q3 can be completely turned on and off when the main power source Vin2 and the auxiliary power source Vin2 are switched. Of course, this is merely experimental data of the present utility model, and the specific values of the first range may be adjusted according to actual requirements, which is not limited herein.
Other structures in the dual power supply circuit are described below:
Referring to fig. 2, as a specific embodiment, the dual-power supply circuit further includes a second resistive unit R2, a third resistive unit R3, and a fourth resistive unit R4; the second resistive unit R2 is coupled between the gate and the ground of the first MOS transistor Q1; the third resistive unit R3 is coupled between the main power source Vin1 and ground; the fourth resistive unit R4 is coupled between the secondary power source Vin2 and ground; wherein the second to fourth resistive cells R2 to R4 each function as a pull-down resistor. The beneficial effects that it has are: through the second resistive unit R2 and the third resistive unit R3, when the main power supply Vin1 fails and is not powered, the first MOS transistor Q1 is turned off thoroughly, and the main power supply Vin1 is pulled down completely, so as to prevent the accuracy of power supply switching from being affected due to the suspension state of the first MOS transistor Q1 and the main power supply Vin 1. By the fourth resistive unit R4, it is ensured that the secondary power source Vin2 is pulled down completely when no power is supplied to the secondary power source Vin 2. Specific: the first to fourth resistive cells R1 to R4 each include a single resistance. Of course, the first to fourth resistive units R1 to R4 may each include a resistor network; the resistor network is formed by connecting a plurality of resistors in series and parallel. The specific structures of the first resistive unit R1 to the fourth resistive unit R4 may be adjusted according to actual requirements, which are not limited herein.
Referring to fig. 3, as a specific embodiment, the dual-power supply circuit further includes a first anti-surge module TVS1 and a second anti-surge module TVS2; the first anti-surge assembly TVS1 is coupled between the main power source Vin1 and ground; the second anti-surge module TVS2 is coupled between the secondary power source Vin2 and ground. The beneficial effects that it has are: the first anti-surge module TVS1 and the second anti-surge module TVS2 are used together to protect components from the transient pulse generated by the main secondary power supply Vin2 in the power supply switching process. Specific: the first anti-surge component TVS1 and the second anti-surge component TVS2 each include at least one of a transient suppression diode and a varistor. The specific choice of the transient suppression diode or the varistor may be selected according to actual requirements, and is not limited herein.
Referring to fig. 3, as a specific embodiment, the dual-power supply circuit further includes a first diode D1; the anode and the cathode of the first diode D1 are coupled to the output end of the main power source Vin1 and the first end of the first MOS transistor Q1, respectively; the beneficial effects that it has are: if only the secondary power source Vin2 supplies power, the first diode D1 is configured to prevent the power supply current output by the secondary power source Vin2 from flowing backward to the primary power source Vin1.
In summary, the dual-power supply circuit provided by the embodiment of the utility model can realize automatic switching between the power supply of the main power supply Vin1 and the power supply of the auxiliary power supply Vin2 only through the first MOS tube Q1, the second MOS tube Q2, the third MOS tube Q3, the fourth MOS tube Q4 and the first resistive unit R1, and has a simple structure and low cost compared with the prior art. Meanwhile, by setting the absolute value of the on threshold voltage of the first MOS transistor Q1 to the absolute value of the on threshold voltage of the third MOS transistor Q3 to be in the first range, the first MOS transistor Q1, the second MOS transistor Q2 and the third MOS transistor Q3 are thoroughly turned on or turned off when the power supply between the main power supply Vin1 and the auxiliary power supply Vin2 is switched.
The embodiment of the utility model also provides an electronic circuit which comprises the dual-power supply circuit.
The embodiment of the utility model also provides equipment comprising the electronic circuit.
Finally, it should be noted that: the above embodiments are only for illustrating the technical solution of the present utility model, and not for limiting the same; although the utility model has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some or all of the technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit of the utility model.
Claims (10)
1. A dual power supply circuit, the circuit comprising:
a main power supply for providing a first power supply voltage;
a secondary power supply for providing a second power supply voltage;
The first end of the first MOS tube is coupled to the output end of the main power supply, the grid electrode of the first MOS tube is grounded, and the second end of the first MOS tube is coupled to the voltage output end;
The second end of the second MOS tube is coupled to the output end of the auxiliary power supply, and the first end of the second MOS tube is coupled to the voltage output end;
The first end of the third MOS tube is coupled to the output end of the auxiliary power supply, and the grid electrode of the third MOS tube is coupled to the output end of the main power supply;
the second end of the fourth MOS tube is coupled to the grid electrode of the second MOS tube, the grid electrode of the fourth MOS tube is coupled to the second end of the third MOS tube, and the first end of the fourth MOS tube is grounded;
The first resistive unit is coupled between the voltage output end and the grid electrode of the second MOS tube and is used for stabilizing the grid electrode voltage of the second MOS tube;
If only the main power supply outputs the first power supply voltage, the first MOS tube is turned on, the second MOS tube, the third MOS tube and the fourth MOS tube are turned off, the voltage output end is powered by the main power supply, and a first output voltage is output;
If the main power supply and the auxiliary power supply respectively output the first power supply voltage and the second power supply voltage, the first MOS tube is conducted, the second MOS tube, the third MOS tube and the fourth MOS tube are all turned off, the voltage output end is powered by the main power supply, and the first output voltage is output;
if only the auxiliary power supply outputs the second power supply voltage, the first MOS tube is turned off, the second MOS tube, the third MOS tube and the fourth MOS tube are all turned on, the voltage output end is powered by the auxiliary power supply, and a second output voltage is output;
The first MOS tube and the third MOS tube are PMOS tubes; the fourth MOS tube is an NMOS tube;
The absolute value of the on threshold voltage of the first MOS tube to the absolute value of the on threshold voltage of the third MOS tube are all in a first range.
2. The dual power supply circuit of claim 1, wherein the first range comprises at least 1V-2.4V.
3. The dual power supply circuit of claim 1, further comprising a second resistive element, a third resistive element, a fourth resistive element; the second resistive unit is coupled between the grid electrode of the first MOS tube and the ground end; the third resistive unit is coupled between the main power supply and the ground; the fourth resistive unit is coupled between the secondary power supply and ground; wherein the second resistive cell to the fourth resistive cell each function as a pull-down resistor.
4. A dual power supply circuit as claimed in claim 3, wherein the first to fourth resistive elements each comprise a single resistor.
5. A dual power supply circuit as claimed in claim 3, wherein the first to fourth resistive elements each comprise a resistive network; the resistor network is formed by connecting a plurality of resistors in series and parallel.
6. The dual power supply circuit of claim 1, further comprising a first anti-surge component and a second anti-surge component; the first anti-surge assembly is coupled between the main power supply and ground; the second anti-surge assembly is coupled between the secondary power supply and ground; the first anti-surge component and the second anti-surge component are jointly used for protecting components from being influenced by transient pulses generated in the power supply switching process of the main power supply and the auxiliary power supply.
7. The dual power supply circuit of claim 6, wherein the first anti-surge component and the second anti-surge component each comprise at least one of a transient suppression diode and a varistor.
8. The dual power supply circuit of claim 1, further comprising a first diode; the anode and the cathode of the first diode are respectively coupled to the output end of the main power supply and the first end of the first MOS tube; and the first diode is used for preventing the power supply current from flowing backward to the main power supply if only the auxiliary power supply supplies power.
9. An electronic circuit comprising a dual supply circuit as claimed in any one of claims 1 to 8.
10. An apparatus comprising the electronic circuit of claim 9.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202322466822.6U CN220985374U (en) | 2023-09-11 | 2023-09-11 | Dual-power supply circuit, electronic circuit and equipment |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202322466822.6U CN220985374U (en) | 2023-09-11 | 2023-09-11 | Dual-power supply circuit, electronic circuit and equipment |
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| Publication Number | Publication Date |
|---|---|
| CN220985374U true CN220985374U (en) | 2024-05-17 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN202322466822.6U Active CN220985374U (en) | 2023-09-11 | 2023-09-11 | Dual-power supply circuit, electronic circuit and equipment |
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| Country | Link |
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| CN (1) | CN220985374U (en) |
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2023
- 2023-09-11 CN CN202322466822.6U patent/CN220985374U/en active Active
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