CN101872971A - Reverse-connection preventing circuit, reverse-connection preventing processing method and communication equipment - Google Patents

Reverse-connection preventing circuit, reverse-connection preventing processing method and communication equipment Download PDF

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CN101872971A
CN101872971A CN 201010225022 CN201010225022A CN101872971A CN 101872971 A CN101872971 A CN 101872971A CN 201010225022 CN201010225022 CN 201010225022 CN 201010225022 A CN201010225022 A CN 201010225022A CN 101872971 A CN101872971 A CN 101872971A
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China
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voltage
circuit
fet
connected
reverse
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CN 201010225022
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Chinese (zh)
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任谦
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北京星网锐捷网络技术有限公司
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Priority to CN 201010225022 priority Critical patent/CN101872971A/en
Publication of CN101872971A publication Critical patent/CN101872971A/en

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Abstract

The invention provides a reverse-connection preventing circuit, a reverse-connection preventing processing method and communication equipment. The circuit comprises a voltage bias resistor connected between the anode and the cathode of the power supply, a bidirectional voltage-lamping circuit and at least one field-effect tube, wherein the voltage bias resistor is connected with the grid electrode of the field-effect tube and is used for conducting and biasing the field-effect tube; the bidirectional voltage-lamping circuit is connected in parallel at two ends of the grid electrode and the source electrode of the field-effect tube and is used for taking a grid electrode and source electrode voltage clamp of the field-effect tube as a first protective voltage when inputting overvoltage in the forward direction; and the first protective voltage is the normal work voltage of the field-effect tube. The invention also provides the reverse-connection preventing processing method and the communication equipment. The invention achieves the input overvoltage protection function of the direct current input reverse-connection preventing circuit and improves the reliability of the circuit.

Description

防反接电路、防反接处理方法和通讯设备 Anti-reverse circuit, anti-reverse processing method and communication apparatus

技术领域 FIELD

[0001] 本发明涉及通信技术领域,尤其涉及一种防反接电路、防反接处理方法和通讯设备。 [0001] The present invention relates to communications technologies, and in particular relates to an anti-reverse circuit, anti-reverse processing method and communication equipment.

背景技术 Background technique

[0002] 在通信领域的使用外接直流电源的电子系统中,外接直流电源的极性误接或反接往往会对设备造成不可恢复的损害,甚至烧毁相关设备,因此,由直流电源供电的通信设备的电源输入通常需要设计为防反接电路。 [0002] Electronic system using an external DC power supply in the communications field, the polarity of the external DC power supply will tend to reverse or misconnection device unrecoverable damage, even burn related equipment, therefore, the DC power supply communication power input devices often need to be designed to prevent reverse circuit.

[0003] 如图1所示为现有技术中的一种防反接电路的连接示意图,现有技术中的防反接电路通常在供电电路上串联一个二极管D1,利用二极管的单向导通、反向截止的特性实现输入防反接功能。 [0003] FIG. 1 is a connection diagram of one prior art anti-reverse circuit, the prior art anti-reverse circuits typically a diode D1 connected in series to the power supply circuit using a single diode is conducting, reverse blocking characteristics for input anti-reverse function. 如果电源VIN+和VIN-的极性反接,二极管D1出现反向截止,使得供电电路处于短路状态,则可以避免电源输入反接导致的主板电路的损坏。 If the reverse polarity of the power supply VIN + and VIN-, appears reverse blocking diode D1, so that the power supply circuit is short-circuited, the power supply circuit to avoid damage to the board resulting from reverse input. 但由于二极管在正向导通时存在电压降,且该电压降相对固定,当其应用在大功率电路应用中时,流经二极管的电流越大,二极管上的消耗功率也越大,导致二极管的温升越高。 However, due to the presence of the diode in forward conduction voltage drop, the voltage drop and the relatively fixed, when it is applied in power circuit applications, the greater the current through the diode, the power consumption of the diode is also larger, resulting in diode The higher the temperature rise. 如果二极管温升过高会明显降低二极管的可靠性,若未对二极管设置专门的散热器进行散热处理,则二极管容易因结温过高而烧毁。 If the temperature is too high the diode will significantly reduce the reliability of the diode, the diode disposed of if not special radiator heat treatment, the diode junction temperature is too high and susceptible to burning. 如图2所示为现有技术中的另一种防反接电路的连接示意图,其为对图1中防反接电路的改进,将串联在供电回路中的二极管更换为N沟信道金属氧化物半导体(N-Channel MetalOxide Semiconductor ;以下简称:NM0S)场效应管Q1,其中,Q1 的S 管脚和D管脚串接于VIN-与负载&之间,G脚通过电阻R2连接到S脚,通过电阻R1连接到VIN+,利用M0S管的开关特性来控制供电电路的导通和截止,从而防止电源极性反接所导致的负载损坏。 2 a schematic view of the connection shown as another anti-reverse circuit of the prior art, which is improvement in the anti-reverse circuit of Figure 1, the power supply circuit in series with a diode to replace the N-channel metal oxide channel semiconductor (N-Channel MetalOxide semiconductor; hereinafter: NM0S) field effect transistor Q1, wherein, Q1 is S and D pins pin connected in series between the load and VIN- &, G pin is connected through a resistor R2 to pin S connected to VIN +, using a switching characteristic M0S tube supply circuit to control the on and off via the resistor R1, so as to prevent load damage caused by power polarity reversal. 由于M0S管的导通内阻很小,基本为毫欧级,即使在大电流的场合中M0S 管的压降也很小,且其导通损耗可以控制在很小的数量级,则可以彻底解决图1中采用二极管作为电源防反接电路导致的压降和功耗过大的问题。 Since the on-resistance tube M0S small, substantially milliohm, M0S drop tube is small even in the case of a large current, and the conduction losses may be controlled in a very small magnitude, it is possible to completely solve the anti-reverse diode as a power supply circuit and the voltage drop caused by the problem of excessive power consumption in FIG. 1 employed.

[0004] 然而,在上述图2中,Q1的开启电压为4.5V-5V,此时Q1的导通内阻还较大,为了达到更小的导通内阻,需要增大Q1的GS管脚之间的电压,当GS管脚间的电压达到10V-15V 时,Q1处在最佳导通状态下,Q1的导通内阻最小。 [0004] However, in the above-described FIG. 2, open voltage of Q1 is 4.5V-5V, Q1 is at this time also greater resistance, in order to achieve a smaller on-resistance needs to be increased, GS tube Q1 voltage between the legs, when the voltage between the pins GS reaches 10V-15V, Q1 is turned on at the optimum state, Q1 is the minimum resistance. 但由于直流输入电源电压并非稳定电压, 当输入直流电压继续升高时,则会导致GS管脚之间的电压也随之升高。 However, due to a DC input supply voltage is not stable, when the input DC voltage continues to rise, will cause the voltage between the pins GS also will increase. 当GS管脚之间的电压达到20V以上时,Q1的GS管脚由于过压容易导致Q1烧毁,导致整个防反接电路失效。 When the voltage reaches 20V between the pin than GS, GS Q1 of pins Q1 overpressure easily lead to burn, resulting in the failure of the anti-reverse circuit.

发明内容 SUMMARY

[0005] 本发明提供一种防反接电路、防反接处理方法和通讯设备,用以解决现有技术中防反接电路存在的输入电压过压导致M0S管击穿的问题,实现直流输入防反接电路的输入过压保护功能,拓展电路的应用电压范围,提高电路的可靠性。 [0005] The present invention provides an anti-reverse circuit, anti-reverse processing method and communication apparatus, the input voltage to solve the problems of the prior art anti-reverse overvoltage circuit causes problems M0S tube breakdown, to achieve DC input input overvoltage protection, to expand the range of the applied voltage circuit of the anti-reverse circuit, to improve the reliability of the circuit.

[0006] 本发明提供一种防反接电路,包括连接在电源正极与电源负极之间的电压偏置电阻、双向电压箝位电路和至少一个场效应管,其中,所述电压偏置电阻与所述场效应管的栅极相连,用于对所述场效应管进行导通偏置,所述双向电压箝位电路并联连接在所述场效 [0006] The present invention provides an anti-reverse circuit includes a bias resistor connected to a voltage between the positive electrode and the negative power supply, the bidirectional voltage clamp circuit and at least one field effect transistor, wherein said bias voltage resistor the gate of the FET is connected to the bias FET turned on, the bidirectional voltage clamp is connected in parallel with said field effect

4应管的栅极-源极的两端,所述双向电压箝位电路用于在正向输入过压时,将所述场效应管的栅极-源极电压箝位为第一保护电压,所述第一保护电压为所述场效应管的正常工作电压。 The gate should pipe 4 - both ends of the source, the bidirectional voltage clamp for the forward input overvoltage, the gate of the FET - source voltage clamp to a first voltage protection the first protective voltage is the normal operating voltage of the FET.

[0007] 本发明提供一种防反接处理方法,包括: [0007] The present invention provides an anti-reverse processing method, comprising:

[0008] 在正向输入过压时,通过并联连接在场效应管的栅极-源极的两端的双向电压箝位电路将所述场效应管的栅极-源极电压箝位为第一保护电压,所述第一保护电压为所述场效应管的正常工作电压。 [0008] When the positive input overvoltage, are connected in parallel to the gate of the FET - bidirectional voltage clamp across the source electrode of the FET gate - source voltage clamped at a first protection voltage, the protection voltage to said first normal operating voltage FET.

[0009] 本发明提供一种通讯设备,包括上述的防反接电路。 [0009] The present invention provides a communication apparatus comprising the above-described anti-reverse circuit.

[0010] 本发明的防反接电路、防反接处理方法和通讯设备,通过在场效应管的栅极-源极的两端并联双向电压箝位电路,在正向输入过压时,由双向电压箝位电路将场效应管的栅极-源极电压箝位在正常工作电压之内,解决了现有技术中防反接电路存在的输入电压过压导致M0S管击穿的问题,实现了直流输入防反接电路的输入过压保护功能,拓展了电路的应用电压范围,提高了电路的可靠性。 [0010] anti-reverse circuit of the present invention, the anti-reverse processing method and communication apparatus, by the FET gate - source ends bidirectional voltage clamp connected in parallel, the positive input overvoltages, bidirectional voltage clamping circuit FET gate - source voltage clamp in the normal operating voltage, the input voltage to solve problems of the prior art anti-reverse circuit overvoltage breakdown leads to problems M0S tube, to achieve a input anti-reverse DC input overvoltage protection circuit, expanding the application of the voltage range of the circuit, improving the reliability of the circuit.

附图说明 BRIEF DESCRIPTION

[0011] 为了更清楚地说明本发明实施例或现有技术中的技术方案,下面将对实施例或现有技术描述中所需要使用的附图作一简单地介绍,显而易见地,下面描述中的附图是本发明的一些实施例,对于本领域普通技术人员来讲,在不付出创造性劳动性的前提下,还可以根据这些附图获得其他的附图。 [0011] In order to more clearly illustrate the technical solutions in the embodiments or the prior art embodiment of the present invention, the accompanying drawings for illustrating the prior art described or needed to be used in an embodiment will be briefly introduced hereinafter, the description below the figures show some embodiments of the present invention, those of ordinary skill in the art is concerned, without any creative effort, and can obtain other drawings based on these drawings.

[0012] 图1为现有技术中的一种防反接电路的连接示意图; [0012] An anti-reverse FIG. 1 is a circuit schematic diagram of the prior art connector;

[0013] 图2为现有技术中的另一种防反接电路的连接示意图; [0013] Figure 2 is another prior art anti-reverse circuit connection diagram;

[0014] 图3为本发明防反接电路实施例一的结构示意图; [0014] FIG. 3 anti-reverse circuit diagram of a schematic structural diagram of embodiment of the present invention;

[0015] 图4为本发明防反接电路实施例二的结构示意图; [0015] Fig 4 a schematic view of the anti-reverse circuit configuration according to a second embodiment of the present invention;

[0016] 图5为本发明防反接电路实施例三的结构示意图; [0016] Fig 5 a schematic view of the anti-reverse circuit configuration according to a third embodiment of the present invention;

[0017] 图6为本发明防反接电路实施例四的结构示意图; [0017] Fig 6 a schematic view of the anti-reverse circuit configuration according to a fourth embodiment of the present invention;

[0018] 图7为本发明防反接电路实施例五的结构示意图; [0018] Figure 7 a schematic view of the anti-reverse circuit configuration according to a fifth embodiment of the present invention;

[0019] 图8为本发明防反接电路实施例六的结构示意图; [0019] Figure 8 a schematic view of the anti-reverse circuit configuration according to a sixth embodiment of the invention;

[0020] 图9为本发明防反接处理方法实施例的流程图。 [0020] FIG. 9 anti-reverse flow diagram processing method of the embodiment of the present invention.

具体实施方式 Detailed ways

[0021] 为使本发明实施例的目的、技术方案和优点更加清楚,下面将结合本发明实施例中的附图,对本发明实施例中的技术方案进行清楚、完整地描述,显然,所描述的实施例是本发明一部分实施例,而不是全部的实施例。 [0021] In order that the invention object, technical solutions, and advantages of the embodiments more clearly, the following the present invention in the accompanying drawings, technical solutions of embodiments of the present invention are clearly and completely described, obviously, the described the embodiment is an embodiment of the present invention is a part, but not all embodiments. 基于本发明中的实施例,本领域普通技术人员在没有作出创造性劳动前提下所获得的所有其他实施例,都属于本发明保护的范围。 Based on the embodiments of the present invention, those of ordinary skill in the art to make all other embodiments without creative work obtained by, fall within the scope of the present invention.

[0022] 图3为本发明防反接电路实施例一的结构示意图,如图3所示,本实施例提供了一种防反接电路,该防反接电路可以包括双向电压箝位电路1、电压偏置电阻6和至少一个场效应管2,图中仅以包括一个场效应管2为例进行说明。 [0022] FIG. 3 anti-reverse circuit diagram of a schematic structural diagram of embodiment of the present invention, shown in Figure 3, the present embodiment provides an anti-reverse circuit, the anti-reverse circuit may comprise a bidirectional voltage clamping circuit 1 , bias resistors 6 and at least one FET 2, FIG. 2 only comprises a field effect transistor will be described as an example. 本实施例中防反接电路中的双向电压箝位电路1和场效应管2均连接在电源正极3与电源负极4之间。 Examples of anti-reverse circuit bidirectional voltage clamp FET 1 and 2 of the present embodiment are connected to the positive power supply 3 and the power source 4 between the negative electrode. 其中,电压偏置电阻6 与场效应管2的栅极G相连,用于对场效应管2进行导通偏置,双向电压箝位电路1并联连接在场效应管2的栅极-源极(即GS)的两端,双向电压箝位电路1用于在电源电压正向输入过压时,将场效应管2的栅极-源极电压箝位为第一保护电压。 Wherein the voltage bias resistor 6 connected to a gate G of the FET 2, FET 2 for bias to be turned on, a parallel bidirectional voltage clamp connected between the gate of the FET 2 - source ( i.e. both ends GS), the bidirectional voltage clamp for an input overvoltage positive power supply voltage, the gate of the FET 2 - source voltage clamped at a first voltage protection. 即将箝位在第一保护电压,即使电源电压继续升高,施加在场效应管2上的V^均保持为第一保护电压,则可以防止场效应管2不会因输入过压而导致其GS管脚过压击穿,进而防止场效应管2被烧毁, 保证防反接电路的稳定性。 Is about to clamp the first protective voltage, even when the power supply voltage continues to rise, the FET is applied on the V ^ 2 are maintained at a first voltage protection, it can be prevented FET 2 will not cause it to an input overvoltage GS pin overvoltage breakdown, thereby preventing the FET 2 is burned, to ensure the stability of the anti-reverse circuit. 在本实施例中,第一保护电压为场效应管2的正常工作电压,即可以将场效应管2的GS管脚的电压维持在其正常工作电压的范围之内,保证其不会被过压击穿而烧毁。 In the present embodiment, a first voltage protection normal operating voltage FET 2, i.e., the voltage of the FET 2 GS pin can be maintained in the range of its normal operating voltage to ensure that it will not be too pressure breakdown and burned.

[0023] 与图1所示的现有技术中的防反接电路相比,本实施例采用场效应管作为开关器件,实现防反接电路的开关控制,而图1中利用二极管的单向导通和反向截止的特性来实现输入防反接功能。 [0023] Compared with the prior art shown in FIG. 1 anti-reverse circuit, the present embodiment employs the use of diode 1 in FIG unidirectional FET as a switching device, the anti-reverse switch control circuit, and and reverse blocking characteristics on the input to achieve the anti-reverse function. 其中,当二极管的输入压降与输出压降之差大于0. 7V,即二极管的正极与负极的电压差大于0. 7V时,二极管导通,电流从正极流向负极,由于二极管存在寄生结电容,因此导通时需要对结电容进行充电,当电容充满之后,二极管实现导通;当输入压降与输出压降之差小于0. 7V时,二极管截止,电流无法流通,二极管截止时寄生结电容需要放电,放完电后实现截止。 Wherein, when the difference between the input and the output voltage drop of the diode drop greater than 0. 7V, i.e., the cathode of the diode and the negative voltage difference greater than 0. 7V, diode conducts, current flows from positive to negative, due to the presence of parasitic junction capacitance diode , it is necessary to charge the junction capacitance when turned on, when the capacitors are fully charged, the diode conduction is; drop when the difference between the input and the output voltage drop is less than 0. 7V, the diode is turned off, current can not flow, the parasitic junction diode is turned off capacitor discharge required to achieve after the deadline discharged. 由于二极管的工艺导致其寄生的结电容比较大,因此二极管的导通和截止需要较长时间,通常约为微秒级别。 Because the process causes the parasitic diode junction capacitance is large, and thus the diode is turned off takes a long time, typically about microsecond. 而场效应管的导通内阻比较小,基本在毫欧级,即时在大电流场合中场效应管的压降也很小,则可以克服图1中现有技术中二极管电源防反接电路中压降和功耗过大的问题,使得电路的可靠性也提高。 The FET on-resistance is relatively small, substantially milliohm, instant pressure drop in a high current FET occasions is small, it can be overcome in the prior art FIG. 1 anti-reverse power diode circuit pressure drop and power dissipation problem, so that the reliability of the circuit also increases.

[0024] 与图2所示的现有技术中的防反接电路相比,本实施例通过在场效应管的GS管脚两端并联一个双向电压箝位电路,实现对场效应管的GS管脚两端的电压进行精确地箝位保护。 [0024] Compared with the prior art shown in FIG. 2 in the anti-reverse circuit, in parallel with this embodiment, a bidirectional voltage clamp across the FET pin GS, GS tube to achieve FET the voltage across the foot precisely clamp protection. 当输入电源电压电压升高时,场效应管的GS管脚电压不会随之升高,而被双向电压箝位电路箝位在场效应管的正常工作电压的范围之内,使得场效应管不会因GS管脚过压击穿而烧毁,从而防止因其引起的整个防反接电路的失效等。 When the input supply voltage increases, GS pin voltage rise FET does not turn, is a bidirectional voltage clamping circuit clamps within the normal operating voltage of the FET, the FET is not so GS pin due to overvoltage breakdown burned, so as to prevent failure of the entire circuit because due to the anti-reverse the like.

[0025] 本实施例提供了一种防反接电路,通过在场效应管的栅极-源极的两端并联双向电压箝位电路,在正向输入过压时,由双向电压箝位电路将场效应管的栅极-源极电压箝位在正常工作电压之内,解决了现有技术中防反接电路存在的输入电压过压导致M0S管击穿的问题,实现了直流输入防反接电路的输入过压保护功能,拓展了电路的应用电压范围, 提高了电路的可靠性。 [0025] The present embodiment provides an anti-reverse circuit, by the gate of the FET - both ends of the parallel source of bidirectional voltage clamp, when the input through the forward pressure, by a bidirectional voltage clamp circuit FET gate - source voltage clamp in the normal operating voltage, the input voltage to solve problems of the prior art anti-reverse circuit overvoltage breakdown leads to problems M0S tube, to achieve the anti-reverse DC input input overvoltage protection circuit, expanding the application of the voltage range of the circuit, improving the reliability of the circuit.

[0026] 进一步地,继续参照上述图3所示,本实施例提供的防反接电路中的双向电压箝位电路还可以用于在反向输入过压时,将场效应管2的栅极-源极电压箝位为第二保护电压,该第二保护电压也是场效应管2的正常工作电压。 [0026] Further, with continued reference to FIG. 3 described above, the anti-reverse circuit provided in the bidirectional voltage clamp of the present embodiment may also be used when the reverse input pressure through the gate of the FET 2 - a second source voltage clamp protection voltage, the second voltage protection is the normal operating voltage FET 2. 即使电源电压的反相输入继续升高, 施加在场效应管2上的VGS均保持为第二保护电压,则可以防止场效应管2不会因输入过压而导致其GS管脚过压击穿,进而防止场效应管2被烧毁,保证防反接电路的稳定性。 Even inverting input supply voltage continues to rise, VGS is applied to the FET 2 on the average maintained at the second voltage protection, can be prevented FET 2 will not lead to overvoltage input pin overvoltage breakdown GS , thereby preventing the FET 2 is burned, to ensure the stability of the anti-reverse circuit. 与图2所示的现有技术中的防反接电路相比,本实施例通过双向电压箝位电路将场效应管2 的栅极_源极电压在反向输入过压时箝位为第二保护电压。 _ The gate-source voltage as compared with the prior art shown in FIG. 2 in the anti-reverse circuit of the present embodiment by a bidirectional voltage clamp FET 2 in the inverting input of the overvoltage clamping is two voltage protection. 在图2所示的现有技术中,当直流输入电源电压比较高的情况下,为了降低分压电阻的损耗,R1和R2的电阻取值就会比较大,由于Q1并联寄生二极管的存在,Q1的反向漏电流便不能忽略,如果直流电源极性反接,反向电压便通过Q1的漏电流施加在R2和R1上,如果R2上的电压高于-20V以上,也非常容易导致Q1由于GS管脚过压击穿而导致Q1烧毁,导致整个防反接电路失效。 In the prior art shown in FIG. 2, when the DC input voltage is relatively high, in order to reduce the loss of voltage dividing resistors, R1, and R2 the resistance values ​​will be relatively large, there is a parasitic diode in parallel with Q1 due, Q1 is reverse leakage current can not be ignored, if the DC reverse polarity, reverse voltage leakage current through Q1 will be applied to the R2 and R1, if the voltage across R2 higher than -20V, very easily lead to Q1 Since GS pin overvoltage breakdown caused Q1 burning, resulting in the failure of the anti-reverse circuit. 而在本实施例中,由于双向电压箝位电路具有电压箝位功能,在输入反接的情况下,双向电压箝位电路实现正向导通,其压降很小,且该压降不会因输入反向电压的升高而升高,则实现了防反接电路的反相过压保护功能,解决了现有技术中因输入反接过压引起的Q1烧毁的缺陷。 In the present embodiment, since the voltage clamp circuit having a bidirectional voltage clamping function in the case of the reverse input, bidirectional voltage clamp achieve positive conduction which small pressure drop and the pressure drop will not input temperature increased reverse voltage, overvoltage protection function is to achieve the anti-reverse inverter circuit Q1 to solve the prior art due to input received the anti-pressure-induced defects burned.

[0027] 进一步地,继续参照上述图3所示,本实施例的防反接电路还可以包括延时电容5,延时电容5与双向电压箝位电路1并联连接,用于在输入电压上电时,将施加在场效应管2上的输入电压进行缓启动处理。 [0027] Further, with continued reference to FIG. 3 described above, the anti-reverse circuit of this embodiment may further include a delay capacitor 5, 5 and the delay capacitor in parallel to a bidirectional voltage clamp connected to the input voltage when electricity is applied to the input voltage to the FET 2 is the slow start processing. 由于在电路中设置延时电容5,在直流电源刚刚接入时, 延时电容5与电压偏置电阻6—起构成一个RC定时充电电路,延时电容5的电压慢慢升高, 只有当延时电容5两端的电压升高到场效应管2的开启电压时,场效应管2才进入导通状态。 Since the delay capacitor 5 in the circuit, when the DC power source access immediately, and the delay capacitor 5 constitute a voltage from a bias resistor 6- timer RC charging circuit, the voltage of the delay capacitor 5 gradually increases, only when when the voltage across the capacitor 5 is increased to delay turn-on voltage of the FET 2, FET 2 into conduction only. 然后随着场效应管2的GS管脚两端的电压的逐步升高,场效应管2的导通内阻也不断减小,直到双向电压箝位电路1被击穿箝位时,场效应管2才完全进入饱和导通的状态。 Then gradually increased as the voltage across the FET GS pin 2, on-resistance FET 2 also continue to decrease until a bidirectional voltage clamp clamped breakdown, the FET 2 was completely turned into the saturated state. 而在图2所示的现有技术中,由于大功率直流供电回路在直流电源接通负载时,由于端子不可避免存在接触抖动和负载滤波电容的影响,往往在直流通电回路产生很大的电流尖峰和冲击电流,则使图2中的负载供电回路上的功率器件Q1损毁,系统不能正常工作。 In the prior art shown in FIG. 2, since the DC power supply circuit when the DC power supply connected to the load, and the load due to contact bounce filter capacitor terminal inevitable presence, often produce large currents in the DC power circuit and peak inrush current, the load power of the power device Q1 is in loop 2 of FIG damaged, the system can not work properly. 由此可见,本实施例提供的防反接电路通过增设延时电容可以克服现有技术中的上述缺陷,实现防反接电路的缓启动功能,提高电路的稳定性。 Thus, the anti-reverse circuit provided in the present embodiment can overcome the above drawbacks of the prior art by adding the delay capacitor, the slow start function to achieve anti-reverse circuit, to improve stability of the circuit.

[0028] 图4为本发明防反接电路实施例二的结构示意图,如图4所示,本实施例提供了一种具体的防反接电路,本实施例中的场效应管具体为NM0S管,且包含一个NM0S管。 [0028] Fig 4 a schematic view of the anti-reverse circuit configuration according to a second embodiment of the present invention, shown in Figure 4, the present embodiment provides a specific anti-reverse circuit, FET embodiment of the present embodiment is particularly NM0S tube, and the tube comprising a NM0S. 在本实施例中,NM0S管Q1的三个引脚G、S和D中,G为栅极,S为源极,D为漏极。 In the present embodiment, NM0S tube G Q1 of three pins, S and D, G is a gate, S a source, D is a drain. 其中在GS脚之间不加电压时,D脚和S脚之间的电阻RDSon无穷大,相当于将电源通路断开,GS脚电压大于开启电Vth时,DS间电阻RDSon快速减少到几毫欧的电阻值,相当于开关闭合。 GS wherein between the foot when no voltage is applied, the resistance RDSon D between the foot and the foot infinity S, corresponding to disconnect the power supply path, GS pin voltage Vth of power is greater than the open, the resistance between the DS RDSon quickly reduced to a few milliohms the resistance value corresponds to the switch is closed. 其中,开启电压Vth为M0S管器件固有的参数。 Wherein the threshold voltage Vth of the device-specific parameter M0S tube. 另外,NM0S管存在寄生的体二极管,在NM0S管未导通时,电流会从体二极管通过。 Further, the presence of the tube NM0S parasitic body diode, when NM0S tube is not conducting, current will pass from the body diode. 在本实施例中,双向电压箝位电路可以包括但不限于稳压二极管、电压抑制器和电压比较电路,本实施例以双向电压箝位电路为稳压二极管为例进行说明。 In the present embodiment, the bidirectional voltage clamp circuit may include but is not limited to the zener diode, the voltage suppressors and voltage comparison circuit, in the present embodiment is a bidirectional voltage clamp Zener diode as an example. 在本实施例中,NM0S管Q1的栅极G与稳压二极管D1的负极相连,并通过电压偏置电阻R1与电源正极VIN+相连;NM0S管Q1的漏极D与电源负极VIN-相连;NM0S管Q1的源极S与稳压二极管D1的正极相连,并通过负载电阻&与电源正极VIN+相连;NM0S管Q1 的体二极管的正极与Q1的源极S相连,其负极与Q1的漏极D相连。 In the present embodiment, the gate G and the cathode of zener diode D1 is connected NM0S transistor Q1, and a bias voltage + via the resistor R1 is connected to the positive supply voltage the VIN; NM0S connected to the drain D of the transistor Q1 and the negative power source VIN-; NM0S positive source S of transistor Q1 and zener diode D1 is connected to the positive supply voltage and & VIN + is connected via a load resistor; positive electrode and the source electrode S is connected to the body diode of Q1 NM0S transistor Q1, negative electrode and the drain D of Q1 connected.

[0029] 在本实施例中,以输入电压为24V为例进行说明,为使Q1能够正常工作,D1选取箝位电压为12V的稳压管,R1作为D1的限流电阻和Q1的电压偏置电阻。 [0029] In the present embodiment, the input voltage of 24V as an example, for the Q1 to work properly, the clamping select D1 zener voltage of 12V, a current limiting resistor Rl D1 and the bias voltage of Q1 set resistance. 当直流电源极性正确连接时,即VIN+接直流电源的正极,VIN-接直流电源的负极,在电源上电时,输入电源电压从0V开始升高,此时由于Q1的GS管脚两端的电压未达到Q1的开启电压Vth,则Q1处于断开状态。 When the dc power polarity is correctly connected, i.e., VIN + cathode connected to the positive electrode of the DC power source, DC power supply connected to VIN-, when an electrical power supply, the input supply voltage starts to rise from 0V, and the GS due to the pin across Q1 voltage does not reach the threshold voltage Vth of Q1, then Q1 is in the OFF state. 但由于Q1中存在寄生体二极管,且按照图4中的连接方式,输入电源电压上电时直流电源正极VIN+经过负载电阻&和Q1的体二极管形成电流回路,回到直流电源负极VIN-。 However, due to parasitic body diode Q1, and the connection according to the embodiment in FIG. 4, when the power DC voltage source positive VIN + and Q1 through the load resistor & diode current loop is formed in the body on the input supply voltage, back to the DC power supply negative VIN-. 而在直流电源的上电初期,由于输入电源电压较低,负载电阻还不能工作,负载电流较小,即使电流通过Q1的体二极管,也不会导致Q1上太大的压降损耗。 In the initial power direct current power supply, the input supply voltage is low, the load resistance can not work, the load current is small, even if the current through the body diode of Q1, the voltage drop will not cause too much loss on Q1.

[0030] 随着输入电源电压的继续升高,输入电源电压通过R1进行限流,施加在Dl、C1和Q1的GS管脚之间。 [0030] As the input supply voltage continues to rise, the input supply voltage to limit the current through R1, is applied between Dl, C1 and GS pins Q1. 由于电容C1的存在,电容C1两端的电压是缓慢升高的,此时由于C1两端的电压还不足以升高到D1的击穿电压,因此D1呈现开路状态。 Due to the presence of the capacitor C1, the voltage across the capacitor C1 is gradually increased, since the voltage across C1 at this time is not enough to increase the breakdown voltage of D1, D1 therefore presents an open circuit state. 经过一定的时间,当C1 的电压继续升高到Q1的开启电压时,Q1进入导通状态。 After a certain time, when the voltage of C1 continues to rise to the threshold voltage of Q1, Q1 into conduction. Q1进入导通状态后,其D管脚和S 管脚之间的内阻从无穷大迅速减小,且DS管脚之间的压降迅速降低,当DS管脚之间的压降 After Q1 into conduction state, the resistance between the pin and the D pin S rapidly decreases from the infinite, and the voltage drop between the DS pin decreases rapidly when the voltage drop between the pin DS

7减小到小于IV时,Ql的寄生体二极管由于不满足电压偏置而截止,电源回路的主电流全部该从Ql的DS管脚之间流过,寄生体二极管不再导通和流过电流。 IV is reduced to less than 7, Ql does not satisfy the parasitic body diode bias voltage is turned off, all of the main current circuit of the power flowing from between the DS pin Ql parasitic body diode conduction and no longer flows current.

[0031] Ql开始导通后,由于导通内阻还未达到最小,此时负载电路的滤波电容开始充电, 必然导致供电回路出现较大的冲击电流,而由于Ql内阻限制,抑制了冲击电流的突然增大。 [0031] After Ql begins to conduct, since the on-resistance has not yet reached the minimum, then the filter starts charging the capacitor load circuit, will inevitably lead to a larger power supply circuit of the inrush current, and because the internal resistance Ql limits, shock is suppressed a sudden increase in current. 随着Ql的GS管脚两端的电压逐渐上升,Ql的导通内阻不断减小,当电压上升到Dl的击穿电压时,Dl进入导通状态,由于Dl的电压箝位作用,将Ql的GS管脚两端的电压稳定在12V附近不再上升。 As the voltage across the pins GS Ql rises gradually, Ql decreasing the on-resistance, when the voltage rises to the breakdown voltage of Dl, Dl into a conducting state, the voltage clamping action Dl will Ql GS voltage across the pins stabilize not rise near 12V. 此时Ql结束缓启动状态,进入正常饱和导通状态。 At this time, the slow start Ql end state into the normal state of saturated conduction.

[0032] 如果此时输入直流电压出现波动,输入电源电压继续升高,由于稳压管的箝位电压的作用,确保Ql的GS管脚两端的电压不再随着电源电压升高而升高,则避免了此时输入电压过压导致Ql的GS管脚两端的电压过压击穿而烧毁Ql。 [0032] At this time, if the DC input voltage fluctuations, the input supply voltage continues to rise, due to the action of the zener clamping voltage to ensure that the voltage across the pins GS Ql no longer rises as the supply voltage rises , is avoided when the input voltage causes the voltage across the overvoltage GS pin overvoltage breakdown Ql Ql and burned. 当直流输入电源电压达到24V 时,Dl击穿,Ql的GS管脚两端的电压被箝位在12V左右,Ql进入饱和导通状态。 When the DC input voltage reaches 24V, Dl breakdown, the voltage across pins Ql GS is clamped at around 12V, Ql into the saturation conducting state. 当输入电源电压波动到48V时,由于Dl的正向稳压箝位作用,确保了Ql的GS管脚两端的电压被箝位在12V左右,Ql仍然可以稳定可靠的工作。 When the input supply voltage fluctuations to the 48V, Dl Since the forward regulator clamping action to ensure the voltage across pins Ql GS is clamped at around 12V, Ql still stable and reliable operation. [0033] 另外,在本实施例中,由于Cl的存在,在直流输入电源刚刚接入时,Rl和Cl构成了一个RC定时充电电路,Cl的电压慢慢升高。 [0033] Further, in the present embodiment, due to the presence of Cl, when the DC input power just access, Rl and Cl constitute an RC timer charging circuit, a voltage gradually rises Cl. 只有当Cl的电压升高到Ql的开启电压时,Ql 才进入导通状态。 Only when the voltage rises to the turn-on voltage Cl is Ql, Ql into conduction only. 然后随着Ql的GS管脚两端的电压逐步升高,Ql的导通内阻不断减小。 Then gradually increased as the voltage across the GS pin Ql, Ql decreasing the on-resistance. 直到Dl被击穿箝位时,Ql完全进入饱和导通的状态,实现了防反接电路的缓启动功能。 Dl clamped until breakdown, Ql, fully saturated into the conducting state, to achieve the function of preventing reverse slow start circuit.

[0034] 进一步地,在本实施例中,当直流输入电源的极性出现错误连接时,即VIN+接直流电源的负极,VIN-接直流电源的正极,输入电源电压上电时输入电源电压从OV开始升高,此时由于Ql的GS管脚两端的电压未达到开启电压,因此Ql处于断开状态。 [0034] Further, in the present embodiment, when the polarity of DC input connection error, i.e., VIN + is connected to the DC power supply negative electrode, positive electrode connected to a DC power source VIN-, when the input supply voltage from the power supply input voltage OV starts to rise, when the voltage across the pins Ql GS does not reach the turn-on voltage, so Ql in the open state. 但此时Ql 的寄生体二极管按照图4的连接方式,正好是截止的,可以防止上电时直流电流经过负载& 和Ql的体二极管形成电流回路,回到VIN+。 But this time Ql parasitic body diode according to the connection of Figure 4, is just turned off, the DC current through the load can be prevented and Ql & body diode current loop is formed at power back VIN +. 然而,在实际电路中,由于Ql的寄生体二极管存在几十UA级的漏电流,实际上VIN-会有微小漏电流从Ql的寄生体二极管的负极流到正极,经过Dl和Rl返回VIN+。 However, in an actual circuit, since the presence of dozens of UA-level leakage current of Ql parasitic body diode, VIN- actually be a slight leakage current flows from the positive electrode to the negative electrode of Ql parasitic body diode, Dl and Rl through return VIN +. 在此种状态下,Dl正向导通,呈现二极管导通特性,Dl的压降大约在-1.0V,并且由于稳压二极管的反向导通箝位功能,Dl的压降不会因输入反向电压的升高而升高,进而实现了防反接电路的反向过压保护功能。 In this state, Dl is forward, rendering diode conduction properties, Dl pressure drop of about -1.0 V, and since the reverse conducting clamp zener diode, Dl will not drop reverse input temperature increased voltage, so as to realize the function of the anti-reverse reverse voltage protection circuit.

[0035] 本实施例提供了一种防反接电路,通过在场效应管的GS的两端并联双向电压箝位电路,在正向输入过压时,由双向电压箝位电路将场效应管的GS两端的电压箝位在正常工作电压之内,在反向输入过压时,通过双向电压箝位电路也将场效应管的GS两端的电压箝位在正常工作电压之内;本实施例解决了现有技术中防反接电路存在的输入电压过压和反向输入电压过压导致MOS管击穿的问题,实现了直流输入防反接电路的输入过压保护功能和反向输入过压保护功能,且具备电路缓启动功能,拓展了电路的应用电压范围,提高了电路的可靠性。 [0035] The present embodiment provides an anti-reverse circuit, at both ends of the shunt FET GS bidirectional voltage clamp circuit, when the positive input overvoltage, by a bidirectional voltage clamp circuit of the FET GS across the voltage clamp at the normal operating voltage, when reverse input overvoltage, by a voltage clamp across the GS will be bidirectional voltage clamp FET is in the normal operating voltage; the present embodiment solves occurring prior art anti-reverse circuit input voltage input overvoltage and reverse over-voltage breakdown of the MOS transistor causes problems, to achieve the reverse input DC input overvoltage protection function and the anti-reverse input overvoltage circuit protection, and have slow-start circuit to expand the application of the voltage range of the circuit to improve the reliability of the circuit.

[0036] 图5为本发明防反接电路实施例三的结构示意图,如图5所示,本实施例提供了一种具体的防反接电路,本实施例中的场效应管具体为NMOS管,且包含多个并联连接的NMOS 管Q1、Q2...。 [0036] FIG. 5 is a schematic view of the invention the anti-reverse circuit configuration according to a third embodiment, shown in Figure 5, the present embodiment provides a specific anti-reverse circuit, FET embodiment of the present embodiment is particularly NMOS tube, and it includes a plurality of NMOS transistors connected in parallel with Q1, Q2 .... 在本实施例中,每个NMOS管(如图5中的Ql或Q2)的栅极G与稳压二极管Dl的负极相连,并通过电压偏置电阻Rl与电源正极VIN+相连;每个NMOS管的漏极D与电源负极VIN-相连;每个NMOS管Ql的源极S与稳压二极管Dl的正极相连,并通过负载电阻&与电源正极VIN+相连;每个NMOS管Ql的体二极管的正极与Ql的源极S相连,其负极与Q1的漏极D相连。 In the present embodiment, each gate G of the NMOS transistor (Ql, Q2 or FIG. 5) and the cathode of the zener diode Dl is connected, and a voltage + bias resistor Rl is connected to the positive supply voltage the VIN; each NMOS transistor the drain D is connected to the negative power supply VIN-; connected to the positive electrode and the source S of each of the zener diode Dl NMOS transistor Ql and & VIN + is connected to the positive supply voltage via a load resistor; each cathode of the body diode of the NMOS transistor Ql S connected to the source electrode of Ql, and its negative pole connected to the drain D of Q1. 本实施例通过采用多个NM0S管并联连接,增加了功率管的过电流能力, 由于稳压二极管D1的正向稳压箝位功能和反向导通箝位功能,可以实现对每个NM0S的输入过压保护和反压箝位保护,且多个NM0S管并联形成的漏电流也不会导致防反接电路的过压失效问题。 In this embodiment, using a plurality of tubes connected in parallel NM0S, increases the current capacity of the power through the tube, since the zener diode D1 is forward regulator clamping function and the reverse conducting clamping function, each input can be achieved in NM0S overvoltage protection clamp and back pressure, and the leakage current is formed by a plurality of parallel tubes NM0S overvoltage does not cause the anti-reverse circuit failures.

[0037] 图6为本发明防反接电路实施例四的结构示意图,如图6所示,本实施例提供了一种具体的防反接电路,本实施例中的场效应管具体为PM0S管Q1,双向电压箝位电路具体为稳压二极管D1。 [0037] Fig 6 a schematic view of the anti-reverse circuit configuration according to a fourth embodiment of the present invention shown in FIG. 6, the present embodiment provides a specific anti-reverse circuit, FET embodiment of the present embodiment is particularly PM0S tube Q1, in particular bidirectional voltage clamp Zener diode D1. 本实施例以包含一个PM0S管为例进行说明,包含多个并联的PM0S管的情况可以与上述图5类似,此处不再赘述。 In the present embodiment comprises a PM0S tube as an example, the case comprising a plurality of parallel tubes PM0S may be similar to the above-described FIG. 5, here omitted. 其中,PM0S管Q1的栅极G与D1的正极相连,并通过电压偏置电阻R1与电源负极VIN-相连;PM0S管Q1的源极S与D1的负极相连,并与电源正极VIN+相连;PM0S管Q1的漏极D通过负载&与电源负极VIN-相连;PM0S管Q1的体二极管的正极与Q1的源极S相连,其负极Q1与的漏极D相连。 Wherein the positive electrode of PMOS transistor Q1 is connected to gate G D1, and is connected to a bias voltage through resistor R1 and the negative power source VIN-; S is connected to the negative electrode of the PMOS transistor Q1 and D1 of the source, and is connected to the positive supply voltage + VIN; PM0S drain D of transistor Q1 is connected to the negative power source through a load & VIN-; the positive electrode and the source electrode S is connected to the body diode of Q1 PM0S transistor Q1, Q1 and its anode connected to the drain D. 本实施例将电路中的场效应管由NM0S管替换为PM0S管,在正向输入过压时,同样可以由D1将Q1的GS两端的电压箝位在正常工作电压之内,在反向输入过压时,通过D1也将Q1的GS两端的电压箝位在正常工作电压之内;本实施例解决了现有技术中防反接电路存在的输入电压过压和反向输入电压过压导致M0S管击穿的问题,实现了直流输入防反接电路的输入过压保护功能和反向输入过压保护功能,且具备电路缓启动功能,拓展了电路的应用电压范围,提高了电路的可靠性。 The circuit of the present embodiment, the FET is replaced by a tube PM0S NM0S, when the pressure over the forward input, likewise by D1 clamps the voltage across the GS Q1 is in the normal operating voltage, the inverting input overpressure, through D1 also clamps the voltage across the GS Q1 is in the normal operating voltage; the present embodiment solves the input voltage in the prior art anti-reverse input circuit overvoltage and reverse over-voltage lead M0S tube breakdown problems and achieve input DC input overvoltage protection circuit and reverse the anti-reverse input overvoltage protection, and includes a slow-start circuit, a voltage is applied to expand the range of the circuit, improving the reliability of the circuit sex.

[0038] 需要指出的是,本实施例中的PM0S管也可以如上述图5所示的为多个并联,具体连接方式与上述实施例类似,此处不再赘述。 [0038] It is noted that, in the embodiment according to the present embodiment may be PM0S tube as shown in FIG. 5 is a plurality of parallel connection with the specific embodiment similar to the embodiment described above, is not repeated here.

[0039] 图7为本发明防反接电路实施例五的结构示意图,如图7所示,本实施例提供了一种具体的防反接电路,本实施例中的场效应管具体为NM0S管。 Schematic structural diagram according to a fifth [0039] FIG. 7 of the present invention, the anti-reverse circuit embodiment shown in Figure 7, the present embodiment provides a specific anti-reverse circuit, FET embodiment of the present embodiment is particularly NM0S tube. 在本实施例中,双向电压箝位电路可以包括相互连接的基准电压源D1、第一分压电阻R2和第二分压电阻R3,为使Q1 能够正常工作,本实施例以采用TL431基准电压源为例进行说明。 In the present embodiment, the bidirectional voltage clamp circuit includes a reference voltage source may be connected to each other D1, a first voltage dividing resistor and the second dividing resistor R2 R3, Q1 order to work properly, the present embodiment to employ TL431 voltage reference source as an example. 在本实施例中,以输入电压为24V为例进行说明,R2,R3作为D1基准电压源的分压电阻网络,R1作为D1的负载电阻和NM0S管Q1的偏置电阻。 In the present embodiment, the input voltage of 24V as an example, R2, R3 D1 as a voltage dividing resistor network reference voltage source, a load resistor Rl and bias resistors NM0S transistor Q1 D1. 其中,相互串联的第一分压电阻R2和第二分压电阻R3与基准电压源D1并联连接,基准电压源D1的基准脚R连接在第一分压电阻R2和第二分压电阻R3之间。 Wherein each of the first series and the second dividing resistor R2 in parallel division resistors R3 D1 is connected to the reference voltage source, a reference voltage source R D1 is connected to a first reference pin dividing resistor and the second dividing resistor R2 to R3 between. 基准电压源D1的正极A为双向电压箝位电路的正极,基准电压源D1的负极K为双向电压箝位电路的负极。 D1 is a positive reference voltage source A bidirectional voltage clamp is positive, negative reference voltage source K is negative D1 bidirectional voltage clamp circuit.

[0040] 在本实施例中,NM0S管的三个引脚G、S和D中,G为栅极,S为源极,D为漏极。 [0040] In the present embodiment, three pins G NM0S tube, S and D, G is a gate, S a source, a drain D. 其中在GS脚之间不加电压时,D脚和S脚之间的电阻RDSon无穷大,相当于将电源通路断开, GS脚电压大于开启电Vth时,DS间电阻RDSon快速减少到几毫欧的电阻值,相当于开关闭合。 GS wherein between the foot when no voltage is applied, the resistance RDSon D between the foot and the foot infinity S, corresponding to disconnect the power supply path, GS pin voltage Vth of power is greater than the open, the resistance between the DS RDSon quickly reduced to a few milliohms the resistance value corresponds to the switch is closed. 其中,开启电压Vth为M0S管器件固有的参数。 Wherein the threshold voltage Vth of the device-specific parameter M0S tube. 另外,NM0S管存在寄生的体二极管,在NM0S管未导通时,电流会从体二极管通过。 Further, the presence of the tube NM0S parasitic body diode, when NM0S tube is not conducting, current will pass from the body diode. 在本实施例中,NM0S管Q1的栅极G与基准电压源D1的负极K以及分压电阻R2的一端连接;NM0S管Q1的漏极D与电源负极VIN-相连; NM0S管Q1的源极S与基准电压源D1的正极A及分压电阻R3的一端相连,并通过负载电阻&与电源正极VIN+相连。 In the present embodiment, the gate G and the reference voltage source D1 is a negative K NM0S transistor Q1 and an end of the voltage dividing resistor R2 is connected; NM0S connected to the drain D of the transistor Q1 and the negative power source VIN-; NM0S source transistor Q1 S D1 of the reference voltage source and one end of the positive electrode a dividing resistor R3 is connected, and is connected via a load resistor + & positive supply VIN. NM0S管Q1的体二极管的正极与Q1的源极S相连,其负极与Q1 的漏极D相连。 Q1 source and the cathode of the body diode of transistor Q1 NM0S S is connected to the negative electrode connected to the drain D of Q1. 基准电压源D1的基准脚R和分压电阻R2和R3的一端相连,分压电阻R2 的另一端连接到NM0S管Q1的栅极G ;分压电阻R3另一端连接到NM0S管Q1的源极S。 One end of the reference voltage source R D1 and the reference foot dividing resistors R2 and R3 is connected to the other end of the dividing resistor R2 is connected to the gate G of transistor Q1 NM0S; the other end of the voltage dividing resistor R3 is connected to the source of transistor Q1 NM0S S. 延时电容C1分别连接到NM0S管Q1的栅极G和NM0S管Q1的源极S。 Delay capacitor C1 are respectively connected to transistors Q1 NM0S gate G and the source of transistor Q1 NM0S S.

9[0041] 其中,当直流电源极性正确连接时,即VIN+接直流电源的正极,VIN-接直流电源的负极,在电源上电时,输入电源电压从0V开始升高,此时由于Q1的GS管脚两端的电压未达到Q1的开启电压Vth,则Q1处于断开状态。 9 [0041] wherein, when the DC power polarity is correctly connected, i.e., VIN + is connected to the positive DC power source, connected to the negative DC power source VIN-, when the power supply, the input supply voltage starts to rise from 0V, and the due Q1 GS voltage across the pin does not reach the threshold voltage Vth of Q1, then Q1 is in the OFF state. 但由于Q1中存在寄生体二极管,且按照图7 中的连接方式,输入电源电压上电时直流电源正极VIN+经过负载电阻&和Q1的体二极管形成电流回路,回到直流电源负极VIN-。 However, due to parasitic body diode Q1, and the connection according to the embodiment in FIG. 7, when the power DC voltage source positive VIN + and Q1 through the load resistor & diode current loop is formed in the body on the input supply voltage, back to the DC power supply negative VIN-. 而在直流电源的上电初期,由于输入电源电压较低,负载电阻还不能工作,负载电流较小,即使电流通过Q1的体二极管,也不会导致Q1上太大的压降损耗。 In the initial power direct current power supply, the input supply voltage is low, the load resistance can not work, the load current is small, even if the current through the body diode of Q1, the voltage drop will not cause too much loss on Q1.

[0042] 随着输入电源电压的继续升高,输入电源电压通过R1进行限流,施加在Dl,R2和R3分压电阻网络、C1和Q1的GS管脚之间。 [0042] As the input supply voltage continues to rise, the input supply voltage to limit the current through R1, is applied between Dl, R2 and R3 divider resistors, C1, and GS pins Q1. 由于电容C1的存在,电容C1两端的电压是缓慢升高的,此时由于C1两端的电压施加在分压电阻网络R2和R3的电压还不足以升高到D1 的基准脚R的击穿电压(D1基准电压=2.5V),因此D1呈现开路状态。 Due to the presence of the capacitor C1, the voltage across the capacitor C1 is slowly increased, in which case the voltage across C1 is applied in the voltage dividing resistors R2 and R3 of the network is not enough to increase the breakdown voltage of the reference pin D1 of R (D1 reference voltage = 2.5V), and therefore presents an open circuit state D1. 经过一定的时间, 当C1的电压继续升高到Q1的开启电压时,Q1进入导通状态。 After a certain time, when the voltage of C1 continues to rise to the threshold voltage of Q1, Q1 into conduction. Q1进入导通状态后,其D管脚和S管脚之间的内阻从无穷大迅速减小,且DS管脚之间的压降迅速降低,当DS管脚之间的压降减小到小于IV时,Q1的寄生体二极管由于不满足电压偏置而截至,电源回路的主电流全部该从Q1的DS管脚之间流过,寄生体二极管不再导通和流过电流。 After Q1 into conduction state, the resistance between the pin and the D pin S rapidly decreases from the infinite, and the voltage drop between the DS pin decreases rapidly when the voltage drop between the pins is reduced to DS less than IV, Q1 does not satisfy the parasitic body diode bias voltage ended, all of the main current supply circuit from the pin between DS Q1 flowing through the parasitic body diode conducting and no current flows.

[0043] 在Q1开始导通后,由于延时电容C1电荷未充满,Q1的导通内阻还未达到最小,此时负载电路的滤波电容开始充电,而由于Q1内阻限制,抑制了冲击电流的突然增大,实现了缓启动供电功能。 [0043] After Q1 begins to conduct, since the delay capacitor C1 is not fully charged, Q1 has not yet reached the minimum on-resistance, when the filter circuit starts charging the capacitive load, and limitations due to the internal resistance of Q1, shock is suppressed a sudden increase in current to achieve a soft-start power supply function. 随着Q1的GS管脚两端的电压逐渐上升,Q1的导通内阻不断减小,此时电阻分压网络R2和R3上的电压也不断升高,当分压电阻网路R2和R3上的电压上升到12V时,经过R2,R3的分压,D1基准电压源的基准脚R达到了2. 5V电压时,D1由截止进入导通状态,由于D1的导通,等效于短路了NM0S管Q1的栅极G和源极S之间的电压,使Q1 的GS电压不再上升,转而下降。 As the voltage across Q1 is gradually increased GS pin, Q1 is turned on decreasing resistance, then resistor divider network R2 and the voltage across R3 is also rising, when the network voltage dividing resistors R2 and R3 when the voltage rises to 12V, after the partial pressure of R2, R3, and R & lt reference pin D1 reaches the reference voltage source 2. 5V voltage, D1 into conduction by the oFF state, since D1 is turned on, is equivalent to a short circuit NM0S voltage between the gate G and the source of transistor Q1 is S, so that the GS voltage of Q1 does not rise, fall instead. 当Q1的GS电压下降时,分压电阻R2和R3的电压也下降, 当D1的R脚分压下降到2. 5V以下时,D1由导通转为截止状态,D1的截止又导致了NM0S管Q1的栅极G和源极S之间的电压回升。 When the GS voltage of Q1 decreases, voltage dividing resistors R2 and R3 also decreases when R D1 is reduced partial pressure foot 2. 5V or less, D1 is turned OFF from ON state, and D1 is led off NM0S voltage rises between the gate G of transistor Q1 and the source S. 这样周而复始,D1循环导通和截止,保证了NM0S管Q1的GS电压正向箝位在12V左右,确保Q1进入饱和导通,导通内阻最小。 This cycle, D1 turned on and off cycle, to ensure that the GS voltage of transistor Q1 is forward NM0S clamped about 12V, is turned on to ensure Q1 into saturation, the minimum on-resistance. 此时Q1结束缓启动状态,进入正常饱和导通状态。 At this time, the end of Q1 slow start state into the normal state of saturated conduction.

[0044] 如果此时输入直流电压出现波动,输入电源电压继续升高,分压电阻R2和R3的电压也升高,施加在D1基准R管脚的电压一旦超过2. 5V,就会导致D1导通,最终使Q1的GS 管脚两端的电压不再随着VIN电压升高而升高,避免了输入电压过压导致Q1的GS管脚两端的电压过压击穿而烧毁Q1。 [0044] At this time, if the DC input voltage fluctuations, the input supply voltage continues to rise, the voltage dividing resistors R2 and R3 of the voltage increases, the voltage applied once the pin D1 exceeds the reference R 2. 5V, it will lead to D1 turned on, eventually the voltage across Q1 is not GS pin as temperature increased voltage VIN, the input voltage to avoid the over-voltage causes the voltage across Q1 GS pin overvoltage breakdown burn Q1. 当直流输入电源电压达到24V时,Dl,R2,R3组成的双向电压箝位电路的共同作用,使Q1的GS管脚两端的电压被箝位在12V左右,Q1进入饱和导通状态。 Interaction when the DC input voltage reaches 24V, Dl, R2, R3 consisting of bidirectional voltage clamp, the voltage across Q1 pin GS is clamped at about 12V, Q1 into saturation conducting state. 当输入电源电压波动到48V时,仍然是D1,R2,R3组成的双向电压箝位电路的共同的正向稳压箝位作用,确保了Q1的GS管脚两端的电压被箝位在12V左右,Q1仍然可以稳定可靠的工作。 When the input supply voltage fluctuations to 48V, remains the common positive regulator clamping effect bidirectional voltage clamp circuit D1, R2, R3 composition, to ensure that the GS voltage across pins Q1 is clamped around 12V , Q1 can still work stable and reliable.

[0045] 另外,在本实施例中,由于C1的存在,在直流输入电源刚刚接入时,R1和C1构成了一个RC定时充电电路,C1的电压慢慢升高。 [0045] Further, in the present embodiment, due to the presence of C1, when the DC input power just access, R1, and C1 form an RC timer charging circuit, the voltage of C1 increases slowly. 只有当C1的电压升高到Q1的开启电压时,Q1 才进入导通状态。 Only when the voltage of C1 increases to the open voltage of Q1, Q1 of it into conduction. 然后随着Q1的GS管脚两端的电压逐步升高,Q1的导通内阻不断减小。 Then gradually increased as the voltage across pins GS Q1, Q1 of decreasing on-resistance. 直到D1,R2,R3组成的双向电压箝位电路被击穿箝位时,Q1完全进入饱和导通的状态,实现了防反接电路的缓启动功能。 The bidirectional voltage clamp circuit until D1, R2, R3 consisting of breakdown clamped, Ql fully into saturation conducting state, to achieve the function of preventing reverse slow start circuit. [0046] 进一步地,在本实施例中,当直流输入电源的极性出现错误连接时,即VIN+接直流电源的负极,VIN-接直流电源的正极,输入电源电压上电时输入电源电压从0V开始升高,此时由于Q1的GS管脚两端的电压未达到开启电压,因此Q1处于断开状态。 [0046] Further, in the present embodiment, when the polarity of DC input connection error, i.e., VIN + is connected to the DC power supply negative electrode, positive electrode connected to a DC power source VIN-, when the input supply voltage from the power supply input voltage raised from 0V, since at this time the voltage across Q1 GS pin does not reach the threshold voltage, and therefore Q1 is in the OFF state. 但此时Q1 的寄生体二极管按照图6的连接方式,正好是截止的,可以防止上电时直流电流经过负载& 和Q1的体二极管形成电流回路,回到VIN+。 But this time the parasitic body diode of the Q1 connection according to FIG. 6, is just turned off, the DC current through the load can be prevented & Q1 and the body diode current loop is formed on power, return to VIN +. 然而,在实际电路中,由于Q1的寄生体二极管存在几十UA级以上的漏电流,实际上VIN-会有漏电流从Q1的寄生体二极管的负极流到正极,经过D1和R1返回VIN+。 However, in an actual circuit, since there are more than several tens of UA stage Q1 drain current of the parasitic body diode, a leakage current flows actually VIN- positive electrode from the negative electrode of the parasitic body diode of Q1, D1 and R1 through return VIN +. 在此种状态下,D1基准电压源正向导通,呈现二极管导通特性,D1正向导通电压降大约在-1. 0V,实现了的反向电压箝位功能,同样D1的压降不会因输入反向电压的升高而升高,进而实现了防反接电路的反向过压保护功能。 In this state, a reference voltage source D1 forward conduction, the diode-characteristics presented, D1 forward voltage drop of about -1. 0V, to achieve the reverse voltage clamping function, the same pressure drop will not D1 input reverse voltage due to temperature increased, so as to realize the function of the anti-reverse reverse voltage protection circuit.

[0047] 本实施例提供了一种防反接电路,通过在场效应管的GS的两端并联由基准电压源和两个分压电阻组成的双向电压箝位电路,在正向输入过压时,由双向电压箝位电路将场效应管的GS两端的电压箝位在正常工作电压之内,在反向输入过压时,通过双向电压箝位电路也将场效应管的GS两端的电压箝位在正常工作电压之内;本实施例解决了现有技术中防反接电路存在的输入电压过压和反向输入电压过压导致M0S管击穿的问题,实现了直流输入防反接电路的输入过压保护功能和反向输入过压保护功能,且具备电路缓启动功能,拓展了电路的应用电压范围,提高了电路的可靠性。 [0047] When the present embodiment provides an anti-reverse circuit by bidirectional voltage clamp in parallel with both ends of the FET GS by the reference voltage source and two voltage dividing resistors, the positive-going voltage at the input the voltage clamp clamps the voltage across both ends of the GS GS by a bidirectional voltage clamp FET in the normal operating voltage, when reverse input overvoltage, by a bidirectional voltage clamp FET will positioned within the normal operating voltage; the present embodiment solves the input voltage in the prior art anti-reverse input circuit overvoltage and reverse over-voltage breakdown causes problems M0S tube, to achieve the anti-reverse DC input circuit input overvoltage protection and reverse input overvoltage protection, and includes a slow-start circuit, a voltage is applied to expand the range of the circuit, improving the reliability of the circuit.

[0048] 图8为本发明防反接电路实施例六的结构示意图,如图8所示,本实施例提供了一种具体的防反接电路,本实施例中的场效应管具体为NM0S管。 [0048] Figure 8 is a schematic view of the invention the anti-reverse circuit configuration according to a sixth embodiment, shown in Figure 8, the present embodiment provides a specific anti-reverse circuit, FET embodiment of the present embodiment is particularly NM0S tube. 在本实施例中,在上述图7 所示的实施例的基础之上,除了基准电压源D1、第一分压电阻R2、第二分压电阻R3之外,双向电压箝位电路还可以包括第三分压电阻R4和三极管Q0,本实施例仍采用TL431的基准电压源为例进行说明。 In the present embodiment, the basis of the embodiment shown in FIG. 7 on the above, in addition to the reference voltage source D1, a first voltage dividing resistor R2, a second voltage dividing resistor R3, a bidirectional voltage clamping circuit may further comprise third voltage dividing resistors R4 and transistors Q0, the present embodiment still uses the TL431 voltage reference example. 在本实施例中,以输入电压为24V为例进行说明,Q0选取PNP三极管,R2,R3作为D1基准电压源的分压电阻网络,R4作为D1的负载电阻和PNP三极管Q0的偏置电阻。 Dividing resistor network in the present embodiment, the input voltage of 24V as an example, select the PNP transistor Q0, R2, R3 as a reference voltage source, D1, R4 as load resistance and a PNP transistor Q0 D1 bias resistor. 其中,第三分压电阻R4串联在与第一分压电阻R2和第二分压电阻R3并联的基准电压源D1的支路中,且连接在电源正极VIN+与基准电压源D1的负极K之间,三极管Q0 的基极B连接在第三分压电阻R4和基准电压源D1的负极K之间;三极管Q0的集电极C为双向电压箝位电路的正极,三极管的发射极E为双向电压箝位电路的负极。 Wherein the third voltage dividing resistor R4 is connected in series with the first parallel branch of the dividing resistor and the second dividing resistor R2 R3 D1 of the reference voltage source, and connected at the cathode K of the negative power source voltage VIN + and reference D1, between, the base B of transistor Q0 is connected between the negative electrode K and the third voltage dividing resistors R4 of the reference voltage source D1; C emitter of transistor Q0 is a positive electrode collector bidirectional voltage clamp circuit, a bidirectional triode voltage E negative clamp circuit.

[0049] 在本实施例中,NM0S管的三个引脚G、S和D中,G为栅极,S为源极,D为漏极。 [0049] In the present embodiment, three pins G NM0S tube, S and D, G is a gate, S a source, a drain D. 其中在GS脚之间不加电压时,D脚和S脚之间的电阻RDSon无穷大,相当于将电源通路断开, GS脚电压大于开启电Vth时,DS间电阻RDSon快速减少到几毫欧的电阻值,相当于开关闭合。 GS wherein between the foot when no voltage is applied, the resistance RDSon D between the foot and the foot infinity S, corresponding to disconnect the power supply path, GS pin voltage Vth of power is greater than the open, the resistance between the DS RDSon quickly reduced to a few milliohms the resistance value corresponds to the switch is closed. 其中,开启电压Vth为M0S管器件固有的参数。 Wherein the threshold voltage Vth of the device-specific parameter M0S tube. 另外,NM0S管存在寄生的体二极管,在NM0S管未导通时,电流会从体二极管通过。 Further, the presence of the tube NM0S parasitic body diode, when NM0S tube is not conducting, current will pass from the body diode. 在本实施例中,NM0S管Q1的栅极G与PNP三极管Q0的发射极E,电阻R4,电阻2的一端连接;NM0S管Q1的;NM0S管Q1的漏极D与电源负极VIN-相连;NM0S管Q1的源极S与PNP三极管Q0的集电极C及D1基准电压源TL431 的正极A及分压电阻R3的一端相连,并通过负载电阻&与电源正极VIN+相连;NM0S管Q1 的体二极管的正极与Q1的源极S相连,其负极与Q1的漏极D相连。 In the present embodiment, NM0S G gate of Q1 and the emitter electrode of the PNP transistor Q0 E, resistor R4, a resistor 2 is connected to one end; Q1 is NM0S; NM0S drain D of Q1 and the negative power source connected to VIN-; source NM0S tube Q1 is S and the collector C, and D1 reference voltage source TL431 the PNP transistor Q0 positive electrode a and the one end of the dividing resistor R3 is connected, and & positive supply VIN + is connected via a load resistor; body diode NM0S transistor Q1 the positive electrode and the source S of Q1 is connected to the negative electrode connected to the drain D of Q1. NPN三极管Q0的基极B与基准电压源D1的负极K及限流电阻R4相连;基准电压源D1的基准脚R和分压电阻R2 和R3的一端相连,分压电阻R2另一端连接到NM0S管Q1的栅极G ;分压电阻R3另一端连接到NM0S管Q1的源极S。 The base B and the reference voltage source D1 of NPN transistor Q0 negative electrode K and a current limiting resistor R4 connected; connected to a reference voltage source D1 reference pin R and one end of the voltage dividing resistors R2 and R3, voltage dividing resistors R2 and the other end connected to the NM0S the gate G of transistor Q1; the other end of the voltage dividing resistor R3 is connected to the source of transistor Q1 NM0S S. 延时电容C1分别连接到NM0S管Q1的栅极G和NM0S管Q1的源极S。 Delay capacitor C1 are respectively connected to transistors Q1 NM0S gate G and the source of transistor Q1 NM0S S. [0050] 其中,当直流电源极性正确连接时,即VIN+接直流电源的正极,VIN-接直流电源的负极,在电源上电时,输入电源电压从0V开始升高,此时由于Q1的GS管脚两端的电压未达到Q1的开启电压Vth,则Q1处于断开状态。 [0050] wherein, when the DC power polarity is correctly connected, i.e., VIN + cathode connected to the positive electrode of the DC power source, DC power supply connected to VIN-, when an electrical power supply, the input supply voltage starts to rise from 0V, and the Q1 is due GS voltage across the pin does not reach the threshold voltage Vth of Q1, then Q1 is in the OFF state. 但由于Q1中存在寄生体二极管,且按照图8 中的连接方式,输入电源电压上电时直流电源正极VIN+经过负载电阻&和Q1的体二极管形成电流回路,回到直流电源负极VIN-。 However, due to parasitic body diode Q1, and the connection according to the embodiment in FIG. 8, when the power DC voltage source positive VIN + and Q1 through the load resistor & diode current loop is formed in the body on the input supply voltage, back to the DC power supply negative VIN-. 而在直流电源的上电初期,由于输入电源电压较低,负载电阻还不能工作,负载电流较小,即使电流通过Q1的体二极管,也不会导致Q1上太大的压降损耗。 In the initial power direct current power supply, the input supply voltage is low, the load resistance can not work, the load current is small, even if the current through the body diode of Q1, the voltage drop will not cause too much loss on Q1.

[0051] 随着输入电源电压的继续升高,输入电源电压通过R1进行限流,施加在Q0,R4,R2 和R3分压电阻网络、C1和Q1的GS管脚之间。 [0051] As the input supply voltage continues to rise, the input supply voltage to limit the current through R1, is applied between Q0, R4, R2 and R3 divider resistors, C1, and GS pins Q1. 由于电容C1的存在,电容C1两端的电压是缓慢升高的,此时由于C1两端的电压施加在分压电阻网络R2和R3的电压还不足以升高到D1的基准R的击穿电压(D1基准电压=2. 5V),因此D1呈现开路状态,PNP三极Q0的基极得不到电压偏置,Q0呈现开路状态。 Due to the presence of the capacitor C1, the voltage across the capacitor C1 is slowly increased, in which case the voltage across C1 is applied in the voltage dividing resistors R2 and R3 of the network is not enough to increase the breakdown voltage of the reference D1 of R ( reference voltage D1 = 2. 5V), and therefore it presents an open circuit state D1, PNP Q0 tripolar base bias voltage not, Q0 exhibits an open state. 经过一定的时间,当C1的电压继续升高到Q1的开启电压时,Q1进入导通状态。 After a certain time, when the voltage of C1 continues to rise to the threshold voltage of Q1, Q1 into conduction. Q1进入导通状态后,其D管脚和S管脚之间的内阻从无穷大迅速减小,且DS管脚之间的压降迅速降低,当DS管脚之间的压降减小到小于IV时,Q1的寄生体二极管由于不满足电压偏置而截至,电源回路的主电流全部该从Q1的DS管脚之间流过,寄生体二极管不再导通和流过电流。 After Q1 into conduction state, the resistance between the pin and the D pin S rapidly decreases from the infinite, and the voltage drop between the DS pin decreases rapidly when the voltage drop between the pins is reduced to DS less than IV, Q1 does not satisfy the parasitic body diode bias voltage ended, all of the main current supply circuit from the pin between DS Q1 flowing through the parasitic body diode conducting and no current flows.

[0052] 在Q1开始导通后,由于延时电容C1电荷未充满,Q1的导通内阻还未达到最小,此时负载电路的滤波电容开始充电,而由于Q1内阻限制,抑制了冲击电流的突然增大,实现了缓启动供电功能。 [0052] After Q1 begins to conduct, since the delay capacitor C1 is not fully charged, Q1 has not yet reached the minimum on-resistance, when the filter circuit starts charging the capacitive load, and limitations due to the internal resistance of Q1, shock is suppressed a sudden increase in current to achieve a soft-start power supply function. 随着Q1的GS管脚两端的电压逐渐上升,Q1的导通内阻不断减小,此时电阻分压网络R2和R3上的电压也不断升高,当反压电阻网路的电压上升到12V时,经过R2,R3的分压,当D1基准电压源的基准脚R达到了2. 5V电压时,D1由截止进入导通状态。 As the voltage across Q1 is gradually increased GS pin, Q1 is decreasing on-resistance, then resistor divider network R2 and R3 of the voltage rising too, when the voltage of the counter-pressure rises to a resistive network when 12V, after the partial pressure of R2, R3, and D1 as the reference voltage source R foot reference voltage is reached 2. 5V, D1 into conduction by the oFF state. 由于D1的导通,R4出现了电压降,Q0的BE极间获得正向偏置,Q0由截止进入导通状态,Q0 一旦进入导通状态,等效于短路了NM0S管Q1的栅极G和源极S之间的电压,使Q1的GS电压不再上升,转而下降。 Since D1 is turned on, R4 voltage drop occurs, the BE Q0 is obtained between the forward bias electrode, Q0 into a conducting state by the stop, Q0 once into a conducting state, the short circuit is equivalent to the gate of transistor Q1 G NM0S and the voltage between the source electrode S, so that the GS voltage of Q1 does not rise, fall instead. 当Q1的GS电压下降导致,分压电阻R2和R3的电压下降,使D1的R脚分压下降到2. 5V以下时,D1由导通转为截止状态,D1的截止引发了Q0的截止。 When the GS voltage of Q1 decreases cause, when the voltage dividing resistors R2 and R3 of the voltage drop, the feet of the R D1 partial pressure drop of 2. 5V or less, D1 is turned OFF from ON state, the trigger D1 is cut off Q0 of . Q0的截止又导致了NM0S管Q1的栅极G和源极S之间的电压回升。 Q0 in turn results in the cutoff voltage rises between the gate G NM0S transistor Q1 and the source S. 这样周而复始,D1和Q0循环导通和截止,保证了NM0S管Q1的GS电压正向箝位在12V左右,确保Q1进入饱和导通, 导通内阻最小。 This cycle, D1 and Q0 cycle on and off to ensure that the GS voltage of transistor Q1 is forward NM0S clamped about 12V, is turned on to ensure Q1 into saturation, the minimum on-resistance. 此时Q1结束缓启动状态,进入正常饱和导通状态。 At this time, the end of Q1 slow start state into the normal state of saturated conduction.

[0053] 如果此时输入直流电压出现波动,输入电源电压继续升高,分压电阻R2和R3的电压也升高,施加在D1基准R管脚的电压一旦超过2. 5V,就会导致Q0导通,进而降低分压电阻R2和R3的电压,最终使Q1的GS管脚两端的电压不再随着VIN电压升高而升高,避免了输入电压过压导致Q1的GS管脚两端的电压过压击穿而烧毁Q1。 [0053] At this time, if the DC input voltage fluctuations, the input supply voltage continues to rise, the voltage dividing resistors R2 and R3 of the voltage increases, the voltage applied once the pin D1 exceeds the reference R 2. 5V, will lead Q0 turned on, thereby reducing the voltage dividing resistors R2 and R3, and eventually the voltage across Q1 is not GS pin voltage VIN as temperature increased, the input voltage to avoid overvoltage GS lead ends of the pins Q1 overvoltage breakdown burn Q1. 当直流输入电源电压达到24V时,Dl,Q0, R2,R3,R4组成的双向电压箝位电路的共同作用,使Q1的GS管脚两端的电压被箝位在12V左右,Q1进入饱和导通状态。 Interaction when the DC input voltage reaches 24V, Dl, Q0, R2, R3, R4 consisting of bidirectional voltage clamp, the voltage across Q1 pin GS is clamped at about 12V, Q1 is turned on into saturation status. 当输入电源电压波动到48V时,仍然是D1, Q0, R2,R3,R4组成的双向电压箝位电路的共同的正向稳压箝位作用,确保了Q1的GS管脚两端的电压被箝位在12V左右,Q1仍然可以稳定可靠的工作。 When the input supply voltage fluctuations to 48V, remains the common positive regulator clamping effect bidirectional voltage clamp circuit D1, Q0, R2, R3, R4 composition, to ensure that the voltage across Q1 is clamped to the pin GS bit about 12V, Q1 still be stable and reliable work.

[0054] 另外,在本实施例中,由于C1的存在,在直流输入电源刚刚接入时,R1和C1构成了一个RC定时充电电路,C1的电压慢慢升高。 [0054] Further, in the present embodiment, due to the presence of C1, when the DC input power just access, R1, and C1 form an RC timer charging circuit, the voltage of C1 increases slowly. 只有当C1的电压升高到Q1的开启电压时,Q1 才进入导通状态。 Only when the voltage of C1 increases to the open voltage of Q1, Q1 of it into conduction. 然后随着Q1的GS管脚两端的电压逐步升高,Q1的导通内阻不断减小。 Then gradually increased as the voltage across pins GS Q1, Q1 of decreasing on-resistance. 直到Dl,Q0, R2,R3,R4组成的双向电压箝位电路被击穿箝位时,Q1完全进入饱和导通的状态,实现了防反接电路的缓启动功能。 The bidirectional voltage clamp circuit until Dl, Q0, R2, R3, R4 breakdown clamped composition, Ql fully into saturation conducting state, to achieve the function of preventing reverse slow start circuit.

[0055] 进一步地,在本实施例中,当直流输入电源的极性出现错误连接时,即VIN+接直流电源的负极,VIN-接直流电源的正极,输入电源电压上电时输入电源电压从0V开始升高,此时由于Q1的GS管脚两端的电压未达到开启电压,因此Q1处于断开状态。 [0055] Further, in the present embodiment, when the polarity of DC input connection error, i.e., VIN + is connected to the DC power supply negative electrode, positive electrode connected to a DC power source VIN-, when the input supply voltage from the power supply input voltage raised from 0V, since at this time the voltage across Q1 GS pin does not reach the threshold voltage, and therefore Q1 is in the OFF state. 但此时Q1 的寄生体二极管按照图8的连接方式,正好是截止的,可以防止上电时直流电流经过负载& 和Q1的体二极管形成电流回路,回到VIN+。 But this time the parasitic body diode of the Q1 is connected according to FIG. 8, just off, the DC current through the load can be prevented & Q1 and the body diode current loop is formed on power, return to VIN +. 然而,在实际电路中,由于Q1的寄生体二极管存在几十UA级以上的漏电流,实际上VIN-会有漏电流从Q1的寄生体二极管的负极流到正极,经过D1和R1返回VIN+。 However, in an actual circuit, since there are more than several tens of UA stage Q1 drain current of the parasitic body diode, a leakage current flows actually VIN- positive electrode from the negative electrode of the parasitic body diode of Q1, D1 and R1 through return VIN +. 在此种状态下,D1基准电压源正向导通,呈现二极管导通特性,D1正向导通电压降大约在-1.0V,实现了的反向电压箝位功能,同样D1的压降不会因输入反向电压的升高而升高,进而实现了防反接电路的反向过压保护功能。 In this state, a reference voltage source D1 forward conduction, the diode-characteristics presented, D1 forward voltage drop of about -1.0 V, to achieve the reverse voltage clamping function, the same pressure drop will not D1 reverse voltage input temperature increased, so as to realize the function of the anti-reverse reverse voltage protection circuit.

[0056] 本实施例提供了一种防反接电路,通过在场效应管的GS的两端并联由基准电压源、三极管和三个分压电阻组成的双向电压箝位电路,在正向输入过压时,由双向电压箝位电路将场效应管的GS两端的电压箝位在正常工作电压之内,在反向输入过压时,通过双向电压箝位电路也将场效应管的GS两端的电压箝位在正常工作电压之内;本实施例解决了现有技术中防反接电路存在的输入电压过压和反向输入电压过压导致M0S管击穿的问题, 实现了直流输入防反接电路的输入过压保护功能和反向输入过压保护功能,且具备电路缓启动功能,拓展了电路的应用电压范围,提高了电路的可靠性。 [0056] The present embodiment provides an anti-reverse circuit by bidirectional voltage clamp in parallel with both ends of the GS of the FET by the reference voltage source, and the three transistors of the voltage dividing resistors, the positive input through the when pressed, the bidirectional voltage clamp circuit clamps the voltage across the GS of the FET in the normal operating voltage, the reverse input overvoltage, by a bidirectional voltage clamping circuit GS will be across the FET voltage clamp in the normal operating voltage; the present embodiment solves the input voltage in the prior art anti-reverse input circuit overvoltage and reverse over-voltage breakdown causes problems M0S tube, to achieve a DC input counter input overvoltage protection and reverse connection input overvoltage protection circuit, and includes a slow-start circuit, a voltage is applied to expand the range of the circuit, improving the reliability of the circuit.

[0057] 本实施例还提供了一种通讯设备,可以包括上述图3-图8中任一所述的防反接电路,通讯设备可以包括需要直流电源输入的交换机和路由器等。 [0057] The present embodiment further provides a communication apparatus may include the above-described Figures 3 to 8 of the anti-reverse circuit according to any one of the communication devices may include switches and routers require DC power input.

[0058] 图9为本发明防反接处理方法实施例的流程图,如图9所示,本实施例提供的防反接处理方法可以具体采用上述图3-图8中所示的防反接电路,具体工作原理和工作过程此处不再赘述。 [0058] FIG. 9 anti-reverse flow diagram processing method of the embodiment of the present invention, shown in Figure 9, the present embodiment provides anti-reverse processing method may be particularly employed in the above-described anti-anti shown in Figures 3 to 8 access circuit, the specific working principle and the process is not repeated here. 本实施提供的防反接处理方法具体可以包括如下步骤: Anti-reverse processing method provided by the present embodiment may specifically include the following steps:

[0059] 步骤901,在正向输入过压时,通过并联连接在场效应管的栅极-源极的两端的双向电压箝位电路将所述场效应管的栅极_源极电压箝位为第一保护电压,所述第一保护电压为所述场效应管的正常工作电压。 [0059] Step 901, the positive input overpressure, through the parallel connected between the gate of the FET - bidirectional voltage clamp across the source _ the gate-source voltage clamp FET is a first protection voltage, the protection voltage to said first normal operating voltage FET.

[0060] 进一步地,本实施例提供的防反接处理方法还可以包括如下步骤:步骤902,在反向输入过压时,通过所述双向电压箝位电路将所述场效应管的栅极-源极电压箝位为第二保护电压,所述第二保护电压为所述场效应管的正常工作电压。 [0060] Further, the anti-reverse processing method provided in this embodiment may further include the following steps: Step 902, when a reverse input overvoltage, by the bidirectional voltage clamp circuit to the gate of FET - a second source voltage clamp protection voltage, the second voltage is the normal operating voltage protection of the FET.

[0061] 更进一步地,本实施例提供的防反接处理方法还可以包括如下步骤:步骤903,在输入电压上电时,通过与所述双向电压箝位电路并联连接的延时电容将施加在所述场效应管上的输入电压进行缓启动处理。 [0061] Furthermore, the anti-reverse processing method provided in this embodiment may further include the following steps: Step 903, when the input voltage, via a delay capacitor connected in parallel with the bidirectional voltage clamp is applied input voltage on the FET soft start process is performed.

[0062] 需要指出的是,在本实施例中,上述步骤901-903之间不存在严格的时序关系,以上三个步骤可以同时执行,还可以根据实际情况调换顺序执行,此处不再赘述。 [0062] It is noted that, in the present embodiment, the above-described steps were not present a strict timing relationship between 901-903, three or more steps may be performed simultaneously, the execution order can also be exchanged in accordance with the actual situation, is not repeated here .

[0063] 本实施例提供了一种防反接处理方法,通过在场效应管的GS的两端并联双向电压箝位电路,在正向输入过压时,由双向电压箝位电路将场效应管的GS两端的电压箝位在正常工作电压之内,在反向输入过压时,通过双向电压箝位电路也将场效应管的GS两端的电压箝位在正常工作电压之内;本实施例解决了现有技术中防反接电路存在的输入电压过压和反向输入电压过压导致M0S管击穿的问题,实现了直流输入防反接电路的输入过压保 [0063] The present embodiment provides an anti-reverse processing method, both ends of the shunt FET GS bidirectional voltage clamp circuit, when the positive input overvoltage, by a bidirectional voltage clamp circuit FET GS across the voltage clamp at the normal operating voltage, when reverse input overvoltage, by a voltage clamp across the GS will be bidirectional voltage clamp FET is in the normal operating voltage; the present embodiment solves the input voltage input over existing prior art anti-reverse input circuit overvoltage and reverse over-voltage breakdown causes problems M0S tube, to achieve the anti-reverse input DC voltage protection circuit

13护功能和反向输入过压保护功能,且具备电路缓启动功能,拓展了电路的应用电压范围,提高了电路的可靠性。 Protection function 13 and an inverting input overvoltage protection, and includes a slow-start circuit, a voltage is applied to expand the range of the circuit, improving the reliability of the circuit.

[0064] 本领域普通技术人员可以理解:实现上述方法实施例的全部或部分步骤可以通过程序指令相关的硬件来完成,前述的程序可以存储于一计算机可读取存储介质中,该程序在执行时,执行包括上述方法实施例的步骤;而前述的存储介质包括:R0M、RAM、磁碟或者光盘等各种可以存储程序代码的介质。 [0064] Those of ordinary skill in the art can be appreciated: realize all or part of the steps of the method described above may be implemented by a program instructing relevant hardware to complete, the program may be stored in a computer readable storage medium, the program execution when, comprising the step of performing the above-described embodiment of the method; and the storage medium comprising: a variety of medium may store program codes R0M, RAM, magnetic disk, or optical disk.

[0065] 最后应说明的是:以上实施例仅用以说明本发明的技术方案,而非对其限制;尽管参照前述实施例对本发明进行了详细的说明,本领域的普通技术人员应当理解:其依然可以对前述各实施例所记载的技术方案进行修改,或者对其中部分技术特征进行等同替换;而这些修改或者替换,并不使相应技术方案的本质脱离本发明各实施例技术方案的精神和范围。 [0065] Finally, it should be noted that: the above embodiments are intended to illustrate the present invention, rather than limiting;. Although the present invention has been described in detail embodiments, those of ordinary skill in the art should be understood: may still be made to the technical solutions described in each embodiment of the modified or part of the technical features equivalents; as such modifications or replacements do not cause the essence of corresponding technical solutions to depart from the technical solutions of the embodiments of the present invention and scope.

Claims (11)

  1. 一种防反接电路,其特征在于,包括连接在电源正极与电源负极之间的电压偏置电阻、双向电压箝位电路和至少一个场效应管,其中,所述电压偏置电阻与所述场效应管的栅极相连,用于对所述场效应管进行导通偏置,所述双向电压箝位电路并联连接在所述场效应管的栅极-源极的两端,所述双向电压箝位电路用于在正向输入过压时,将所述场效应管的栅极-源极电压箝位为第一保护电压,所述第一保护电压为所述场效应管的正常工作电压。 An anti-reverse circuit, characterized in that it comprises connected between the power supply positive electrode and the negative bias resistors bidirectional voltage clamp and at least one field effect transistor, wherein said bias resistor and the voltage FET gate is connected to the bias FET turned on, the bidirectional voltage clamp is connected in parallel to the FET gate - source at both ends of the bidirectional voltage clamping circuit used in the forward input overvoltage, the gate of the FET - a first source electrode voltage clamp protection voltage, the protection voltage of the first FET work Voltage.
  2. 2.根据权利要求1所述的电路,其特征在于,所述双向电压箝位电路还用于在反向输入过压时,将所述场效应管的栅极_源极电压箝位为第二保护电压,所述第二保护电压为所述场效应管的正常工作电压。 The circuit according to claim 1, wherein said bidirectional voltage clamp circuit is further configured to reverse the input overvoltage, the gate of the FET source electrode voltage clamp _ for the first two protection voltage, the protection voltage to said second normal operating voltage FET.
  3. 3.根据权利要求2所述的电路,其特征在于,还包括:延时电容,与所述双向电压箝位电路并联连接,用于在输入电压上电时,将施加在所述场效应管上的输入电压进行缓启动处理。 The circuit according to claim 2, characterized in that, further comprising: a delay capacitor, in parallel with the bidirectional voltage clamp connected to the power input voltage, is applied to the FET input voltage will be slow start treatment.
  4. 4.根据权利要求3所述的电路,其特征在于,所述双向电压箝位电路为电压比较电路、 稳压二极管、电压抑制器。 4. The circuit of claim 3, wherein the bidirectional voltage clamp circuit is a voltage comparator circuit, a zener diode, voltage suppressor.
  5. 5.根据权利要求3所述的电路,其特征在于,所述双向电压箝位电路包括相互连接的基准电压源、第一分压电阻和第二分压电阻;相互串联的所述第一分压电阻和所述第二分压电阻与所述基准电压源并联连接,所述基准电压源的基准脚连接在所述第一分压电阻和所述第二分压电阻之间;所述基准电压源的正极为所述双向电压箝位电路的正极,所述基准电压源的负极为所述双向电压箝位电路的负极。 The circuit according to claim 3, wherein said bidirectional voltage clamp includes a reference voltage source connected to each other, a first dividing resistor and the second voltage dividing resistor; said first sub-series with each other resistor and the voltage dividing resistor and the second reference voltage source connected in parallel to the reference pin of the reference voltage source connected between said first voltage dividing resistor and the second voltage dividing resistor; the reference the positive electrode is the positive electrode of the bidirectional voltage clamp voltage source, the negative reference voltage source of the negative electrode is extremely bidirectional voltage clamp circuit.
  6. 6.根据权利要求5所述的电路,其特征在于,所述双向电压箝位电路还包括三极管和第三分压电阻;所述第三分压电阻串联在与所述第一分压电阻和所述第二分压电阻并联的所述基准电压源的支路中,且连接在所述电源正极与所述基准电压源的负极之间,所述三极管的基极连接在所述第三分压电阻和所述基准电压源的负极之间;所述三极管的集电极为所述双向电压箝位电路的正极,所述三极管的发射极为所述双向电压箝位电路的负极。 The circuit as claimed in claim 5, wherein said bidirectional voltage clamp transistor and further comprises a third voltage dividing resistor; said third voltage dividing resistor connected in series with the first voltage dividing resistor and the second sub-branch of the reference voltage source voltage resistor in parallel, and the power source connected between said positive electrode and the negative reference voltage source, the base of the transistor connected between the third branch resistor between the negative electrode and the reference voltage source; a positive electrode collector of the transistor of the bidirectional voltage clamp circuit, the transistor emitter to the anode of the bidirectional voltage clamp.
  7. 7.根据权利要求4-6中任一项所述的电路,其特征在于,当所述场效应管为N沟信道金属氧化物半导体场效应管时,所述场效应管的栅极与所述双向电压箝位电路的负极相连, 并通过电压偏置电阻与所述电源正极相连;所述场效应管的漏极与所述电源负极相连;所述场效应管的源极与所述双向电压箝位电路的正极相连,并通过负载电阻与所述电源正极相连;所述场效应管的体二极管的正极与所述场效应管的源极相连,其负极与所述场效应管的漏极相连;或者当所述场效应管为P沟信道金属氧化物半导体场效应管时,所述场效应管的栅极与所述双向电压箝位电路的正极相连,并通过电压偏置电阻与所述电源负极相连;所述场效应管的源极与所述双向电压箝位电路的负极相连,并与所述电源正极相连;所述场效应管的漏极通过负载电阻与所述电源负极相连 7. A circuit according to any one of claims 4-6, characterized in that, when the gate is the N-channel FET channel metal oxide semiconductor field effect transistor, said field effect transistor and the the negative electrode of said bidirectional voltage clamp is connected, and connected to the positive supply voltage via a bias resistor; and a drain of the FET is connected to the negative power supply; a source electrode of the FET and the bidirectional voltage clamping circuit is connected to the positive electrode, and connected to the positive supply via a load resistor; cathode and the source of FET body diode of the FET is connected to a drain of the FET and its cathode is connected to the gate; or when the FET is a P channel trench metal oxide semiconductor field effect transistor, a gate connected to the positive electrode of the circuit of the bidirectional voltage clamp FET, and through bias resistors and the power supply is connected to the negative electrode; a source of said FET is connected to the negative of the bidirectional voltage clamp and connected to the power supply positive electrode; a drain electrode of the FET and via a load resistor to the negative power supply connection 所述场效应管的体二极管的正极与所述场效应管的源极相连,其负极与所述场效应管的漏极相连。 The positive electrode body diode of the FET and the source of the FET is connected to its cathode connected to the drain of the FET.
  8. 8. 一种防反接处理方法,其特征在于,包括:在正向输入过压时,通过并联连接在场效应管的栅极-源极的两端的双向电压箝位电路将所述场效应管的栅极_源极电压箝位为第一保护电压,所述第一保护电压为所述场效应管的正常工作电压。 An anti-reverse processing method characterized by comprising: input overvoltage in the forward, connected in parallel to the gate of the FET - bidirectional voltage clamp across the source electrode of the FET _ the gate-source voltage clamp to a first voltage protection, said protection voltage to said first normal operating voltage FET.
  9. 9.根据权利要求8所述的方法,其特征在于,还包括:在反向输入过压时,通过所述双向电压箝位电路将所述场效应管的栅极-源极电压箝位为第二保护电压,所述第二保护电压为所述场效应管的正常工作电压。 9. The method according to claim 8, characterized in that, further comprising: reverse input overvoltage, by the bidirectional voltage clamp FET the gate - source voltage is clamped to a second protection voltage, the second voltage is the normal operating voltage protection of the FET.
  10. 10.根据权利要求8所述的方法,其特征在于,还包括:在输入电压上电时,通过与所述双向电压箝位电路并联连接的延时电容将施加在所述场效应管上的输入电压进行缓启动处理。 10. The method according to claim 8, characterized in that, further comprising: when the input voltage is a time-delay capacitor and the bidirectional voltage clamp circuit connected in parallel to the applied field effect tube input voltage soft-start process.
  11. 11. 一种通讯设备,其特征在于,包括权利要求1-7中任一项所述的防反接电路。 11. A communication apparatus, characterized by comprising the anti-reverse circuit as claimed in any one of the claims.
CN 201010225022 2010-07-02 2010-07-02 Reverse-connection preventing circuit, reverse-connection preventing processing method and communication equipment CN101872971A (en)

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CN102136724A (en) * 2011-01-26 2011-07-27 华为技术有限公司 Method and device for protecting reverse connection prevention and slow start of direct-current power supply input
CN102142681A (en) * 2010-12-23 2011-08-03 聚信科技有限公司 Method and device for preventing input reverse-connection damage
CN102638034A (en) * 2012-04-01 2012-08-15 杭州科岛微电子有限公司 Reverse connection protection high pressure circuit of power supply
CN102684142A (en) * 2011-02-04 2012-09-19 飞兆半导体公司 Integrated overdrive and overvoltage protection device
CN102931637A (en) * 2011-08-10 2013-02-13 联创汽车电子有限公司 Power source protection circuit of vehicle-mounted electronic component
CN103036226A (en) * 2012-12-06 2013-04-10 南京莱斯信息技术股份有限公司 Low-cost and low-power-consumption power supply reverse connection protection circuit and protection method of the same
CN103050964A (en) * 2011-10-12 2013-04-17 昆山广兴电子有限公司 Reverse voltage protection device
CN103337984A (en) * 2013-06-28 2013-10-02 深圳市汇川控制技术有限公司 Reusable mini-type PLC power supply circuit
CN103441486A (en) * 2013-08-14 2013-12-11 上海华兴数字科技有限公司 Reverse-connection-prevention protective circuit of high current power supply
CN103647339A (en) * 2013-12-20 2014-03-19 广东威创视讯科技股份有限公司 Power supply device with multiple power sources in parallel connection
CN104143906A (en) * 2014-07-28 2014-11-12 武汉中元通信股份有限公司 Medium-power power source module for mobile wireless communication device
CN104393558A (en) * 2014-11-24 2015-03-04 程信羲 Thick film low power consumption counter-attack under-voltage protection module
CN105048403A (en) * 2015-05-25 2015-11-11 长城电器集团有限公司 Overvoltage protection circuit for AC voltage stabilizer controller
CN105262165A (en) * 2015-10-13 2016-01-20 深圳茂硕电子科技有限公司 Solar charging and discharging controller
CN105262160A (en) * 2015-09-29 2016-01-20 安徽华米信息科技有限公司 Anti-reverse-connection circuit, anti-reverse-connection processing method, device and intelligent wearable equipment
CN105515352A (en) * 2015-12-31 2016-04-20 邦彦技术股份有限公司 Dual-input power supply system used for MTCA machine frame
CN106208247A (en) * 2016-08-30 2016-12-07 合肥博雷电气有限公司 A kind of car-mounted terminal power supply reverse connection protection is held concurrently Anti-surging device
CN106655385A (en) * 2016-12-28 2017-05-10 深圳市科陆电子科技股份有限公司 Anti-reverse connection system and method applied to battery management unit equalization channels
US9735147B2 (en) 2014-09-15 2017-08-15 Fairchild Semiconductor Corporation Fast and stable ultra low drop-out (LDO) voltage clamp device
CN108169663A (en) * 2017-12-28 2018-06-15 湖南国科微电子股份有限公司 A kind of pcb board with fool proof debugging interface
CN108390365A (en) * 2018-02-27 2018-08-10 武汉煜炜光学科技有限公司 A kind of power supply unidirectional current control circuit
CN108879648A (en) * 2017-05-15 2018-11-23 华为技术有限公司 A kind of power protecting circuit

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Cited By (27)

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CN102142681A (en) * 2010-12-23 2011-08-03 聚信科技有限公司 Method and device for preventing input reverse-connection damage
WO2012083738A1 (en) * 2010-12-23 2012-06-28 华为技术有限公司 Method and device for preventing input reverse-connection damage
CN102136724A (en) * 2011-01-26 2011-07-27 华为技术有限公司 Method and device for protecting reverse connection prevention and slow start of direct-current power supply input
CN102136724B (en) 2011-01-26 2013-10-09 华为技术有限公司 Method and device for protecting reverse connection prevention and slow start of direct-current power supply input
CN102684142A (en) * 2011-02-04 2012-09-19 飞兆半导体公司 Integrated overdrive and overvoltage protection device
CN102684142B (en) * 2011-02-04 2017-03-01 飞兆半导体公司 Integrated overdrive and overvoltage protection device
CN102931637A (en) * 2011-08-10 2013-02-13 联创汽车电子有限公司 Power source protection circuit of vehicle-mounted electronic component
CN103050964A (en) * 2011-10-12 2013-04-17 昆山广兴电子有限公司 Reverse voltage protection device
CN102638034A (en) * 2012-04-01 2012-08-15 杭州科岛微电子有限公司 Reverse connection protection high pressure circuit of power supply
CN103036226A (en) * 2012-12-06 2013-04-10 南京莱斯信息技术股份有限公司 Low-cost and low-power-consumption power supply reverse connection protection circuit and protection method of the same
CN103337984A (en) * 2013-06-28 2013-10-02 深圳市汇川控制技术有限公司 Reusable mini-type PLC power supply circuit
CN103441486A (en) * 2013-08-14 2013-12-11 上海华兴数字科技有限公司 Reverse-connection-prevention protective circuit of high current power supply
CN103647339A (en) * 2013-12-20 2014-03-19 广东威创视讯科技股份有限公司 Power supply device with multiple power sources in parallel connection
CN103647339B (en) * 2013-12-20 2015-10-28 广东威创视讯科技股份有限公司 Many power sources in parallel electric supply installation
CN104143906A (en) * 2014-07-28 2014-11-12 武汉中元通信股份有限公司 Medium-power power source module for mobile wireless communication device
US9735147B2 (en) 2014-09-15 2017-08-15 Fairchild Semiconductor Corporation Fast and stable ultra low drop-out (LDO) voltage clamp device
CN104393558A (en) * 2014-11-24 2015-03-04 程信羲 Thick film low power consumption counter-attack under-voltage protection module
CN105048403B (en) * 2015-05-25 2019-01-01 浙江凯发电气有限公司 A kind of AC voltage regulator controller overvoltage crowbar
CN105048403A (en) * 2015-05-25 2015-11-11 长城电器集团有限公司 Overvoltage protection circuit for AC voltage stabilizer controller
CN105262160A (en) * 2015-09-29 2016-01-20 安徽华米信息科技有限公司 Anti-reverse-connection circuit, anti-reverse-connection processing method, device and intelligent wearable equipment
CN105262165A (en) * 2015-10-13 2016-01-20 深圳茂硕电子科技有限公司 Solar charging and discharging controller
CN105515352A (en) * 2015-12-31 2016-04-20 邦彦技术股份有限公司 Dual-input power supply system used for MTCA machine frame
CN106208247A (en) * 2016-08-30 2016-12-07 合肥博雷电气有限公司 A kind of car-mounted terminal power supply reverse connection protection is held concurrently Anti-surging device
CN106655385A (en) * 2016-12-28 2017-05-10 深圳市科陆电子科技股份有限公司 Anti-reverse connection system and method applied to battery management unit equalization channels
CN108879648A (en) * 2017-05-15 2018-11-23 华为技术有限公司 A kind of power protecting circuit
CN108169663A (en) * 2017-12-28 2018-06-15 湖南国科微电子股份有限公司 A kind of pcb board with fool proof debugging interface
CN108390365A (en) * 2018-02-27 2018-08-10 武汉煜炜光学科技有限公司 A kind of power supply unidirectional current control circuit

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