CN101872971A - Reverse-connection preventing circuit, reverse-connection preventing processing method and communication equipment - Google Patents
Reverse-connection preventing circuit, reverse-connection preventing processing method and communication equipment Download PDFInfo
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Abstract
The invention provides a reverse-connection preventing circuit, a reverse-connection preventing processing method and communication equipment. The circuit comprises a voltage bias resistor connected between the anode and the cathode of the power supply, a bidirectional voltage-lamping circuit and at least one field-effect tube, wherein the voltage bias resistor is connected with the grid electrode of the field-effect tube and is used for conducting and biasing the field-effect tube; the bidirectional voltage-lamping circuit is connected in parallel at two ends of the grid electrode and the source electrode of the field-effect tube and is used for taking a grid electrode and source electrode voltage clamp of the field-effect tube as a first protective voltage when inputting overvoltage in the forward direction; and the first protective voltage is the normal work voltage of the field-effect tube. The invention also provides the reverse-connection preventing processing method and the communication equipment. The invention achieves the input overvoltage protection function of the direct current input reverse-connection preventing circuit and improves the reliability of the circuit.
Description
Technical field
The present invention relates to communication technical field, relate in particular to a kind of reverse-connection preventing circuit, reverse-connection preventing processing method and communication apparatus.
Background technology
In the electronic system of the use external direct current power supply of the communications field, the polarity misconnection of external direct current power supply or reversal connection tend to equipment is caused expendable infringement, even burn relevant device, therefore, the power supply input by the communication equipment of DC power supply need be designed to reverse-connection preventing circuit usually.
Be illustrated in figure 1 as the connection diagram of a kind of reverse-connection preventing circuit of the prior art, reverse-connection preventing circuit of the prior art is diode D1 of series connection on power supply circuits usually, utilizes the unidirectional conducting of diode, the characteristic of oppositely ending to realize the anti-reverse function of input.If oppositely ending appears in the error-polarity connection of power supply VIN+ and VIN-, diode D1, make power supply circuits be in short-circuit condition, then can avoid the damage of the motherboard circuit that power supply input reversal connection causes.But because there is voltage drop in diode when forward conduction, and this voltage drop relative fixed, when it was applied in the high-power circuit application, the electric current of the diode of flowing through was big more, and the consumed power on the diode is also big more, causes the temperature rise of diode high more.If the too high meeting of diode temperature rise obviously reduces the reliability of diode, if diode not being provided with special radiator carries out radiating treatment, then diode burns because of junction temperature is too high easily.Be illustrated in figure 2 as the connection diagram of another kind of reverse-connection preventing circuit of the prior art, it is the improvement to reverse-connection preventing circuit among Fig. 1, and the diode that is connected in the current supply circuit is replaced by N ditch channel metal-oxide semiconductor (N-Channel MetalOxide Semiconductor; Hereinafter to be referred as: NMOS) field effect transistor Q1, wherein, the S pin of Q1 and D pin are serially connected with VIN-and load R
LBetween, the G pin is connected to the S pin by resistance R 2, is connected to VIN+ by resistance R 1, utilizes the switching characteristic of metal-oxide-semiconductor to control the conducting of power supply circuits and end, thereby prevents that the load that error-polarity connection of power supply causes from damaging.Because the conducting internal resistance of metal-oxide-semiconductor is very little, basic is the milliohm level, even the pressure drop of metal-oxide-semiconductor is also very little in the occasion of big electric current, and its conduction loss can be controlled at the very little order of magnitude, then can thoroughly solve the pressure drop and the excessive problem of power consumption that adopt diode to cause as circuit for preventing reverse connection of power supply among Fig. 1.
Yet, in above-mentioned Fig. 2, the cut-in voltage of Q1 is 4.5V-5V, this moment, the conducting internal resistance of Q1 was also bigger, in order to reach littler conducting internal resistance, the voltage between the GS pin of needs increase Q1 is when the voltage between the GS pin reaches 10V-15V, Q1 is under the best conducting state, the conducting internal resistance minimum of Q1.But, when input direct voltage continues to raise, then can cause the voltage between the GS pin also to increase because direct-current input power supplying voltage is not burning voltage.When the voltage between the GS pin reaches 20V when above, the GS pin of Q1 causes whole reverse-connection preventing circuit to lose efficacy because overvoltage causes Q1 to burn easily.
Summary of the invention
The invention provides a kind of reverse-connection preventing circuit, reverse-connection preventing processing method and communication apparatus; the problem that causes the metal-oxide-semiconductor puncture in order to the input voltage overvoltage that solves reverse-connection preventing circuit existence in the prior art; realize the input over-voltage protecting function of direct current input reverse-connection preventing circuit; expand the applied voltage scope of circuit, improve the reliability of circuit.
The invention provides a kind of reverse-connection preventing circuit; comprise the voltage bias resistance that is connected between positive source and the power cathode; bi-directional voltage clamp circuit and at least one field effect transistor; wherein; described voltage bias resistance links to each other with the grid of described field effect transistor; be used for described field effect transistor is carried out turn-on bias; described bi-directional voltage clamp circuit is connected in the two ends of the gate-to-source of described field effect transistor in parallel; described bi-directional voltage clamp circuit is used for when forward input overvoltage; with the grid-source voltage clamp of described field effect transistor is the first protection voltage, and the described first protection voltage is the normal working voltage of described field effect transistor.
The invention provides a kind of reverse-connection preventing processing method, comprising:
When forward input overvoltage; the bi-directional voltage clamp circuit at the two ends of the gate-to-source by being connected in field effect transistor in parallel is the first protection voltage with the grid-source voltage clamp of described field effect transistor, and the described first protection voltage is the normal working voltage of described field effect transistor.
The invention provides a kind of communication apparatus, comprise above-mentioned reverse-connection preventing circuit.
Reverse-connection preventing circuit of the present invention, reverse-connection preventing processing method and communication apparatus; by at the two ends of the gate-to-source of field effect transistor bi-directional voltage clamp circuit in parallel; when forward input overvoltage; be clamped within the normal working voltage by the grid-source voltage of bi-directional voltage clamp circuit field effect transistor; solved the problem that the input voltage overvoltage that reverse-connection preventing circuit exists in the prior art causes metal-oxide-semiconductor to puncture; realized the input over-voltage protecting function of direct current input reverse-connection preventing circuit; expand the applied voltage scope of circuit, improved the reliability of circuit.
Description of drawings
In order to be illustrated more clearly in the embodiment of the invention or technical scheme of the prior art, to do one to the accompanying drawing of required use in embodiment or the description of the Prior Art below introduces simply, apparently, accompanying drawing in describing below is some embodiments of the present invention, for those of ordinary skills, under the prerequisite of not paying creative work, can also obtain other accompanying drawing according to these accompanying drawings.
Fig. 1 is the connection diagram of a kind of reverse-connection preventing circuit of the prior art;
Fig. 2 is the connection diagram of another kind of reverse-connection preventing circuit of the prior art;
Fig. 3 is the structural representation of reverse-connection preventing circuit embodiment one of the present invention;
Fig. 4 is the structural representation of reverse-connection preventing circuit embodiment two of the present invention;
Fig. 5 is the structural representation of reverse-connection preventing circuit embodiment three of the present invention;
Fig. 6 is the structural representation of reverse-connection preventing circuit embodiment four of the present invention;
Fig. 7 is the structural representation of reverse-connection preventing circuit embodiment five of the present invention;
Fig. 8 is the structural representation of reverse-connection preventing circuit embodiment six of the present invention;
Fig. 9 is the flow chart of reverse-connection preventing processing method embodiment of the present invention.
Embodiment
For the purpose, technical scheme and the advantage that make the embodiment of the invention clearer, below in conjunction with the accompanying drawing in the embodiment of the invention, technical scheme in the embodiment of the invention is clearly and completely described, obviously, described embodiment is the present invention's part embodiment, rather than whole embodiment.Based on the embodiment among the present invention, those of ordinary skills belong to the scope of protection of the invention not making the every other embodiment that is obtained under the creative work prerequisite.
Fig. 3 is the structural representation of reverse-connection preventing circuit embodiment one of the present invention, as shown in Figure 3, present embodiment provides a kind of reverse-connection preventing circuit, this reverse-connection preventing circuit can comprise bi-directional voltage clamp circuit 1, voltage bias resistance 6 and at least one field effect transistor 2, among the figure only to comprise that a field effect transistor 2 is that example describes.Bi-directional voltage clamp circuit 1 in the present embodiment in the reverse-connection preventing circuit and field effect transistor 2 all are connected between positive source 3 and the power cathode 4.Wherein, voltage bias resistance 6 links to each other with the grid G of field effect transistor 2; be used for field effect transistor 2 is carried out turn-on bias; bi-directional voltage clamp circuit 1 is connected in the two ends of the gate-to-source (being G-S) of field effect transistor 2 in parallel; bi-directional voltage clamp circuit 1 is used for when supply voltage forward input overvoltage, is the first protection voltage with the grid-source voltage clamp of field effect transistor 2.Be about to V
GSBe clamped at the first protection voltage,, be applied to the V on the field effect transistor 2 even supply voltage continues to raise
GSAll remain the first protection voltage, can prevent that then field effect transistor 2 from can not cause its GS pin over-voltage breakdown because of importing overvoltage, and then prevent that field effect transistor 2 from being burnt, guarantee the stability of reverse-connection preventing circuit.In the present embodiment, the first protection voltage is the normal working voltage of field effect transistor 2, promptly the voltage of the GS pin of field effect transistor 2 can be maintained within the scope of its normal working voltage, guarantees that it can not burnt by over-voltage breakdown.
Compare with reverse-connection preventing circuit of the prior art shown in Figure 1, present embodiment adopts field effect transistor as switching device, realize the switch control of reverse-connection preventing circuit, and utilize the unidirectional conducting of diode among Fig. 1 and the characteristic of oppositely ending realizes importing anti-reverse function.Wherein, when the difference of the input pressure drop of diode and output pressure drop greater than 0.7V, be that the voltage difference of the positive pole of diode and negative pole is during greater than 0.7V, diode current flow, electric current flows to negative pole from positive pole, because there is parasitic junction capacitance in diode, so need charge to junction capacitance during conducting, after electric capacity was full of, diode was realized conducting; When the difference of input pressure drop and output pressure drop during less than 0.7V, diode ends, and electric current can't circulate, diode by the time parasitic junction capacitance need discharge, put the realization of electricity back and ended.Because the technology of diode causes its parasitic junction capacitance bigger, so the conducting of diode and by needing the long period, be about the microsecond rank usually.And the conducting internal resistance of field effect transistor is smaller, substantially in the milliohm level, immediately the pressure drop of field effect transistor is also very little in big current applications, then can overcome among Fig. 1 in the prior art pressure drop and the excessive problem of power consumption in the diode power source reverse-connection preventing circuit, makes the reliability of circuit also improve.
Compare with reverse-connection preventing circuit of the prior art shown in Figure 2, present embodiment is by bi-directional voltage clamp circuit in parallel at the GS of field effect transistor pin two ends, and realization is carried out accurately clamping protection to the voltage at the GS pin two ends of field effect transistor.When input supply voltage voltage raises, the GS pin voltage of field effect transistor can not increase, and be clamped at by the bi-directional voltage clamp circuit within the scope of normal working voltage of field effect transistor, make field effect transistor can not burn, thereby prevent inefficacy because of its whole reverse-connection preventing circuit that causes etc. because of GS pin over-voltage breakdown.
Present embodiment provides a kind of reverse-connection preventing circuit; by at the two ends of the gate-to-source of field effect transistor bi-directional voltage clamp circuit in parallel; when forward input overvoltage; be clamped within the normal working voltage by the grid-source voltage of bi-directional voltage clamp circuit field effect transistor; solved the problem that the input voltage overvoltage that reverse-connection preventing circuit exists in the prior art causes metal-oxide-semiconductor to puncture; realized the input over-voltage protecting function of direct current input reverse-connection preventing circuit; expand the applied voltage scope of circuit, improved the reliability of circuit.
Further; continue with reference to above-mentioned shown in Figure 3; bi-directional voltage clamp circuit in the reverse-connection preventing circuit that present embodiment provides can also be used for when oppositely importing overvoltage; with the grid-source voltage clamp of field effect transistor 2 is the second protection voltage, and this second protection voltage also is the normal working voltage of field effect transistor 2.Even the anti-phase input of supply voltage continues to raise; the VGS that is applied on the field effect transistor 2 all remains the second protection voltage; can prevent that then field effect transistor 2 from can not cause its GS pin over-voltage breakdown because of importing overvoltage, and then prevent that field effect transistor 2 from being burnt, guarantee the stability of reverse-connection preventing circuit.Compare with reverse-connection preventing circuit of the prior art shown in Figure 2, present embodiment is the second protection voltage by the bi-directional voltage clamp circuit with the grid-source voltage of field effect transistor 2 clamp when the reverse input overvoltage.In prior art shown in Figure 2, under direct-current input power supplying voltage ratio condition with higher, in order to reduce the loss of divider resistance, the resistance value of R1 and R2 will be bigger, because the existence of Q1 parasitic diode in parallel, the reverse leakage current of Q1 just can not be ignored, if DC power supply error-polarity connection, reverse voltage just is applied on R2 and the R1 by the leakage current of Q1, if the voltage on the R2 were higher than-more than the 20V, also be very easy to cause Q1 owing to GS pin over-voltage breakdown causes Q1 to burn, cause whole reverse-connection preventing circuit to lose efficacy.And in the present embodiment; because the bi-directional voltage clamp circuit has voltage clamp function; under the situation of input reversal connection; the bi-directional voltage clamp circuit is realized forward conduction; its pressure drop is very little; and this pressure drop can not raise because of the rising of input reverse voltage, has then realized the anti-phase over-voltage protecting function of reverse-connection preventing circuit, has solved the defective that the Q1 that causes because of input reversal connection overvoltage in the prior art burns.
Further, continue with reference to above-mentioned shown in Figure 3, the reverse-connection preventing circuit of present embodiment can also comprise delay capacitor 5, and delay capacitor 5 is connected in parallel with bi-directional voltage clamp circuit 1, be used for when input voltage powers on, the input voltage that is applied on the field effect transistor 2 is delayed the startup processing.Because delay capacitor 5 is set in circuit, when DC power supply just inserts, delay capacitor 5 constitutes regularly charging circuit of a RC with voltage bias resistance 6, the voltage of delay capacitor 5 slowly raises, have only when the voltage at delay capacitor 5 two ends is elevated to the cut-in voltage of field effect transistor 2, field effect transistor 2 just enters conducting state.Along with the progressively rising of the voltage at the GS pin two ends of field effect transistor 2, the conducting internal resistance of field effect transistor 2 also constantly reduces then, and when bi-directional voltage clamp circuit 1 breakdown clamp, field effect transistor 2 just enters the state of saturation conduction fully.And in prior art shown in Figure 2, because when the high power DC current supply circuit is connected load in DC power supply, because unavoidably there is the influence of contact shake and load filter capacitor in terminal, often produce very big current spike and impulse current at the direct current power circuit, then make the power device Q1 damage on the electric loop among Fig. 2, system's cisco unity malfunction.This shows that the reverse-connection preventing circuit that present embodiment provides can overcome above-mentioned defective of the prior art by setting up delay capacitor, realize the soft start function of reverse-connection preventing circuit, improve the stability of circuit.
Fig. 4 is the structural representation of reverse-connection preventing circuit embodiment two of the present invention, and as shown in Figure 4, present embodiment provides a kind of concrete reverse-connection preventing circuit, and the field effect transistor in the present embodiment is specially the NMOS pipe, and comprises a NMOS pipe.In the present embodiment, among three pin G, the S and D of NMOS pipe Q1, G is a grid, and S is a source electrode, and D is drain electrode.Wherein between the GS pin not during making alive, the resistance R DSon infinity between D pin and the S pin is equivalent to power path is disconnected, and GS pin voltage is greater than opening electric V
ThThe time, resistance R DSon reduces to the resistance value of several milliohms fast between DS, is equivalent to switch closure.Wherein, cut-in voltage V
ThBe the intrinsic parameter of metal-oxide-semiconductor device.In addition, there is parasitic body diode in the NMOS pipe, and when NMOS managed not conducting, electric current can pass through from body diode.In the present embodiment, the bi-directional voltage clamp circuit can include but not limited to voltage stabilizing didoe, voltage suppressor and voltage comparator circuit, and present embodiment is that voltage stabilizing didoe is that example describes with the bi-directional voltage clamp circuit.In the present embodiment, the grid G of NMOS pipe Q1 links to each other with the negative pole of voltage stabilizing didoe D1, and links to each other with positive source VIN+ by voltage bias resistance R 1; The drain D of NMOS pipe Q1 links to each other with power cathode VIN-; The source S of NMOS pipe Q1 links to each other with the positive pole of voltage stabilizing didoe D1, and by load resistance R
LVIN+ links to each other with positive source; The positive pole of the body diode of NMOS pipe Q1 links to each other with the source S of Q1, and its negative pole links to each other with the drain D of Q1.
In the present embodiment, be that 24V is that example describes with the input voltage, can operate as normal for making Q1, D1 chooses the voltage-stabiliser tube that clamping voltage is 12V, and R1 is as the current-limiting resistance of D1 and the voltage bias resistance of Q1.When DC power supply polarity correctly connected, promptly VIN+ connect the positive pole of DC power supply, and VIN-connects the negative pole of DC power supply, and when power supply electrifying, input supply voltage begins to raise from 0V, and this moment is not because the voltage at the GS pin two ends of Q1 reaches the cut-in voltage V of Q1
Th, then Q1 is in off-state.But owing to have parasitic body diode among the Q1, and according to the connected mode among Fig. 4, dc power anode VIN+ was through load resistance R when input supply voltage powered on
LForm current circuit with the body diode of Q1, get back to dc power cathode VIN-.And at the initial stage that powers on of DC power supply, because input supply voltage is lower, load resistance can't be worked, and load current is less, even electric current by the body diode of Q1, can not cause pressure drop loss too big on the Q1 yet.
Along with the continuation rising of input supply voltage, input supply voltage carries out current limliting by R1, is applied between the GS pin of D1, C1 and Q1.Because the existence of capacitor C 1, the voltage at capacitor C 1 two ends are slowly to raise, this moment is because the voltage at C1 two ends also is not enough to be elevated to the puncture voltage of D1, so D1 presents open-circuit condition.Through the regular hour, when the voltage of C1 continued to be elevated to the cut-in voltage of Q1, Q1 entered conducting state.After Q1 enters conducting state, internal resistance between its D pin and the S pin reduces rapidly from infinity, and the pressure drop between the DS pin reduces rapidly, when the pressure drop between the DS pin is reduced to less than 1V, the parasitic body diode of Q1 is owing to discontented afc voltage biasing ends, the principal current of electric power loop all should flow through between the DS pin of Q1, no longer conducting and flow through electric current of parasitic body diode.
After Q1 began conducting, because the conducting internal resistance does not also reach minimum, this moment, the filter capacitor of load circuit began charging, must cause current supply circuit bigger impulse current to occur, and because Q1 internal resistance restriction has suppressed the unexpected increase of impulse current.Along with the voltage at the GS pin two ends of Q1 rises gradually, the conducting internal resistance of Q1 constantly reduces, and when voltage rose to the puncture voltage of D1, D1 entered conducting state, because the voltage clamp effect of D1, no longer rise near the voltage at the GS pin two ends of Q1 is stabilized in 12V.This moment, Q1 finished slow starting state, entered normal saturation conduction state.
If this moment, fluctuation appearred in input direct voltage, input supply voltage continues to raise, because the effect of the clamping voltage of voltage-stabiliser tube, the voltage of guaranteeing the GS pin two ends of Q1 no longer raises and raises along with supply voltage, has then avoided input voltage overvoltage this moment to cause the electric voltage over press at the GS pin two ends of Q1 to puncture and burns Q1.When direct-current input power supplying voltage reached 24V, D1 punctured, and the voltage at the GS pin two ends of Q1 is clamped at about 12V, and Q1 enters the saturation conduction state.When input supply voltage fluctuates 48V, because the forward voltage stabilizing clamping action of D1 has guaranteed that the voltage at the GS pin two ends of Q1 is clamped at about 12V, the work that Q1 still can be reliable and stable.
In addition, in the present embodiment, because the existence of C1, when direct-current input power supplying just inserted, R1 and C1 had constituted regularly charging circuit of a RC, and the voltage of C1 slowly raises.Have only when the voltage of C1 is elevated to the cut-in voltage of Q1, Q1 just enters conducting state.Voltage along with the GS pin two ends of Q1 progressively raises then, and the conducting internal resistance of Q1 constantly reduces.When the breakdown clamp of D1, Q1 enters the state of saturation conduction fully, has realized the soft start function of reverse-connection preventing circuit.
Further, in the present embodiment, when incorrect link appears in the polarity of direct-current input power supplying, it is the negative pole that VIN+ connects DC power supply, VIN-connects the positive pole of DC power supply, input supply voltage began to raise from 0V when input supply voltage powered on, and this moment is not because the voltage at the GS pin two ends of Q1 reaches cut-in voltage, so Q1 is in off-state.But the parasitic body diode of Q1 is just in time ended according to the connected mode of Fig. 4 at this moment, and direct current is through overload R in the time of can preventing to power on
LForm current circuit with the body diode of Q1, get back to VIN+.Yet in side circuit, because there is the leakage current of tens UA levels in the parasitic body diode of Q1, in fact VIN-has small leakage current and flows to positive pole from the negative pole of the parasitic body diode of Q1, returns VIN+ through D1 and R1.Under this kind state, the D1 forward conduction presents the diode current flow characteristic; the pressure drop of D1 is greatly about-1.0V; and because the reverse-conducting clamp function of voltage stabilizing didoe, the pressure drop of D1 can not raise because of the rising of input reverse voltage, and then has realized the reverse over-voltage protecting function of reverse-connection preventing circuit.
Present embodiment provides a kind of reverse-connection preventing circuit, by at the two ends of the GS of field effect transistor bi-directional voltage clamp circuit in parallel, when forward input overvoltage, by the bi-directional voltage clamp circuit with the voltage clamp at the GS two ends of field effect transistor within normal working voltage, when reverse input overvoltage, by the bi-directional voltage clamp circuit also with the voltage clamp at the GS two ends of field effect transistor within normal working voltage; Present embodiment has solved the input voltage overvoltage of reverse-connection preventing circuit existence in the prior art and the problem that reverse input voltage overvoltage causes metal-oxide-semiconductor to puncture; realize the input over-voltage protecting function of direct current input reverse-connection preventing circuit and oppositely imported over-voltage protecting function; and possesses the circuit soft start function; expand the applied voltage scope of circuit, improved the reliability of circuit.
Fig. 5 is the structural representation of reverse-connection preventing circuit embodiment three of the present invention, and as shown in Figure 5, present embodiment provides a kind of concrete reverse-connection preventing circuit, and the field effect transistor in the present embodiment is specially the NMOS pipe, and comprises a plurality of NMOS pipe Q1, Q2... that are connected in parallel.In the present embodiment, the grid G of each NMOS pipe (as Q1 among Fig. 5 or Q2) links to each other with the negative pole of voltage stabilizing didoe D1, and links to each other with positive source VIN+ by voltage bias resistance R 1; The drain D of each NMOS pipe links to each other with power cathode VIN-; The source S of each NMOS pipe Q1 links to each other with the positive pole of voltage stabilizing didoe D1, and by load resistance R
LVIN+ links to each other with positive source; The positive pole of the body diode of each NMOS pipe Q1 links to each other with the source S of Q1, and its negative pole links to each other with the drain D of Q1.Present embodiment is connected in parallel by adopting a plurality of NMOS pipes; increased the overcurrent capability of power tube; because forward voltage stabilizing clamp function and the reverse-conducting clamp function of voltage stabilizing didoe D1; can realize input overvoltage protection and back-pressure clamping protection, and a plurality of NMOS pipe leakage current that forms in parallel also can not cause the overvoltage Problem of Failure of reverse-connection preventing circuit to each NMOS.
Fig. 6 is the structural representation of reverse-connection preventing circuit embodiment four of the present invention, and as shown in Figure 6, present embodiment provides a kind of concrete reverse-connection preventing circuit, and the field effect transistor in the present embodiment is specially PMOS pipe Q1, and the bi-directional voltage clamp circuit is specially voltage stabilizing didoe D1.Present embodiment is that example describes to comprise a PMOS pipe, and the situation that comprises the PMOS pipe of a plurality of parallel connections can be similar with above-mentioned Fig. 5, repeats no more herein.Wherein, the grid G of PMOS pipe Q1 links to each other with the positive pole of D1, and links to each other with power cathode VIN-by voltage bias resistance R 1; The source S of PMOS pipe Q1 links to each other with the negative pole of D1, and links to each other with positive source VIN+; The drain D of PMOS pipe Q1 is by load R
LVIN-links to each other with power cathode; The positive pole of the body diode of PMOS pipe Q1 links to each other with the source S of Q1, its negative pole Q1 with drain D link to each other.Present embodiment replaces with the PMOS pipe with the field effect transistor in the circuit by the NMOS pipe, when forward input overvoltage, equally can by D1 with the voltage clamp at the GS two ends of Q1 within normal working voltage, when reverse input overvoltage, by D1 also with the voltage clamp at the GS two ends of Q1 within normal working voltage; Present embodiment has solved the input voltage overvoltage of reverse-connection preventing circuit existence in the prior art and the problem that reverse input voltage overvoltage causes metal-oxide-semiconductor to puncture; realize the input over-voltage protecting function of direct current input reverse-connection preventing circuit and oppositely imported over-voltage protecting function; and possesses the circuit soft start function; expand the applied voltage scope of circuit, improved the reliability of circuit.
It is pointed out that the PMOS pipe in the present embodiment also can be as above-mentioned a plurality of parallel connections that are shown in Figure 5, concrete connected mode is similar to the above embodiments, repeats no more herein.
Fig. 7 is the structural representation of reverse-connection preventing circuit embodiment five of the present invention, and as shown in Figure 7, present embodiment provides a kind of concrete reverse-connection preventing circuit, and the field effect transistor in the present embodiment is specially the NMOS pipe.In the present embodiment, the bi-directional voltage clamp circuit can comprise interconnective reference voltage source D1, the first divider resistance R2 and the second divider resistance R3, can operate as normal for making Q1, and present embodiment is that example describes to adopt the TL431 reference voltage source.In the present embodiment, be that 24V is that example describes with the input voltage, R2, R3 are as the resistor voltage divider network of D1 reference voltage source, and R1 is as the load resistance of D1 and the biasing resistor of NMOS pipe Q1.Wherein, the first divider resistance R2 of series connection and the second divider resistance R3 and reference voltage source D1 are connected in parallel mutually, and the benchmark pin R of reference voltage source D1 is connected between the first divider resistance R2 and the second divider resistance R3.The anodal A of reference voltage source D1 is the positive pole of bi-directional voltage clamp circuit, and the negative pole K of reference voltage source D1 is the negative pole of bi-directional voltage clamp circuit.
In the present embodiment, among three pin G, the S and D of NMOS pipe, G is a grid, and S is a source electrode, and D is drain electrode.Wherein between the GS pin not during making alive, the resistance R DSon infinity between D pin and the S pin is equivalent to power path is disconnected, and GS pin voltage is greater than opening electric V
ThThe time, resistance R DSon reduces to the resistance value of several milliohms fast between DS, is equivalent to switch closure.Wherein, cut-in voltage V
ThBe the intrinsic parameter of metal-oxide-semiconductor device.In addition, there is parasitic body diode in the NMOS pipe, and when NMOS managed not conducting, electric current can pass through from body diode.In the present embodiment, the grid G of NMOS pipe Q1 is connected with the negative pole K of reference voltage source D1 and the end of divider resistance R2; The drain D of NMOS pipe Q1 links to each other with power cathode VIN-; The source S of NMOS pipe Q1 links to each other with the anodal A of reference voltage source D1 and the end of divider resistance R3, and by load resistance R
LVIN+ links to each other with positive source.The positive pole of the body diode of NMOS pipe Q1 links to each other with the source S of Q1, and its negative pole links to each other with the drain D of Q1.The benchmark pin R of reference voltage source D1 links to each other with the end of divider resistance R2 and R3, and the other end of divider resistance R2 is connected to the grid G of NMOS pipe Q1; The divider resistance R3 other end is connected to the source S of NMOS pipe Q1.Delay capacitor C1 is connected respectively to the grid G of NMOS pipe Q1 and the source S of NMOS pipe Q1.
Wherein, when DC power supply polarity correctly connected, promptly VIN+ connect the positive pole of DC power supply, and VIN-connects the negative pole of DC power supply, and when power supply electrifying, input supply voltage begins to raise from 0V, and this moment is not because the voltage at the GS pin two ends of Q1 reaches the cut-in voltage V of Q1
Th, then Q1 is in off-state.But owing to have parasitic body diode among the Q1, and according to the connected mode among Fig. 7, dc power anode VIN+ was through load resistance R when input supply voltage powered on
LForm current circuit with the body diode of Q1, get back to dc power cathode VIN-.And at the initial stage that powers on of DC power supply, because input supply voltage is lower, load resistance can't be worked, and load current is less, even electric current by the body diode of Q1, can not cause pressure drop loss too big on the Q1 yet.
Along with the continuation rising of input supply voltage, input supply voltage carries out current limliting by R1, is applied to D1, between the GS pin of R2 and R3 resistor voltage divider network, C1 and Q1.Because the existence of capacitor C 1, the voltage at capacitor C 1 two ends is slowly to raise, this moment is because the voltage at C1 two ends is applied to the puncture voltage that the voltage of resistor voltage divider network R2 and R3 also is not enough to be elevated to the benchmark pin R of D1 (D1 reference voltage=2.5V), so D1 presents open-circuit condition.Through the regular hour, when the voltage of C1 continued to be elevated to the cut-in voltage of Q1, Q1 entered conducting state.After Q1 enters conducting state, internal resistance between its D pin and the S pin reduces rapidly from infinity, and the pressure drop between the DS pin reduces rapidly, when the pressure drop between the DS pin is reduced to less than 1V, the parasitic body diode of Q1 because the biasing of discontented afc voltage and by, the principal current of electric power loop all should flow through between the DS pin of Q1, no longer conducting and flow through electric current of parasitic body diode.
After Q1 began conducting, because the underfill of delay capacitor C1 electric charge, it is minimum that the conducting internal resistance of Q1 does not also reach, this moment, the filter capacitor of load circuit began charging, and, realized slow startup function of supplying power because Q1 internal resistance restriction has suppressed the unexpected increase of impulse current.Along with the voltage at the GS pin two ends of Q1 rises gradually, the conducting internal resistance of Q1 constantly reduces, and the voltage on resistance pressure-dividing network R2 and the R3 also constantly raises at this moment, when the voltage on divider resistance networking R2 and the R3 rises to 12V, through R2, the dividing potential drop of R3, when the benchmark pin R of D1 reference voltage source had reached 2.5V voltage, D1 entered conducting state by ending, because the conducting of D1, the be equivalent to short circuit grid G of NMOS pipe Q1 and the voltage between the source S no longer rises the GS voltage of Q1, then descends.When the GS of Q1 voltage descended, the voltage of divider resistance R2 and R3 also descended, and when the R of D1 pin dividing potential drop drops to 2.5V when following, D1 transfers cut-off state to by conducting, and grid G and the voltage between the source S by having caused NMOS pipe Q1 again of D1 go up.Go round and begin again like this, D1 circulation conducting and ending, the GS voltage positive clamping that has guaranteed NMOS pipe Q1 guarantees that Q1 enters saturation conduction, conducting internal resistance minimum about 12V.This moment, Q1 finished slow starting state, entered normal saturation conduction state.
If this moment, fluctuation appearred in input direct voltage, input supply voltage continues to raise, the voltage of divider resistance R2 and R3 also raises, be applied to the voltage of D1 benchmark R pin in case surpass 2.5V, will cause the D1 conducting, finally make the voltage at the GS pin two ends of Q1 no longer raise and raise, avoided the input voltage overvoltage to cause the electric voltage over press at the GS pin two ends of Q1 to puncture and burn Q1 along with VIN voltage.When direct-current input power supplying voltage reaches 24V, D1, R2, the acting in conjunction of the bi-directional voltage clamp circuit that R3 forms is clamped at about 12V the voltage at the GS pin two ends of Q1, and Q1 enters the saturation conduction state.When input supply voltage fluctuates 48V, remain D1, R2, the common forward voltage stabilizing clamping action of the bi-directional voltage clamp circuit that R3 forms has guaranteed that the voltage at the GS pin two ends of Q1 is clamped at about 12V, the work that Q1 still can be reliable and stable.
In addition, in the present embodiment, because the existence of C1, when direct-current input power supplying just inserted, R1 and C1 had constituted regularly charging circuit of a RC, and the voltage of C1 slowly raises.Have only when the voltage of C1 is elevated to the cut-in voltage of Q1, Q1 just enters conducting state.Voltage along with the GS pin two ends of Q1 progressively raises then, and the conducting internal resistance of Q1 constantly reduces.Up to D1, during the breakdown clamp of the bi-directional voltage clamp circuit that R2, R3 form, Q1 enters the state of saturation conduction fully, has realized the soft start function of reverse-connection preventing circuit.
Further, in the present embodiment, when incorrect link appears in the polarity of direct-current input power supplying, it is the negative pole that VIN+ connects DC power supply, VIN-connects the positive pole of DC power supply, input supply voltage began to raise from 0V when input supply voltage powered on, and this moment is not because the voltage at the GS pin two ends of Q1 reaches cut-in voltage, so Q1 is in off-state.But the parasitic body diode of Q1 is just in time ended according to the connected mode of Fig. 6 at this moment, and direct current is through overload R in the time of can preventing to power on
LForm current circuit with the body diode of Q1, get back to VIN+.Yet in side circuit, because there is the above leakage current of tens UA levels in the parasitic body diode of Q1, in fact VIN-has leakage current and flows to positive pole from the negative pole of the parasitic body diode of Q1, returns VIN+ through D1 and R1.Under this kind state; D1 reference voltage source forward conduction; present the diode current flow characteristic; the D1 forward conduction voltage drop is greatly about-1.0V; the reverse voltage clamp function of having realized; the pressure drop of same D1 can not raise because of the rising of input reverse voltage, and then has realized the reverse over-voltage protecting function of reverse-connection preventing circuit.
Present embodiment provides a kind of reverse-connection preventing circuit, by in the two ends parallel connection of the GS of field effect transistor by reference voltage source and two bi-directional voltage clamp circuits that divider resistance is formed, when forward input overvoltage, by the bi-directional voltage clamp circuit with the voltage clamp at the GS two ends of field effect transistor within normal working voltage, when reverse input overvoltage, by the bi-directional voltage clamp circuit also with the voltage clamp at the GS two ends of field effect transistor within normal working voltage; Present embodiment has solved the input voltage overvoltage of reverse-connection preventing circuit existence in the prior art and the problem that reverse input voltage overvoltage causes metal-oxide-semiconductor to puncture; realize the input over-voltage protecting function of direct current input reverse-connection preventing circuit and oppositely imported over-voltage protecting function; and possesses the circuit soft start function; expand the applied voltage scope of circuit, improved the reliability of circuit.
Fig. 8 is the structural representation of reverse-connection preventing circuit embodiment six of the present invention, and as shown in Figure 8, present embodiment provides a kind of concrete reverse-connection preventing circuit, and the field effect transistor in the present embodiment is specially the NMOS pipe.In the present embodiment, on the basis of above-mentioned embodiment shown in Figure 7, except reference voltage source D1, the first divider resistance R2, the second divider resistance R3, the bi-directional voltage clamp circuit can also comprise the 3rd divider resistance R4 and triode Q0, and it is that example describes that present embodiment still adopts the reference voltage source of TL431.In the present embodiment, be that 24V is that example describes with the input voltage, Q0 chooses the PNP triode, and R2, R3 are as the resistor voltage divider network of D1 reference voltage source, and R4 is as the load resistance of D1 and the biasing resistor of PNP triode Q0.Wherein, the 3rd divider resistance R4 is connected in the branch road of the reference voltage source D1 in parallel with the first divider resistance R2 and the second divider resistance R3, and be connected between the negative pole K of positive source VIN+ and reference voltage source D1, the base stage B of triode Q0 is connected between the negative pole K of the 3rd divider resistance R4 and reference voltage source D1; The collector electrode C of triode Q0 is the positive pole of bi-directional voltage clamp circuit, and the emitter E of triode is the negative pole of bi-directional voltage clamp circuit.
In the present embodiment, among three pin G, the S and D of NMOS pipe, G is a grid, and S is a source electrode, and D is drain electrode.Wherein between the GS pin not during making alive, the resistance R DSon infinity between D pin and the S pin is equivalent to power path is disconnected, and GS pin voltage is greater than opening electric V
ThThe time, resistance R DSon reduces to the resistance value of several milliohms fast between DS, is equivalent to switch closure.Wherein, cut-in voltage V
ThBe the intrinsic parameter of metal-oxide-semiconductor device.In addition, there is parasitic body diode in the NMOS pipe, and when NMOS managed not conducting, electric current can pass through from body diode.In the present embodiment, the grid G of NMOS pipe Q1 and the emitter E of PNP triode Q0, resistance R 4, an end of resistance 2 connects; NMOS pipe Q1's; The drain D of NMOS pipe Q1 links to each other with power cathode VIN-; The source S of NMOS pipe Q1 and the collector electrode C of PNP triode Q0 and the anodal A of D1 reference voltage source TL431 and the end of divider resistance R3 link to each other, and pass through load resistance R
LVIN+ links to each other with positive source; The positive pole of the body diode of NMOS pipe Q1 links to each other with the source S of Q1, and its negative pole links to each other with the drain D of Q1.The base stage B of NPN triode Q0 links to each other with the negative pole K of reference voltage source D1 and current-limiting resistance R4; The benchmark pin R of reference voltage source D1 links to each other with the end of divider resistance R2 and R3, and the divider resistance R2 other end is connected to the grid G of NMOS pipe Q1; The divider resistance R3 other end is connected to the source S of NMOS pipe Q1.Delay capacitor C1 is connected respectively to the grid G of NMOS pipe Q1 and the source S of NMOS pipe Q1.
Wherein, when DC power supply polarity correctly connected, promptly VIN+ connect the positive pole of DC power supply, and VIN-connects the negative pole of DC power supply, and when power supply electrifying, input supply voltage begins to raise from 0V, and this moment is not because the voltage at the GS pin two ends of Q1 reaches the cut-in voltage V of Q1
Th, then Q1 is in off-state.But owing to have parasitic body diode among the Q1, and according to the connected mode among Fig. 8, dc power anode VIN+ was through load resistance R when input supply voltage powered on
LForm current circuit with the body diode of Q1, get back to dc power cathode VIN-.And at the initial stage that powers on of DC power supply, because input supply voltage is lower, load resistance can't be worked, and load current is less, even electric current by the body diode of Q1, can not cause pressure drop loss too big on the Q1 yet.
Along with the continuation rising of input supply voltage, input supply voltage carries out current limliting by R1, is applied to Q0, and R4 is between the GS pin of R2 and R3 resistor voltage divider network, C1 and Q1.Because the existence of capacitor C 1, the voltage at capacitor C 1 two ends is slowly to raise, this moment is because the voltage at C1 two ends is applied to the puncture voltage that the voltage of resistor voltage divider network R2 and R3 also is not enough to be elevated to the benchmark R of D1 (D1 reference voltage=2.5V), therefore D1 presents open-circuit condition, the base stage of PNP three utmost point Q0 can not get voltage bias, and Q0 presents open-circuit condition.Through the regular hour, when the voltage of C1 continued to be elevated to the cut-in voltage of Q1, Q1 entered conducting state.After Q1 enters conducting state, internal resistance between its D pin and the S pin reduces rapidly from infinity, and the pressure drop between the DS pin reduces rapidly, when the pressure drop between the DS pin is reduced to less than 1V, the parasitic body diode of Q1 because the biasing of discontented afc voltage and by, the principal current of electric power loop all should flow through between the DS pin of Q1, no longer conducting and flow through electric current of parasitic body diode.
After Q1 began conducting, because the underfill of delay capacitor C1 electric charge, it is minimum that the conducting internal resistance of Q1 does not also reach, this moment, the filter capacitor of load circuit began charging, and, realized slow startup function of supplying power because Q1 internal resistance restriction has suppressed the unexpected increase of impulse current.Along with the voltage at the GS pin two ends of Q1 rises gradually, the conducting internal resistance of Q1 constantly reduces, voltage on resistance pressure-dividing network R2 and the R3 also constantly raises at this moment, when the voltage at back-pressure resistance networking rises to 12V, through R2, the dividing potential drop of R3, when the benchmark pin R of D1 reference voltage source had reached 2.5V voltage, D1 entered conducting state by ending.Because the conducting of D1, voltage drop has appearred in R4, and the BE interpolar of Q0 obtains forward bias, Q0 is by by entering conducting state, and in a single day Q0 enters conducting state, the be equivalent to short circuit grid G of NMOS pipe Q1 and the voltage between the source S, the GS voltage of Q1 is no longer risen, then descend.Cause when the GS of Q1 voltage descends, the voltage of divider resistance R2 and R3 descends, and makes the R pin dividing potential drop of D1 drop to 2.5V when following, and D1 transfers cut-off state to by conducting, and ending of D1 caused ending of Q0.Grid G and the voltage between the source S by having caused NMOS pipe Q1 again of Q0 go up.Go round and begin again like this, D1 and Q0 circulation conducting and end, the GS voltage positive clamping that has guaranteed NMOS pipe Q1 guarantees that Q1 enters saturation conduction, conducting internal resistance minimum about 12V.This moment, Q1 finished slow starting state, entered normal saturation conduction state.
If this moment, fluctuation appearred in input direct voltage, input supply voltage continues to raise, the voltage of divider resistance R2 and R3 also raises, be applied to the voltage of D1 benchmark R pin in case surpass 2.5V, will cause the Q0 conducting, and then reduce the voltage of divider resistance R2 and R3, and finally make the voltage at the GS pin two ends of Q1 no longer raise and raise along with VIN voltage, avoid the input voltage overvoltage to cause the electric voltage over press at the GS pin two ends of Q1 to puncture and burnt Q1.When direct-current input power supplying voltage reaches 24V, D1, Q0, R2, R3, the acting in conjunction of the bi-directional voltage clamp circuit that R4 forms is clamped at about 12V the voltage at the GS pin two ends of Q1, and Q1 enters the saturation conduction state.When input supply voltage fluctuates 48V, remain D1, Q0, R2, R3, the common forward voltage stabilizing clamping action of the bi-directional voltage clamp circuit that R4 forms, the voltage of having guaranteed the GS pin two ends of Q1 is clamped at about 12V, the work that Q1 still can be reliable and stable.
In addition, in the present embodiment, because the existence of C1, when direct-current input power supplying just inserted, R1 and C1 had constituted regularly charging circuit of a RC, and the voltage of C1 slowly raises.Have only when the voltage of C1 is elevated to the cut-in voltage of Q1, Q1 just enters conducting state.Voltage along with the GS pin two ends of Q1 progressively raises then, and the conducting internal resistance of Q1 constantly reduces.Up to D1, Q0, R2, during the breakdown clamp of the bi-directional voltage clamp circuit that R3, R4 form, Q1 enters the state of saturation conduction fully, has realized the soft start function of reverse-connection preventing circuit.
Further, in the present embodiment, when incorrect link appears in the polarity of direct-current input power supplying, it is the negative pole that VIN+ connects DC power supply, VIN-connects the positive pole of DC power supply, input supply voltage began to raise from 0V when input supply voltage powered on, and this moment is not because the voltage at the GS pin two ends of Q1 reaches cut-in voltage, so Q1 is in off-state.But the parasitic body diode of Q1 is just in time ended according to the connected mode of Fig. 8 at this moment, and direct current is through overload R in the time of can preventing to power on
LForm current circuit with the body diode of Q1, get back to VIN+.Yet in side circuit, because there is the above leakage current of tens UA levels in the parasitic body diode of Q1, in fact VIN-has leakage current and flows to positive pole from the negative pole of the parasitic body diode of Q1, returns VIN+ through D1 and R1.Under this kind state; D1 reference voltage source forward conduction; present the diode current flow characteristic; the D1 forward conduction voltage drop is greatly about-1.0V; the reverse voltage clamp function of having realized; the pressure drop of same D1 can not raise because of the rising of input reverse voltage, and then has realized the reverse over-voltage protecting function of reverse-connection preventing circuit.
Present embodiment provides a kind of reverse-connection preventing circuit, by in the two ends parallel connection of the GS of field effect transistor by reference voltage source, triode and three bi-directional voltage clamp circuits that divider resistance is formed, when forward input overvoltage, by the bi-directional voltage clamp circuit with the voltage clamp at the GS two ends of field effect transistor within normal working voltage, when reverse input overvoltage, by the bi-directional voltage clamp circuit also with the voltage clamp at the GS two ends of field effect transistor within normal working voltage; Present embodiment has solved the input voltage overvoltage of reverse-connection preventing circuit existence in the prior art and the problem that reverse input voltage overvoltage causes metal-oxide-semiconductor to puncture; realize the input over-voltage protecting function of direct current input reverse-connection preventing circuit and oppositely imported over-voltage protecting function; and possesses the circuit soft start function; expand the applied voltage scope of circuit, improved the reliability of circuit.
Present embodiment also provides a kind of communication apparatus, can comprise arbitrary described reverse-connection preventing circuit among above-mentioned Fig. 3-Fig. 8, and communication apparatus can comprise the switch that needs DC power supply input and router etc.
Fig. 9 is the flow chart of reverse-connection preventing processing method embodiment of the present invention, and as shown in Figure 9, the reverse-connection preventing processing method that present embodiment provides can specifically adopt the reverse-connection preventing circuit shown in above-mentioned Fig. 3-Fig. 8, and the concrete operation principle and the course of work repeat no more herein.The reverse-connection preventing processing method that this enforcement provides specifically can comprise the steps:
Further; the reverse-connection preventing processing method that present embodiment provides can also comprise the steps: step 902; when oppositely importing overvoltage; is the second protection voltage by described bi-directional voltage clamp circuit with the grid-source voltage clamp of described field effect transistor, and the described second protection voltage is the normal working voltage of described field effect transistor.
Further, the reverse-connection preventing processing method that present embodiment provides can also comprise the steps: step 903, when input voltage powers on, will be applied to input voltage on the described field effect transistor by the delay capacitor that is connected in parallel with described bi-directional voltage clamp circuit and delay to start and handle.
It is pointed out that in the present embodiment, do not have strict sequential relationship between the above-mentioned steps 901-903, more than three steps can carry out simultaneously, can also carry out in proper order according to the actual conditions transposing, repeat no more herein.
Present embodiment provides a kind of reverse-connection preventing processing method, by at the two ends of the GS of field effect transistor bi-directional voltage clamp circuit in parallel, when forward input overvoltage, by the bi-directional voltage clamp circuit with the voltage clamp at the GS two ends of field effect transistor within normal working voltage, when reverse input overvoltage, by the bi-directional voltage clamp circuit also with the voltage clamp at the GS two ends of field effect transistor within normal working voltage; Present embodiment has solved the input voltage overvoltage of reverse-connection preventing circuit existence in the prior art and the problem that reverse input voltage overvoltage causes metal-oxide-semiconductor to puncture; realize the input over-voltage protecting function of direct current input reverse-connection preventing circuit and oppositely imported over-voltage protecting function; and possesses the circuit soft start function; expand the applied voltage scope of circuit, improved the reliability of circuit.
One of ordinary skill in the art will appreciate that: all or part of step that realizes said method embodiment can be finished by the relevant hardware of program command, aforesaid program can be stored in the computer read/write memory medium, this program is carried out the step that comprises said method embodiment when carrying out; And aforesaid storage medium comprises: various media that can be program code stored such as ROM, RAM, magnetic disc or CD.
It should be noted that at last: above embodiment only in order to technical scheme of the present invention to be described, is not intended to limit; Although with reference to previous embodiment the present invention is had been described in detail, those of ordinary skill in the art is to be understood that: it still can be made amendment to the technical scheme that aforementioned each embodiment put down in writing, and perhaps part technical characterictic wherein is equal to replacement; And these modifications or replacement do not make the essence of appropriate technical solution break away from the spirit and scope of various embodiments of the present invention technical scheme.
Claims (11)
1. reverse-connection preventing circuit; it is characterized in that; comprise the voltage bias resistance that is connected between positive source and the power cathode; bi-directional voltage clamp circuit and at least one field effect transistor; wherein; described voltage bias resistance links to each other with the grid of described field effect transistor; be used for described field effect transistor is carried out turn-on bias; described bi-directional voltage clamp circuit is connected in the two ends of the gate-to-source of described field effect transistor in parallel; described bi-directional voltage clamp circuit is used for when forward input overvoltage; with the grid-source voltage clamp of described field effect transistor is the first protection voltage, and the described first protection voltage is the normal working voltage of described field effect transistor.
2. circuit according to claim 1; it is characterized in that; described bi-directional voltage clamp circuit also is used for when reverse input overvoltage, is the second protection voltage with the grid-source voltage clamp of described field effect transistor, and the described second protection voltage is the normal working voltage of described field effect transistor.
3. circuit according to claim 2 is characterized in that, also comprises:
Delay capacitor is connected in parallel with described bi-directional voltage clamp circuit, is used for when input voltage powers on, and the input voltage that is applied on the described field effect transistor is delayed the startup processing.
4. circuit according to claim 3 is characterized in that, described bi-directional voltage clamp circuit is voltage comparator circuit, voltage stabilizing didoe, voltage suppressor.
5. circuit according to claim 3 is characterized in that, described bi-directional voltage clamp circuit comprises interconnective reference voltage source, first divider resistance and second divider resistance; Described first divider resistance of series connection and described second divider resistance and described reference voltage source are connected in parallel mutually, and the benchmark pin of described reference voltage source is connected between described first divider resistance and described second divider resistance; The positive pole of the just very described bi-directional voltage clamp circuit of described reference voltage source, the negative pole of described reference voltage source are the negative pole of described bi-directional voltage clamp circuit.
6. circuit according to claim 5 is characterized in that, described bi-directional voltage clamp circuit also comprises triode and the 3rd divider resistance; Described the 3rd divider resistance is connected in the branch road of the described reference voltage source in parallel with described first divider resistance and described second divider resistance, and be connected between the negative pole of described positive source and described reference voltage source, the base stage of described triode is connected between the negative pole of described the 3rd divider resistance and described reference voltage source; The positive pole of the very described bi-directional voltage clamp circuit of the current collection of described triode, the negative pole of the very described bi-directional voltage clamp circuit of the emission of described triode.
7. according to each described circuit among the claim 4-6, it is characterized in that, when described field effect transistor is N ditch channel metal-oxide semiconductor field effect transistor, the grid of described field effect transistor links to each other with the negative pole of described bi-directional voltage clamp circuit, and links to each other with described positive source by voltage bias resistance; The drain electrode of described field effect transistor links to each other with described power cathode; The source electrode of described field effect transistor links to each other with the positive pole of described bi-directional voltage clamp circuit, and links to each other with described positive source by load resistance; The positive pole of the body diode of described field effect transistor links to each other with the source electrode of described field effect transistor, and its negative pole links to each other with the drain electrode of described field effect transistor; Perhaps
When described field effect transistor was P ditch channel metal-oxide semiconductor field effect transistor, the grid of described field effect transistor linked to each other with the positive pole of described bi-directional voltage clamp circuit, and linked to each other with described power cathode by voltage bias resistance; The source electrode of described field effect transistor links to each other with the negative pole of described bi-directional voltage clamp circuit, and links to each other with described positive source; The drain electrode of described field effect transistor links to each other with described power cathode by load resistance; The positive pole of the body diode of described field effect transistor links to each other with the source electrode of described field effect transistor, and its negative pole links to each other with the drain electrode of described field effect transistor.
8. a reverse-connection preventing processing method is characterized in that, comprising:
When forward input overvoltage; the bi-directional voltage clamp circuit at the two ends of the gate-to-source by being connected in field effect transistor in parallel is the first protection voltage with the grid-source voltage clamp of described field effect transistor, and the described first protection voltage is the normal working voltage of described field effect transistor.
9. method according to claim 8 is characterized in that, also comprises:
When reverse input overvoltage, be the second protection voltage by described bi-directional voltage clamp circuit with the grid-source voltage clamp of described field effect transistor, the described second protection voltage is the normal working voltage of described field effect transistor.
10. method according to claim 8 is characterized in that, also comprises:
When input voltage powers on, will be applied to input voltage on the described field effect transistor by the delay capacitor that is connected in parallel with described bi-directional voltage clamp circuit and delay to start and handle.
11. a communication apparatus is characterized in that, comprises each described reverse-connection preventing circuit among the claim 1-7.
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| CN110098605A (en) * | 2018-01-31 | 2019-08-06 | 上海安浦鸣志自动化设备有限公司 | One kind being based on PMOS tube low-voltage DC supply drive power supply reverse-connection preventing circuit |
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| CN110380387A (en) * | 2019-07-26 | 2019-10-25 | 中国南方电网有限责任公司超高压输电公司 | A kind of fault secure circuit of power module |
| CN110429579A (en) * | 2019-08-26 | 2019-11-08 | 珠海格力电器股份有限公司 | Reverse connection prevention protection circuit and method for improving safety and direct current power grid system |
| CN110470037A (en) * | 2019-08-01 | 2019-11-19 | 广东美的制冷设备有限公司 | Reverse-connection preventing circuit, method, apparatus and the air conditioner of convertible frequency air-conditioner power supply line |
| CN110509772A (en) * | 2018-05-22 | 2019-11-29 | 联合汽车电子有限公司 | Accessory power supply |
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| CN112055923A (en) * | 2018-05-15 | 2020-12-08 | 大陆-特韦斯贸易合伙股份公司及两合公司 | Circuit arrangement for protecting electronic components |
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| CN113422361A (en) * | 2021-06-09 | 2021-09-21 | 宁波普瑞均胜汽车电子有限公司 | Input reverse connection prevention circuit for vehicle |
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| CN113644876A (en) * | 2021-08-12 | 2021-11-12 | 阳光新能源开发有限公司 | Photovoltaic power generation system and photovoltaic module's protection circuit |
| CN115313345A (en) * | 2022-10-12 | 2022-11-08 | 成都新欣神风电子科技有限公司 | Reverse connection prevention protection circuit for direct-current power supply |
| CN117175487A (en) * | 2023-11-02 | 2023-12-05 | 江苏慕林智造科技股份有限公司 | Short-circuit protection circuit, method and readable storage medium |
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Application publication date: 20101027 |